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Camera Auto FocusPresentation 7, March 7th, 2007
Team W1:Tom Goff (W11)David Hwang (W12)Kate Killfoile (W13)Greg Look (W14)
Design Manager: Bowei GaiProject Goal: Design a low-power, small auto focus chip for
a camera or other hand-held device
Status
• Last Time– Schematic testing– Control logic structural Verilog
• This WeekRigorous schematic testingControl logic structural VerilogSub-module layout
• In Process…LayoutExtraction, LVSControl logic
• UnfinishedPost-layout simulation
Design Decisions
• Concentrated on layout decisions
Same Transistor Count
Component Full Chip Count
AG Preprocessor 2,274
Delta I Preprocessor 2,624
FP multiplier 5,832
FP adder 994
Power control ~1,000
Buffers 2,000
Total ~17,182
Modified SERF Adder
Power Analysis:
Normal 5 gate FA: ~16 uW
T gate FA: 9.127 uW
SERF: 6.834 uW
Adder Layout
Wang’s XOR and XNOR
Int to Float
Integer Compare
Floating Point Compare
Sample Shifter
AG Preprocessor
Floating Point Adder
Muxes
Integer Multiplier…so far
Next Steps
• Spring Break!• Continue laying out, extracting and LVS’ing
modules• Complete control logic
Problems
• Beginning to realize how useful floorplanning is; difficult to follow it
• Other professors; selfishly want us to work on their class
• Curiosity about “glass” layer caused 2450 DRC errors *cough* Greg *cough*
Problems II
• XORs and XNORs named Wang; endless amusement for mature group members
Questions
References
• None this week