Embed Size (px)
Citation preview
1
Architectures and Tools for the Design of Reconfigurable Radio Systems
Olivier Sentieys IRISA/INRIA – CAIRN Project-Team
Joint team with INRIA, CNRS Université de Rennes 1 and ENS Cachan
2 2
Agenda What is inside a (reconfigurable) radio
system (terminal and base-station) ? Some challenges Reconfigurable architectures Design, prototyping and compilation On-going and past projects
3G/4G, MIMO Wireless Sensor Networks
Other research activities CAIRN project-team
A cairn in Bréhat
2
3 3
Wireless Communications Systems What is inside a radio system nowadays ?!
a hardware platform!• heterogeneous (GPP, DSP, FPGA) !• mixed A/D, RF!• domain or application specific!• use off-the-shelf and specific components!
and a lot of embedded software!• spectrum management, middleware!
Specific constraints ! Energy and power consumption! Cost, re-use! Limited resources, real-time! Reliability, security!
4 4
Generic Node Architecture
Battery DC/DC conv.
Processor Coprocessor
RAM Flash
Tranceiver
Power management
Radio
Digital Processing
Memory
Physical Sensing
Sensor Actuator
A/D D/A
3
5 5
Generic Node Architecture
PHY
MAC
LINK
NET APPLICATION
SW
Infrastructure
hardware
abstraction,
middleware, API
HW Infrastructure
7 7
Challenges and Limitations High-performance applications
e.g. 802.11n MIMO, OFDM, WCDMA… Energy and Power constraints
Battery life, manufacturing cost Rapidly changing application standards
SW updates, multi-modes “Software Radio”
Technological impacts Manufacturing reliability issues, transient errors,
silicon bugs
4
8 8
A road for reconfigurable chips
Dynamically adapt the hardware to the application energy-performance-cost
trade-off error and fault tolerance
Self-adapting devices continuously adapt to
changing environments Fresh SoC from CEA with DART IP from IRISA
“Flexible Software on Flexible Hardware”
9 9
Processing Model
T3
T1
T2b T2a T2c
RA4
t
T1
T2a
T3
T2b
RA: Reconfigurable Area CM: Configuration Management
RA5
RA2 RA3 RA1
T2c
5
10 10
CAIRN Research Objectives Take advantage of CAIRN team skills
Compilation, parallelization Architecture, circuit design Signal processing
to design efficient reconfigurable architectures, multi-mode IP
blocks, specialized processors associated compilation or synthesis tools
for wireless communications (mainly)
11 11
Agenda What is inside a (reconfigurable) radio
system (terminal and base-station) ? Some challenges Reconfigurable architectures Design, prototyping and compilation On-going and past projects
3G/4G, MIMO Wireless Sensor Networks
Other research activities CAIRN project-team
A cairn in Bréhat
6
12 12
Related Research Themes Hardware architectures
Dynamic reconfiguration in off-the-shelf FPGA Proposition of new architectures Low-power reconfigurable architectures
Reconfigurable architecture management On-line scheduling and placement Flexible interconnect
Compilation from high-level software code Compilation for reconfigurable architectures Floating-point to fixed-point transformations
13 13
Reconfigurable Architectures Fine-Grain Architectures: FPGA
Configurable interconnection array of • logic blocks, memory, DSP blocks • and processor cores (soft or hard)
Complete system on a programmable chip • Complex design
Example: Xilinx Virtex 5 65 nm, 550 MHz 1100 DMIPS PowerPC 440 528 GMACS, 68/192 GFLOPS 1.25 Gbps LVDS I/O Dynamic reconfiguration
7
14 14
Config Mem. FPGA
Ctrl DMA
Ctrl
RDP1
RDP2
RDP3
RDP4
RDP5
RDP6
Data. Mem.
Segmented N
etwork
reg reg FU1 FU2 FU3 FU4
Fully Connected Network
Data mem1
Data mem2
Data mem3
Data mem4
AG1 AG2 AG3 AG4
Loop Management
Reconfigurable Architectures Coarse-grain architectures
Reconfigurable data-path Dynamic reconfiguration in
a few cycles
Example: DART (IRISA) 3G/UMTS/802.11a 5-10 GOPS/cluster 300 mW @ 200MHz 16 MOPS/mW @ 5 GOPS Simulator, compiler Fabricated circuit in 130nm
15 15
Coarse-Grain Reconfiguration
for (n=0;n<1024;n++){! tmp=0;! for (i=0;i<N;i++){! tmp+=x[i]*h[N-i];! }! y[n]=tmp<<6;! X[0]=x[n]+128;!}!
Irregular Processing few parallelism few regularity less complex
Regular Processing massively parallel very regular complex
8
16 16 16
Reconfiguration management
Spatial schedule t1 t2
T1
Temporal schedule
T2 T3
T4
t0 t1 t2 t3 t4 t5
T1
t6 t7
T2 T3
T4
….
T2
T3
T1
T2 T3
T4 T4
T1
Task graph
Task Ri Ci
T1
T2
T4
Pi
T3
0
1
1 2
3
3
2 5
5
5
5 5
areai
2
12
8 15
17 17
Reconfiguration management Dynamic reconfiguration and allocation of
embedded heterogeneous multiprocessor
Based on neural-networks Scheduling Task placement
Flexible communication management Low-power scheduling policies Fault-tolerant approach
17
9
18 18
Agenda What is inside a (reconfigurable) radio
system (terminal and base-station) ? Some challenges Reconfigurable architectures Design, prototyping and compilation On-going and past projects
3G/4G, MIMO Wireless Sensor Networks
Other research activities CAIRN project-team
A cairn in Bréhat
19 19
Design and compilation tools Goal is to compile from high-level software
towards embedded processors towards reconfigurable area to synthesize specific hardware or to extend the instruction-set of a processor
C to HW tools Source-to-source transformation High-level synthesis
Dataflow (e.g. Simulink) to HW tools Optimization of processing accuracy
10
20 20
Compilation for reconfigurable High-level formal transformations
Loop parallelization and optimization Compilation using complex pattern matching
Generation of data-path configurations Automatic extension of instruction-set Constrained-programming optimizations
21 21
Accuracy Optimization
Fixed-point arithmetic Power and cost but more complex design
Automatic conversion from float to fixed-point Analytical method
Float2Fix tool Accuracy optimization
Optimal structure FWR Matlab toolbox
• e.g. filtering, control
Determination dynamique
Génération code
Application
Front-end
Con
vers
ion
virg
ule
fixe
minSQNR
Fixed-point VHDL
Code C, Matlab type float
DSP, µC ASIC, FPGA
Evaluation précision
()SQNROptimisation
format
Fixed-point C (ac_fixed)
11
22 22
Agenda What is inside a (reconfigurable) radio
system (terminal and base-station) ? Some challenges Reconfigurable architectures Design, prototyping and compilation On-going and past projects
3G/4G, MIMO Wireless Sensor Networks
Other research activities CAIRN project-team
A cairn in Bréhat
23 23
Wireless Sensor Networks Design of an energy-efficient
software stack and hardware platform for wireless sensor networks
Decrease Tx power Optimize radio activity Power optimization of the
hardware Optimize software stack Cooperative MIMO/relay
Base station
Relay
Sensor and relay
Wireless Sensor Network
12
24 24
Cooperative MIMO technique Three phases of cooperative MIMO
communications Phase 1: Local data exchange Phase 2: Cooperative MIMO transmission Phase 3: Cooperative reception
S D MIMO transmission
dm<<d
dm = 1..10 m d
dm
Nt
Nr
25 25
Energy consumption efficiency
Cooperative MIMO technique is more energy efficient than SISO and multi-hop SISO techniques for long distance transmission
T. Nguyen, O. Berder, and O. Sentieys, “Impact of transmission synchronization error and cooperative reception techniques on the performance of cooperative MIMO systems ”, ICC 2008, Beijing, China. T. Nguyen, O. Berder, and O. Sentieys, “Cooperative MIMO schemes optimal selection for wireless sensor networks,” IEEE 65th Vehicular Technology Conference, VTC-Spring, pp. 85–89, 2007.
13
26 26
Rapid Prototyping Real-time demonstrators
FPGA, DSP Reconfigurable SoC
WCDMA/3G system (2002) MIMO/WCDMA (HSUPA)
Flexible hardware architecture • modulation, Nyquist filter, spatio-temporal searcher
and rake, max-ratio combining Real-time prototype of a WCDMA 2-2
• From matlab/simulink simulations • to real-type prototype
base-station, RF front-end, reconfigurable platform T Saidi, S. Roy, O. Sentieys. A testbed for evaluation of MIMO WCDMA architectures, in ISSSE’07, Montréal, Canada, 2007
27 27
Rapid Prototyping
14
28 28
Software Defined Radio (SDR) Flexible arithmetic operators Multi-mode components
Different: modes, parameters, algorithms e.g. channel coding, CDMA
Adaptive architectures dynamically modify the structure of
• the architecture, the algorithm, the accuracy depending on the context
• channel condition, standard, environment e.g. to minimize the dissipated power
29 29
Rapid Prototyping for SDR GNU Radio for Software Radio
15
30 30
MIMO Systems Pre-coding or beamforming
Goal: migrate processing towards base-station Linear pre-coder (max-dmin)
Towards a 4G testbed MIMO/OFDM
• Influence of algorithmic and precision parameters on the quality of transmission and on energy
LTE standard context Suitable for radio-over-fibre
Q. Ngo, O. Berder, and O. Sentieys, “Minimum distance based precoder for MIMO-OFDM systems using a 16-QAM modulation”, ICC 2009, Dresden, Germany.
31 31
Agenda What is inside a (reconfigurable) radio
system (terminal and base-station) ? Some challenges Reconfigurable architectures Design, prototyping and compilation On-going and past projects
3G/4G, MIMO Wireless Sensor Networks
Other research activities CAIRN project-team
A cairn in Bréhat
16
32 32
True Random Number Generation True Random Number Generator
Based on oscillator sampling with random jitter On-chip jitter measurement Embedded statistical tests Suitable for FPGA and ASIC Focus on increasing bit-rate
MIMO channel emulator Collaboration with SmartQuantum
Quantum Cryptography
33 33 CAIRN Team
CAIRN team at a glance IRISA : Institut de Recherche en Informatique et
Systèmes Aléatoires UMR CNRS 6074, INRIA Rennes Nearly 600 people, 31 research teams
CAIRN team 37 people, Lannion (ENSSAT) and Rennes (Campus de
Beaulieu, ENS Cachan) Domain-Specific and Reconfigurable System-on-Chip
(architectures, tools, algorithms) Wireless Communications
Skills in computer science and electronics engineering Compilation, parallelization Architecture, circuit design Signal processing
17
38 38
Summary Reconfigurable architecture for wireless
systems
Adaptive and flexible radio architecture Power consumption constraints Ad hoc wireless sensor networks MIMO Cooperative/relay
