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2013-1224(Reexamination Nos. 95/001,106 and 95/001,131)

IN THEUNITED STATES COURT OF APPEALSFOR THE FEDERAL CIRCUIT

___________

RAMBUS, INC.,Appellant,

v.

MICRON TECHNOLOGY, INC.,Appellee.

___________

Appeal from the United States Patent and Trademark Office,Patent Trial and Appeal Board.___________

BRIEF FOR APPELLANT RAMBUS INC.___________

June 27, 2013

J. Michael JakesJames R. BarneyMolly R. Silfen

Aidan C. SkoylesFINNEGAN,HENDERSON,FARABOW,GARRETT &DUNNER,LLP901 New York Avenue, NW

Washington, DC 20001(202) 408-4000

Attorneys for Appellant Rambus Inc.

Case: 13-1224 Document: 29-1 Page: 1 Filed: 06/27/2013

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CERTIFICATE OF INTEREST

Pursuant to Federal Circuit Rules 27(a)(7) and 47.4(a), counsel for AppellantRambus Inc. certify the following:

1. The full name of every party or amicus represented by us is:

Rambus Inc.

2. The name of the real party in interest (if the party named in the caption is not

the real party in interest) represented by us is:

Rambus Inc.

3. All parent corporations and any publicly held companies that own 10 percent or

more of the stock of any party represented by us are:

None

4. The names of all law firms and the partners or associates that appeared for theparties now represented by us in the trial court or are expected to appear in this

Court are:

J. Michael Jakes, Kathleen Daley, James R. Barney, Naveen Modi,

Molly R. Silfen, Aidan C. SkoylesFINNEGAN,HENDERSON,FARABOW,GARRETT &DUNNER, LLP


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TABLE OF CONTENTS

Table of Authorities ...................................................................................................vStatement of Related Cases .................................................................................... viiiStatement of Jurisdiction ............................................................................................1I. Statement of the Issues ....................................................................................2II. Statement of the Case ......................................................................................3III. Statement of Facts ............................................................................................7

A. Procedural HistoryMicron Appealed a Samsung Issue tothe Board that Micron Never Raised in Its Own

Reexamination Request .........................................................................71. The Samsung Reexamination Request .......................................72. The Micron Reexamination Request ..........................................73. The PTOs Merger of the Two Reexaminations .........................84. Samsungs Withdrawal from Reexamination .............................85. The Examiners Decision ............................................................86. The Parties Appeals to the Board ..............................................97. The Boards Ruling that Micron Had Standing to

Appeal Samsungs Issues ..........................................................10B. Facts Relating to the Boards Reversal of the Examiners

Finding that Claims 15 and 16 of the 285 Patent Are NotAnticipated by Bennett ........................................................................111. The 285 Patent .........................................................................112. Background of the Technology-at-Issue ...................................12

a. Dynamic Random Access Memory Devices ..................12b. Asynchronous Versus Synchronous Memory

Devices ...........................................................................13


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c. The Role of Access-Time Registers in theSynchronous Memory Devices of the 285 Patent .........15

3. The Bennett Reference ..............................................................19a. Overview of Bennett .......................................................19b. The Role of Wait Lines in Bennett .............................22c. Timing of Bus Activity in Bennett .................................25

i. Figure 36 ...............................................................25ii. Figure 32 ...............................................................27iii. Figures 25a and 25b .............................................29

4. The Examiners Finding that Bennett Does NotAnticipate Claims 15 and 16 .....................................................33

5. The Boards Decision Reversing the ExaminersFinding that Bennett Does Not Anticipate Claims 15and 16 ........................................................................................34

IV. Summary of Argument ..................................................................................36

V.

Argument .......................................................................................................37

A. The Board Erred in Determining that It Had Jurisdictionover Microns Appeal ..........................................................................371. 35 U.S.C. 315 Does Not Give a Requester the Right

to Appeal Issues Raised by Another Requester inAnother Reexamination, Even If the Reexaminations

Are Merged ...............................................................................372. The PTOs Merger Procedure Cannot Confer

Statutory Rights upon a Party that It Would Not

Otherwise Have Had Absent the Merger ..................................413. Because 35 U.S.C. 315 Clearly Sets Forth the

Limits of the Boards Jurisdiction, the PTO Is NotEntitled to Chevron Deference in Interpreting This

Statute ........................................................................................46


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4. Allowing Micron to Step Into Samsungs Shoes byAppealing Samsungs Reexamination Arguments

Violates the Statutory Prohibition Against a PartyInstituting Simultaneous Inter Partes Reexaminations

of the Same Patent.....................................................................495. The Board Could Not Have Created Jurisdiction over

Microns Appeal by Entering New Grounds of

Rejection of Claims 15 and 16 ................................................50B. The Board Erred in Reversing the Examiners Finding that

Bennett Does Not Disclose a Value Which is

Representative of the Programmable Number of ClockCycles ................................................................................................521. Standards of Review .................................................................52

a. Factual Findings of the Board Are Reviewed forSubstantial Evidence Based on the Entire Record,

Including Any Findings of Fact Made by theExaminer .........................................................................52

b. The Boards Claim Construction Is Reviewed deNovo, and Its Anticipation Finding Is Reviewedfor Substantial Evidence .................................................53

2. The Board Implicitly Misconstrued Representativeas Requiring Only the Ability toAffectthe Numberof Clock Cycles .......................................................................54

3. Under the Correct Claim Construction, the BoardsFindings Lack Substantial Evidence and Are Clearly

Rebutted by the Examiners Contrary Findings .......................58VI. Conclusion .....................................................................................................63


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TABLE OF AUTHORITIES

Cases

Almendarez-Torres v. United States,

523 U.S. 224 (1998) ............................................................................................ 48

Brand v. Miller,

487 F.3d 862 (Fed. Cir. 2007) ...................................................................... 52, 63

Chevron U.S.A. Inc. v. Natural Resources Defense Council, Inc.,467 U.S. 837 (1984) ................................................................................ 46, 47, 48

City of Arlington, Texas v. Federal Communications Commission,No. 11-1545, slip op. (S. Ct. May 20, 2013) ...................................................... 46

Fornaris v. Ridge Tool Co.,

400 U.S. 41 (1970) .............................................................................................. 40

Gechter v. Davidson,116 F.3d 1454 (Fed. Cir. 1997) .................................................................... 52, 53

In re Baker Hughes Inc.,

215 F.3d 1297 (Fed. Cir. 2000) .......................................................................... 53

In re Gartside,

203 F.3d 1305 (Fed. Cir. 2000) .......................................................................... 52

In re Paulsen,30 F.3d 1475 (Fed. Cir. 1994) ............................................................................ 53

In re Stepan Co.,

660 F.3d 1341 (Fed. Cir. 2011) .......................................................................... 51

In re Suitco Surface, Inc.,603 F.3d 1255 (Fed. Cir. 2010) .......................................................................... 53

Johnson v. Manhattan Railway Co.,289 U.S. 479 (1933) ............................................................................................ 44

Kokoszka v. Belford,

417 U.S. 642 (1974) ............................................................................................ 39


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Koninklijke Philips Electronics N.V. v. Cardiac Science Operating Co.,590 F.3d 1326 (Fed. Cir. 2010) .......................................................................... 43

Lujan v. Defenders of Wildlife,

504 U.S. 555 (1992) ............................................................................................ 48

Merck & Co. v. Kessler,80 F.3d 1543 (Fed. Cir. 1996) ............................................................................ 44

New York v. Microsoft Corp.,

2002 WL 318565 (D.D.C. 2002) ........................................................................ 44

Office of Senator Mark Dayton v. Hanson,

550 U.S. 511 (2007) ............................................................................................ 40

Perry Education Assn v. Perry Local Educators Assn,460 U.S. 37 (1983) .............................................................................................. 40

Phillips v. AWH Corp.,

415 F.3d 1303 (Fed. Cir. 2005) .......................................................................... 57

Rite-Hite Corp. v. Kelley Co.,56 F.3d 1538 (Fed. Cir. 1995) ............................................................................ 50

Southern California Federal Savings & Loan Assn v. United States,

51 Fed. Cl. 676 (Fed. Cl. 2002) .......................................................................... 44

St. Clair Intellectual Property Consultants, Inc. v. Canon Inc.,

412 F. Appx 270 (Fed. Cir. 2011) ..................................................................... 53

Sullivan v. Stroop,496 U.S. 478 (1990) ............................................................................................ 40

Syntex (U.S.A.) Inc. v. U.S. Patent & Trademark Office,

882 F.2d 1570 (Fed. Cir. 1989) .......................................................................... 50

Talbert Fuel Systems Patents Co. v. Unocal Corp.,275 F.3d 1371 (Fed. Cir. 2002), vacated and remanded on

other grounds, 537 U.S. 802 (2002) ................................................................... 58

Tehrani v. Hamilton Medical, Inc.,

331 F.3d 1355 (Fed. Cir. 2003) .............................................................. 54, 56, 62


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vii

United States v. Jin Fuey Moy,241 U.S. 394 (1916) ............................................................................................ 48

Universal Camera Corp. v. National Labor Relations Board,

340 U.S. 474 (1951) ............................................................................................ 53

Watson v. Bruns,239 F.2d 948 (D.C. Cir. 1956) ............................................................................ 51

STATUTES

2 U.S.C. 1412 ........................................................................................................ 40

35 U.S.C. 2 .....................................................................................................passim

35 U.S.C. 6 ............................................................................................................ 52

35 U.S.C. 7 ............................................................................................................ 52

35 U.S.C. 141 .......................................................................................................... 1

35 U.S.C. 314 ........................................................................................................ 40

35 U.S.C. 315 .................................................................................................passim

35 U.S.C. 317 .................................................................................................passim

OTHER AUTHORITIES

37 C.F.R. 1.989 ..............................................................................................passim

37 C.F.R. 41.50 ..................................................................................................... 50

37 C.F.R. 41.77 ..................................................................................................... 50

4 Donald S. Chisum, Chisum on Patents 11.06 .................................................... 50

MPEP 2674 ........................................................................................................... 45


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STATEMENT OF RELATED CASES

Rambus is unaware of any other appeals or petitions taken in this

reexamination proceeding. There are, however, a number of different matters

pending in this Court and other courts that involve the patent-at-issue in this

appeal, U.S. Patent No. 6,266,285 (the 285 patent).

1. The following pending cases involve the 285 patent.

a. Rambus Inc. v. Hynix Semiconductor Inc., No. 5:05-cv-00334-

RMW (N.D. Cal.) (Whyte, J.).

b. Rambus Inc. v. Micron Technology, Inc., No. 5:06-cv-00244-

RMW (N.D. Cal.) (Whyte, J.).

2. The following pending cases do not involve the 285 patent but

involve patents that, like the 285 patent, descend from Application No.

07/510,898 (the 898 application).

a. Hynix Semiconductor Inc. v. Rambus Inc., No. 5:00-cv-20905-

RMW (N.D. Cal.) (Whyte, J.). This case is on remand from Appeal Nos. 2009-

1299, -1347, 645 F.3d 1336 (Fed. Cir. 2011).

b. Micron Technology, Inc. v. Rambus Inc., No. 1:00-cv-00792-

SLR (D. Del.) (Robinson, J.). This case is on remand from Appeal No. 2009-1263,

645 F.3d 1311 (Fed. Cir. 2011).


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c. Rambus Inc. v. LSI Corp., No. 3:10-cv-05446-RS (N.D. Cal.)

(Seeborg, J.).

d. Rambus Inc. v. STMicroElectronics, N.V., No. 3:10-cv-05449-

RS (N.D. Cal.) (Seeborg, J.).

3. Several ex parte and inter partes reexaminations involving patents

descended from the 898 application are pending at the U.S. Patent and Trademark

Office (PTO). Of those, the following have been appealed to this Court.

a. In re Rambus Inc., No. 2011-1247, 694 F.3d 42 (Fed. Cir.

2012).

b. Rambus, Inc. v. Kappos, No. 2012-1634 (Fed. Cir.) (briefing

complete).

c. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1087

(Fed. Cir.) (briefing not yet complete).

d. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1192

(Fed. Cir.) (briefing not yet complete).

e. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1228

(Fed. Cir.) (docketed).

f. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1339



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g. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1426



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STATEMENT OF JURISDICTION

This appeal arises from two inter partes reexamination proceedings before

the U.S. Patent and Trademark Office (PTO). Micron Technology, Inc.

(Micron), one of the requesters, appealed the examiners confirmation of the

claims-at-issue to the Board of Patent Appeals and Interferences (Board). The

Board reversed the examiners confirmation of claims 15 and 16 on April 24, 2012,

and Rambus requested rehearing, which the Board denied on November 15, 2012.

The Boards decision was final and appealable. Rambus appealed. This Court has

jurisdiction under 35 U.S.C. 141.


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I. STATEMENT OF THE ISSUES1. Did Micron have standing to appeal an issue to the Board that it never

raised in its reexamination request, where: (1) Micron did not have a statutory right

to appeal that issue prior to the PTOs sua sponte merger of Microns and

Samsungs reexamination proceedings; (2) the PTOs merger procedure is purely

administrative and cannot, by itself, create substantive appeal rights; (3) allowing

Micron to step into Samsungs shoes on appeal violated the principle of 35 U.S.C.

317(a), which prohibits a third-party requester from concurrently pursuing two

inter partes reexaminations of the same patent; and (4) the Board originally ruled

that Micron could not appeal Samsungs issues before reversing itself on that

issue?

2. If the Board had jurisdiction, did it err in reversing the examiners

decision confirming claims 15 and 16 over Bennett, where the examiner had

correctly found that Bennett does not disclose storing a value which is

representative of the programmable number of clock cycles between a write

request and the sampling of data in response to that write request, and where the

Boards reversal of that finding was based on an incorrect construction of

representative and a factually unsupported interpretation of Bennett?


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II. STATEMENT OF THE CASERambus appeals the Boards reversal of the examiners decision confirming

the validity of claims 15 and 16 of the 285 patent over U.S. Patent No. 4,734,909

to Bennett (Bennett). First, the Board lacked jurisdiction over Microns appeal

because Micron appealed only based on anticipation by Bennett, a theory that was

not raised in Microns request for reexamination. Because Micron had no standing

to appeal that issue prior to the PTOs merger of Microns reexamination with

Samsungs, it could not have gained the right to do so merely by virtue of the

PTOs merger. In other words, the PTO does not have the authority to confer

statutory rights on a party through the administrative act of merging two

reexamination proceedings. Moreover, allowing Micron to step into Samsungs

shoes on appeal violated the prohibition of 35 U.S.C. 317(a) that a third-party

requester, having successfully initiated an inter partes reexamination of a patent,

cannot initiate a second inter partes reexamination of that same patent while the

first reexamination is still ongoing. Thus, the Boards decision should be vacated,

and the Board should be ordered to dismiss Microns appeal for lack of

jurisdiction.

Second, even if the Board had jurisdiction over Microns appeal, the Board

erred substantively. The examiner in this inter partes reexamination correctly

concluded that claims 15 and 16 are not anticipated by Bennett because Bennett


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does not disclose storing a value which is representative of the programmable

number of clock cycles that transpire between a write request and the subsequent

sampling of data. (A1078-81.) The examiner specifically rejected the argument

that Micron later adopted on appeal (from Samsung), i.e., that a value indicating

the configuration of wait lines in Bennett somehow satisfies this limitation. (Id.)

As the examiner recognized, and as Micron does not dispute, a wait signal

in Bennett merely indicates whethera device is currently available to receive data;

it does not specify when it will receive data. (A1408[16:51-58].) Thus, a wait

signal is akin to a busy signal on a telephone line, merely informing the requester

that it should try again later at some unspecified time. Recognizing that

transaction-refusal wait signals in Bennett are different than, and essentially the

opposite of, the predetermined delay times recited in claims 15 and 16, Micron

devised a hypertechnical argument based on the configuration of the wait lines in

Bennettnamely, whether they are dedicated or multiplexed.

In one subset of configurations of Bennett, wait signals are transmitted on a

dedicated wait line and can therefore be transmitted simultaneously with incoming

data. By analogy, two cars can pass on a two-lane road because each has its own

dedicated lane. In an alternative subset of configurations of Bennett, wait signals

are sent on a multiplexed line, which is shared by other signals in a time-based,

sequential fashion. This is analogous to two cars traveling in opposite directions


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on a single-lane roadi.e., the cars must take turns. Samsung (and later Micron

after it stepped into Samsungs shoes) argued that the wait-line setting in Bennett

constitutes a value which is representative of the programmable number of clock

cycles to transpire because, ignoring all of Bennetts other settings and their

effects, multiplexing the wait-line signal and data causes the data-transmission

time slot to move by one clock cycle as compared to a dedicated wait-line

configuration. But this argument, which attempts to convert Bennetts wait-line

configuration into a stored, programmable number of clock cycles, is factually

incorrect, as the examiner readily recognized.

As the examiner found, although changing the wait-line configuration in

Bennett can affect when data is sampled (assuming everything else remains

constant), the wait-line configuration itself is not representative of a number of

clock cycles since the number of wait lines [i.e., their configuration] does not

correlate to a specific number of clock cycles. (A1079 (emphasis in original).)

He noted, for instance, that the same wait-line value of 3 (denoting a single,

dedicated wait line) results in different numbers of clock cycles transpiring in the

transactions shown in Figures 25b, 35, and 36. He further noted that different

wait-line configurations can result in the samenumber of clock cycles transpiring,

for instance as shown in the transactions in Figures 25b and 32, which use different


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wait-line settings yet result in the same number of clock cycles transpiring. Thus,

the examiner was correct when he concluded:

[T]he above citations shown in Bennett also makes itclear that the Wait Line does not represent a number of

clock cycles but instead indicates whether data isaccepted or whether the[re] is a need to re-try at a later

time. The Examiner notes that that [sic] based on theprogrammed configuration, the accepting or retrying

causes data to be sampled at different clock cycles,however while the configuration digit changes the

number of clock cycles that must transpire, theconfiguration digit itself is not indicative of the number

of []clock cycles that will have transpired before data issampled.

(A1078 (emphasis in original).)

As the examiner understood (but the Board ignored), many other variables in

Bennett, including arbitration, retry conditions, pin configuration, address block

size, and bus conditions, can affect the time between a write request and data

sampling. Thus, merely knowing the wait-line configuration in Bennett (i.e.,

dedicated versus multiplexed) does not allow one to know the actual number of

clock cycles that will transpire between a given write request and the

corresponding sampling of data, which is a critical feature of the claimed

invention. The examiner correctly recognized this and found that claims 15 and 16

are not anticipated by Bennett. The Board erred in reversing this finding.


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III. STATEMENT OF FACTSA. Procedural HistoryMicron Appealed a Samsung Issue to

the Board that Micron Never Raised in Its Own

Reexamination Request

1. The Samsung Reexamination RequestOn November 6, 2008, Samsung filed a request for inter partes

reexamination of the 285 patent. In its request, Samsung alleged that claims 13,

15, and 16 of the 285 patent were anticipated by Bennett. (A1549.) Samsung also

alleged that claims 13, 15, and 16 were rendered obvious by the JEDEC

Standard in view of U.S. Patent No. 5,590,086 to Park (Park), or by Park in

view of the knowledge of one of ordinary skill in the art.1

(Id.) On January 9,

2009, the PTO ordered reexamination of the 285 patent based on Samsungs

request, assigning it Reexamination Control No. 95/001,106. (A1598.)

2. The Micron Reexamination RequestOn December 31, 2008, Micron filed a separate request for inter partes

reexamination of the 285 patent. In its request, Micron alleged that claims 13, 15,

and 16 of the 285 patent were anticipated by an iAPX Manual and were

rendered obvious by Gustavson, Scalable Coherent Interface Project

(Gustavson), in view of either Bennett or U.S. Patent No. 5,301,278 to Bowater

(Bowater). (A1619, A1634-42.) Notably, Micron didnotallege that claims 13,

1Samsung argued that the 285 patent was not entitled to an effective filing date

earlier than the JEDEC Standard or Park references.


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15, and 16 were anticipated by Bennett, nor did it raise the JEDEC Standard or

Park. On January 22, 2009, the PTO ordered reexamination of the 285 patent

based on Microns request, assigning it Reexamination Control No. 95/001,131.

(A1680.)

3. The PTOs Merger of the Two ReexaminationsOn March 9, 2009, the PTO decided sua sponte to merge the Samsung-

requested reexamination (95/001,106) and the Micron-requested reexamination

(95/001,131) into a consolidated proceeding pursuant to 37 C.F.R. 1.989.

(A1693.)

4. Samsungs Withdrawal from ReexaminationOn February 11, 2010, Samsung filed a notice of nonparticipation in inter

partesReexamination Control No. 95/001,106, stating that it no longer intends to

participate in the present reexamination. (A1698.)

5. The Examiners DecisionOn June 23, 2010, after considering all the arguments presented by Samsung

and Micron, the examiner declined to adopt Microns anticipation argument based

on the iAPX Manual or its obviousness arguments based on Gustavson in view of

Bennett or Bowater. (A1105-06.) The examiner also declined to adopt Samsungs

obviousness arguments based on the JEDEC Standard and Park. (A1101-02.) The

examiner adopted Samsungs anticipation argument based on Bennett, but only for

claim 13, declining to maintain the Bennett rejection for claims 15 and 16.


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(A1102-04.) Thus, at the end of prosecution, the examiner rejected claim 13 as

anticipated by Bennett (an argument raised only by Samsung) and sustained claims

15 and 16.

6. The Parties Appeals to the BoardBecause Samsung had already withdrawn from the reexamination and was

no longer participating, it did not appeal the examiners confirmation of claims 15

and 16 over Bennett.

Micron, however, appealed the examiners confirmation of claims 15 and 16

of the 285 patent. Specifically, in its appeal brief to the Board, Micron challenged

the examiners findings that (1) claims 15 and 16 are not anticipated by Bennett;

(2) claims 13, 15, and 16 are entitled to the earlier filing date of the 285 patents

parent application; (3) claims 13, 15, and 16 are not rendered obvious by the

JEDEC Standard in view of Park; and (4) claims 13, 15, and 16 are not rendered

obvious by Park in view of the knowledge of one of ordinary skill in the art.

(A1742.) Notably, all of thesearguments were originally raised by Samsung, not

Micron. Micron did not appeal any of its own issues, i.e., the examiners

nonadoption of Microns proposed rejections based on the iAPX Manual or

Gustavson in view of Bennett or Bowater. (Id.) In short, Micron attempted to step

into Samsungs shoes, taking up issues that only Samsung had raised and that only


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Samsung had a statutory right to appeal. Or, to use another analogy, Micron

attempted to switch horses in the middle of the race.

7. The Boards Ruling that Micron Had Standing toAppeal Samsungs Issues

Rambus filed a petition to expunge Microns appeal brief on the ground that

Micron lacked standing to appeal arguments that had been raised only by Samsung,

a nonparticipating party. (A2033.) On June 17, 2011, the Board denied Rambuss

petition. The Board held that the origin of a patentability issue is immaterial to a

requesters right to raise the issue on appeal, citing its earlier decision in merged

proceeding 95/000,250 and 95/001,124. (A2084 (citing A20003-05).) That earlier

decision refers, in turn, to the Boards February 16, 2011, reconsideration decision

in merged proceeding 95/001,026 and 95/001,128 (A20009),2

and its April 15,

2011, decision in merged proceeding 95/000,183 and 95/001,112 (A20017). In its

substantive briefs, Rambus also raised Microns lack of standing (A1782-84), and

the Board addressed the issue in its substantive decisions, relying primarily on its

petition decision (A32-33; A4-5). Finding that it had jurisdiction, the Board then

proceeded to decide the merits of Microns appeal.

2This reconsideration decision overturned the December 13, 2010, decision of the

Board in merged proceeding 95/001,026 and 95,001,128, in which the Board

expunged Microns appeal brief and correctly held that, in a notice of appeal

(or cross appeal), a requester is limited to presenting rejections previouslyproposed by that third party requester. (A20028 (emphasis in original).)


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B. Facts Relating to the Boards Reversal of the ExaminersFinding that Claims 15 and 16 of the 285 Patent Are Not

Anticipated by Bennett

1. The 285 PatentThe 285 patent is titled Method of Operating a Memory Device Having

Write Latency. (A60.) In general, it discloses [a]n integrated circuit bus

interface for computer and video systems . . . which allows high speed transfer of

blocks of data, particularly to and from memory devices, with reduced power

consumption and increased system reliability. (A78[1:20-24].)

One focus of the 285 patent is to make the memory system more efficient

so that data can be transferred faster than was possible in the prior art. This is

accomplished, in part, by: (1) employing a synchronous memory interface, i.e.,

one that utilizes an external clock signal to govern memory transactions; and

(2) storing a value indicating how many clock cycles are to elapse between a write

request and the corresponding sampling of data.

Claims 15 and 16 of the 285 patent, the sole claims-at-issue in this appeal,

depend from independent claim 13, and recite as follows:

13. A method of operation in a memory device having a

section of memory which includes a plurality of memorycells, the method comprising:

receiving an external clock signal;

receiving a request for a write operation synchronously

with respect to the external clock signal; and


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sampling data, in response to the request for a writeoperation, after a programmable number of clock cycles

of the external clock signal transpire.

15. The method of claim 13 further including storing a

value which is representative of the programmablenumber of clock cycles of the external clock in aprogrammable register on the memory device.

16. The method of claim 15 further including receiving a

set register request, wherein in response to the set registerrequest, the memory device stores the value in the

register.

(A90[25:41-50, 57-64] (emphasis added).)

2. Background of the Technology-at-Issuea. Dynamic Random Access Memory Devices

The improvements of the 285 patent, while applicable to many types of

memory devices, are particularly applicable to dynamic random access memory

devices or DRAMs. (A78[1:48-58].) A DRAM stores information in memory

cells for a computer system. These memory cells are typically arranged in a two-

dimensional array containing many memory cells. (A89[23:43-47].) Each

memory cell contains a capacitor that stores a charge representing one bit of

information; for example, a charged capacitor may represent a 1, while an

uncharged capacitor may represent a 0. (A78[1:59-63].)

A computer typically has many DRAMs controlled by a single memory

controller. (A78[2:9-12].) Information and control signals flowing between the


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memory controller and the numerous DRAMs can travel on a bus, consisting of

a series of wires or lines that connect the devices. (A78[2:30-33].)

b. Asynchronous Versus Synchronous MemoryDevices

Prior to 1990 (the effective filing date of the 285 patent), conventional

DRAMs operated asynchronously, i.e., without being synchronized with an

external clock signal. (A79[3:7-13].) Because the control lines that signal read

and write operations must continually signal the asynchronous DRAM throughout

the transfer, there was no way to temporally decouple a write operation from the

write data. The data transfers associated with read and write operations were

conducted as soon as the memory controller drove certain control signal transitions

on specific bus lines and the DRAMs were able to respond to those control signals.

(A78[2:7-19].)

In contrast, the DRAMs disclosed in the 285 patent are synchronous

(A81[8:43-58]), which means they operate markedly differently from prior-art

asynchronous DRAMs. The hallmark of a synchronous DRAM is that an external

clock signal governs the timing of the read and write operations. (A81[8:29-30].)

In a synchronous system, at least one signal line carries an external clock signal,

such as the one shown below from Figure 14 of the 285 patent, which is used to

synchronize all read and write operations for all the DRAMs in the system.


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(A75[Fig. 14].)

In this manner, the memory controller and its DRAMs operate

synchronously with each other. In such a system, the memory controller can

issue a request for a write operation to a particular DRAM at a given clock cycle

and further specify that the requested data must be sampled a precise number of

clock cycles later. (A85[15:63-16:10].) Then, after that precise number of clock

cycles has elapsed, that DRAM can sample the data on the bus lines and know that

it is the data associated with the earlier write request. (Id.) Meanwhile, in the

intervening clock cycles, the memory controller can issue another request to

another DRAM and start another access while the first DRAM is working to

process the first write. (Id.) In this way, transactions can be interleaved and pre-

scheduled to occur at certain times, i.e., after a certain number of clock cycles.

(Id.)

To understand why interleaving is desirable, it is important to remember that

read and write operations take time and that a memory bus has only a limited

number of lines to carry all the necessary control signals and data between the

memory controller and multiple DRAMs. (A85[15:63-16:2].) If the bus lines are

tied up during a particular transaction with one DRAM (as they were in prior-art


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asynchronous systems), they are not available for other transactions that the

memory controller may wish to execute. However, if the delay time between a

write request and the corresponding sampling can be precisely known (e.g., the

data for writing will be sampled in exactly X clock cycles), then during the

intervening clock cycles, the memory controller can issue other requests or

send/receive data corresponding to previous requests. This increases the overall

efficiency of the system. (See A81[7:8-18].)

c. The Role of Access-Time Registers in theSynchronous Memory Devices of the 285 Patent

The 285 inventors realized that, in order to interleave read and write

transactions in a synchronous memory system, there must be an external clock

signal to which all DRAM transactions are synchronizedandthe controller issuing

the read and write requests must know the precise amount of time that will

transpire between each request and when a particular memory device will begin

outputting or receiving the requested data. (A85[15:63-16:10].) Their solution

was to include a set of DRAM internal registers, as shown in Figure 16, that

contains one or more access-time registers 173 specifying one or more delay

times for each individual memory device:


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(A77[Fig. 16].)

The 285 patent describes these access-time registers as follows:

With reference to FIG. 16, each semiconductor device

contains a set of internal registers 170, preferably

including a device identification (device ID) register 171,a device-type descriptor register 174, control registers175 and other registers containing other information

relevant to that type of device. In a preferredimplementation, semiconductor devices connected to the

bus contain registers 172 which specify the memoryaddresses contained within that device and access-time

registers 173 which store a set of one or more delay

times at which the device can or should be available to

send or receive data.

(A80[6:28-39] (emphasis added).)

In a preferred embodiment of the invention, read and write requests are

issued as part of a request packet, an example of which is illustrated in Figure 4:


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(A65[Fig. 4].)

Part of the request packet in Figure 4 is an AccessType field, which

indicates the type of request that is being issued, where different types of requests

may have different response timings when multiple access-time registers are

provided. (A82[9:57-59].) The 285 patent explains this concept as follows:

The AccessType field [of the request packet] specifies

whether the requested operation is a read or write and the

type of access, for example, whether it is to the control

registers or other parts of the device, such as memory. . . .AccessType[1:2] preferably indicates the timing of the

response, which is stored in an access-time register,

AccessRegN.

(A82[9:47-59] (emphasis added).)

Thus, the 285 patent discloses a synchronous memory system having an

external clock signal that governs the timing of read/write requests and the


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responses to those requests. In a preferred embodiment, when the memory

controller wishes to issue a read or write request to a particular memory device, it

assembles a request packet that includes the type of access. The timing of the

response by the memory device is known based on the value stored in the access-

time register that corresponds to the type of access specified (e.g., data for write

requests for this device should be sampled in X bus cycles). (A82[9:16-19].) In

this manner, once the write request has been issued, the controller will know that it

has exactly X bus cycles during which it can process other memory transactions

before the memory device begins sampling data to be written. This allows for

interleaving, which improves the overall efficiency of the system, as explained

above. (See also A81[7:8-18].)

The use of access-time registers also reduces the complexity of the memory

devices themselves (sometimes referred to as slaves), as the 285 patent

explains:

To reduce the complexity of the slaves [e.g., memory

devices], a slave should preferably respond to a request

in a specified time, sufficient to allow the slave to beginor possibly complete a device-internal phase including

any internal actions that must precede the subsequent bus

access phase.

(A81[8:48-52].)

The 285 patent also explains how to choose and set appropriate access

times for a given memory device:


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The value stored in a slave access-time register 173 ispreferably one-half the number of bus cycles for which

the slave device should wait before using the bus inresponse to a request. Thus an access time value of 1

would indicate that the slave should not access the busuntil at least two cycles after the last byte of the request

packet has been received.

(A85[15:63-16:8].) Thus, the values stored in the access-time registers have a

direct correlation to the request-to-sampling access times they represent. For

instance, in the preferred embodiment, an access-time value of 1 represents two

bus cycles, while 2 represents four bus cycles, 3 represents six bus cycles, etc.

(Id.) And, as the above discussion makes clear, the access time represents the

number of bus cycles a memory device will wait (i.e., skip) before it begins

accessing the bus to respond to that request. (A85[16:5-8]; see also A81[7:8-18]

(A request packet and the corresponding bus access are separated by a selected

number of bus cycles . . . .).)

3. The Bennett Referencea. Overview of Bennett

Bennett is a 396-page patent that nowhere discloses access-time registers or

the concept of a predetermined delay time between receipt of a write request and

the sampling of data. Instead, what this voluminous document discloses is a

versatile bus interface for a mainframe computer system, circa 1982. (A1146.)


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A key component of Bennetts system is a Versatile Bus, which is the

primary bus that carries information and control signals to and from the various

user devices that are attached to it, as illustrated in Figure 1:

(A1147[Fig. 1].)

As its name suggests, the Versatile Bus in Bennett presents an overarching

protocol that can be configured in many different ways, resulting in what Bennett

calls stupendous versatility. (A1440[79:32].) In practice, the Versatile Bus is

configured using a configuration register that includes eight parameters (I through

VIII), each having the possible values set forth in Figure 3:


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(A1149[Fig. 3].)

Bennett explains Figure 3 as follows:

FIG. 3 shows an entire spectrum of possible

parameterization of Versatile Buses. The left hand

column, Configuration Digit, is an index number used tospecify a selection of a particular configuration value in

one of the other columns I through VIII. For example, aconfiguration digit of 5 in the position of group lines

column I specifies that 8 lines are used in an arbitrationgroup. A string of eight configuration digits will

completely specify a Versatile Bus configuration. For

example the string 43133355 specifies a Versatile Bus

configuration with four group lines, 2 multiplexed groups

using a (fixed priority) multiplexed scheme for theconduct of time-phased arbitration[,] two SlaveIdentification/Function lines, 2 Slave Identification/Function cycles, 1 wait line and 16 data lines . . . .


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(A1439[78:26-40].) Thus, Bennett discloses a single Versatile Bus that can be

configured many different ways. (A1440[79:32].) Bennett does not, however,

disclose DRAMs and DRAM controllers, or enable the operation of a DRAM by a

DRAM controller using the Versatile Bus.

The area below the dashed line corresponding to configuration 55255355 in

Figure 3 defines a preferred bus configuration envelope that Bennett considered

preferable. As Bennett explains:

[I]t must be recognized that this 55255355 Versatile Businterface envelope of the preferred embodiment of the

invention will support a great multitude of subset

interfaces meeting the design rule. For example, the

Versatile Bus configurations of 42252255 shown inFIG. 32, 43112244 shown in FIG. 33, 52252355 shown

in FIG. 35, and 43153352 shown in FIG. 36, will all besupported by 55255355 preferred embodiment Versatile

Bus interface envelope as incorporated in the preferred

embodiment Versatile Bus Interface Logics chip design.

(A1439-40[78:68-79:10]; see also A1420[39:18-20] (There are 31,045 different

allowable configurations of the preferred embodiment of the invention.).)

Notably, Figure 3 is the only configuration matrix in Bennett

(see A1412[24:25]), and it serves as a roadmap to understanding the entire

universe of Versatile Bus configurations (see A1440[79:27-33]).

b. The Role of Wait Lines in BennettEight configuration parameters, each taking one of up to five preferred

configuration values, describe the overall operation of a given Versatile Bus


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configuration. Of these, the Board focused only on the sixth configuration

parameter (i.e., parameter VI), which specifies the number and configuration of

wait lines on the Versatile Bus. A wait line is a bus line that carries wait

information. Wait information tells an owner (e.g., a requester) whether a

slave (e.g., memory) attached to the bus is currently able to accept or sample

data in a particular transaction. (A1438[75:57-68].) As Bennett explains:

[T]here are a lot of meanings that can be ascribed to thewait line, all generally subsumed under the concept that a

slave device is unable, unwilling, or indisposed fromaccepting the data transfer activity within a transaction.

(A1438[76:20-24].) A slave drives a nonzero wait value onto a wait line to alert a

requester that data cannot presently be accepted by that slave for that particular

transaction and that the requester should therefore try again later. (See id.) Thus,

it is akin to a busy signal on a conventional telephone line, telling the caller to

try again later.

As shown below in red, in column VI of Figure 3, there are three options for

the number and configuration of wait lines in the preferred embodiment of Bennett

(below the dashed envelope line): one dedicated wait line (configuration digit =

3); zero wait lines (configuration digit = 2); or MPX, which stands for a

multiplexed wait line (configuration digit = 1). (See A1438[76:1-4].) Note that

two or four wait lines are also possible (configuration digits = 4 or 5), but these are

not within Bennetts preferred envelope. (A1438[76:57-67].)


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(A1149[Fig. 3] (boxes added).)

In the first case described above (wait-line configuration digit = 3), the

system contains one dedicated wait line, separate and distinct from any other data

line. This means the slave for a given transaction can transmit wait information

simultaneously with the master transmitting data, since they are carried on

different lines. (A1439[77:40-43].) Like two cars passing on a two-lane road, they

can travel at the same time. In the second case described above (configuration

digit = 2), there are zero wait lines and, therefore, wait information is not used at

all. (A1446[92:46-51].) In the third case described above (configuration digit =

1), wait information is multiplexed with data on a single line, such that both wait

information and data share the line. In this case, although there is no dedicated


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wait line, the slaves still transmit wait information by alternating it with the master

data on a shared line. (A1439[77:40-43].) Like two cars passing on a one-lane

road, one must wait until the other has gone first. They cannot pass at the same

time.

c. Timing of Bus Activity in BennettThe Boards decision refers to several timing schematics in Bennett,

including those illustrated in Figures 25a, 25b, 32, and 36. Each of these will be

discussed briefly below to provide context for the Boards decision.

i. Figure 36Figure 36 of Bennett shows pin utilization and activity timing for an

operation Write conducted with a large memory across a 43153355 configuration

Versatile Bus. (A1413[26:55-57] (emphasis added to highlight parameter VI).)

By reference to Figure 3, this configuration is within the envelope of Bennetts

preferred embodiment. (See A1440[79:4-10].) Notably, parameter VI in the

Figure 36 configuration is set to 3, indicating one dedicated wait line. Figure 36 is

reproduced below with annotations added to show the write instruction and the

commencement of data sampling in response to the write instruction. Note that

time transpires in the downward direction in this figure, with each horizontal row

representing one clock cycle.


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(A1170[Fig. 36].)

As shown above, and as the examiner found (A1078), in the memory write

transaction shown in Figure 36, two clock cycles elapse between receipt of the

write instruction and the commencement of data sampling (i.e., data sampling

begins on the third clock cycle after receipt of the write instruction). The two

intervening cycles contain the wait signal (WT in the figure above) and the

address bits for the location of the write request. Note that the number of address

bits is not established based on any value stored in a register on the large memory.

(A1448[96:33-42].)

The WT signal in Figure 36 provides the wait information for the recipient

memory slave. WT allows the memory slave in Figure 36 to refuse or accept the

write

instr.

data


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transaction based on the instantaneous conditions of the system, i.e., the slave need

not sample the data if it will not absorb it. (See A1438[76:26-30] ([A] Wait

signal simply tells the User who is master that the currently outgoing data is failing

to be absorbed by at least one slave User device and that the master User should

(normally) try again after an interval to send the same data.); A1408[16:56-58].)

ii. Figure 32Figure 32 of Bennett shows pin utilization and activity timing for an

operation Read or Write with a fast memory across a 42252255 configuration

Versatile Bus. (A1413[26:41-43] (emphasis added to highlight parameter VI).)

By reference to Figure 3, this configuration is within the envelope of Bennetts

preferred embodiment. (See A1440[79:4-10].) Notably, parameter VI in the

Figure 32 configuration is set to 2, indicating that there is no wait line. Figure 32

is reproduced below with annotations added to show the read/write request and the

commencement of data transfer in response to the read/write request.

(A1167[Fig. 32].)

read/

write

instr.

data


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As shown above, and as the examiner found (A1077), in the memory read or

write transaction shown in Figure 32, there are no clock cycles (i.e., no delay time)

between receipt of the read/write instruction (i.e., the OPERATION block in the

above schematic) and the commencement of data transfer. In other words, data

transfer begins on the next clock cycle after the read or write instruction is

received.

Note that if Figure 32 were configured to use the same wait configuration (3)

as Figure 36 (i.e., a non-fast-memory arrangement), such that it exchanged wait

information at the same time as the data, the data timing would remain unchanged.

In other words, in that configuration, data in Figure 32 would still be transmitted

on the next clock cycle after the read or write instruction because the wait

information would be transmitted simultaneously on the same clock cycle. Thus,

as the examiner noted (A1077-79), two bus configurations in Bennett with the

identical wait-line setting in Bennett will notnecessarily have the same sampling

delay (i.e., Figure 32 with a wait configuration of 3 would sample data on the next

clock cycle after the instruction, whereas Figure 36 using wait configuration 3

samples data on the third clock cycle after the instruction). Likewise, two

otherwise identical bus configurations in Bennett with different wait-line settings

can nevertheless have the same sampling delay (i.e., Figure 32 would have the

same zero-clock-cycle delay whether the wait-line setting were 2, 3, 4 or 5). These


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were important points supporting the examiners finding that the wait-line

configuration in Bennett is not representative of the number of clock cycles that

will necessarily transpire between a write instruction and the corresponding

sampling of data. (A1079 ([T]he Configuration Value of Wait Lines is not

representative of a number of clock cycles since the number of wait lines does

not correlate to a specific number of clock cycles. (emphasis in original).)

iii. Figures 25a and 25bFigures 25a and 25b of Bennett are part of a sequence of figures (25a-h)

used to show the relative order of operations in a generic bus transaction, not

disclosed as a memory transaction. (A1443[85:10-17].) Specifically, Figures 25a

and 25b show hypothetical transactions for two particular configurations of the

Versatile Bus differing only in that one has a multiplexed wait and data line

(Figure 25a), and the other has one dedicated wait line (Figure 25b). Notably, as

the Board conceded in a related proceeding, these figures depict only generic

informational transactions, not necessarily memory transactions. (A20181.)

Moreover, the illustrated transactions in these figures have been artificially

simplified to illustrate the sequence of operations. Specifically, as Bennett

explains, to simplify presentation of timing concepts [in these figures,] all . . .

activities are assumed to be but one cycle. (A1443[85:17-19] (emphasis added).)

This artificial assumption would not necessarily apply, however, to real-world


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memory transactions in Bennett, such as those illustrated in Figures 32 and 36

(as explained above).

Figures 25a and 25b are reproduced below, showing clock cycles T0, T1,

T2, etc., across the top:

(A1160[Figs. 25a, 25b].)

In Figure 25a, the Versatile Bus configuration is completely pin

multiplexed: Arbitration, Slave Identification/Function, Wait and Data all transpire

upon the selfsame data pins (lines). (A1443[86:4-9].) In other words, although

they are shown on separately illustrated lines in Figure 25a, they are in fact

implemented on a single bus line where the first clock cycle corresponds to

Arbitration, the second to ID/Function, the third to Wait, and the fourth to Data.

Because of this (i.e., because all four activities are transmitted sequentially on the

same bus line), this configuration must, and does, accord separate cycles to the

four activities of Arbitration, Slave Identification/Function, Wait and Data . . . .

(A1443[86:9-14].)


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As can be seen in Figure 25a, in this hypothetical, simplified transaction,

there are a total of four clock cycles between the beginning of the generic

transaction at T0 and the end of the transaction at T4. (A1443[86:37-41].) And

there is one clock cycle between the end of the generic ID/Function transmission at

T2 and the beginning of data transmission at T3 (which, again, would not

necessarily be the case in a real-world memory transaction in Bennett, e.g.,

because real memory transactions require a memory address).

In Figure 25b, the Wait line is not multiplexed. Instead, it is provided as a

dedicated line (i.e., parameter VI is set to 3 instead of 1). Because of this, the Wait

signal and Data can both be transmitted simultaneously during T2, since they are

being transmitted on separate lines. These are the two cars passing at the same

time on a two-lane road. This, in turn, allows reduction in total transaction cycle

times from 4 clock cycles to 3 clock cycles, as compared to Figure 25a.

(A1443[86:39-41].) This hypothetical reduction (which, again, may be completely

obscured in a real-world memory transaction once other factors are considered)

results from the fact that wait information and data are transmitted simultaneously,

rather than being multiplexed as in Figure 25a.

It should be noted that just because Data is transmitted in Figures 25a and

25b does not mean a slave is actually receiving that data. As explained above, a

wait instruction generally indicates unavailability of the slave device(s) to


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complete the requested transaction, necessitating that the master try again after an

interval to send the same data. (A1438[76:25-30].) Thus, just because data is

being transmitted on the Versatile Bus in Figures 25a and 25b, this does not mean

the data is actually being sampled by the slave to which it is addressed. Instead, it

is up to the slave whether or not to sample the data based on the instantaneous

conditions of the system.

Moreover, because Figures 25a and 25b show only simplified generic

informational transactions (A20181), it is impossible to know how they would

relateif at allto an actual memory write transaction such as that shown in

Figure 36. In other words, because Figures 25a and 25b are so simplified and

generic, they provide no information about the actual time that would transpire

between a write request and sampled data in an actual memory write transaction.

For example, Figures 25a and 25b do not show any address information being sent

across the bus, whereas an actual memory transaction would necessarily include

such address information. (See A1168[Fig. 34].) In Figure 36, this address

information is provided over two clock cycles. But in Figures 25a and 25b,

because no address information is shown at all, it is impossible to know how much

time would actually transpire between a write request and data sampling, even

assuming memory accesses were possible with these hypothetical transactions.


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4. The Examiners Finding that Bennett Does NotAnticipate Claims 15 and 16

After a thorough review of the record, the examiner concluded that Bennett

does not disclose storing a value which is representative of the programmable

number of clock cycles of the external clock in a programmable register. (A1072-

81.) The examiner found that, although a change in the wait-line value in Bennett

(i.e., parameter VI) can affectthe number of cycles that transpire in a transaction,

this does not mean the wait-line value represents the number of clock cycles that

will transpire before data is sampled in response to a write request:

[T]he Examiner notes that Figures 25a and 25b shows

[sic] that a change in the configuration value changes thenumber of clock cycles that transpire, however, the above

citations shown in Bennett also makes it clear that theWait Line does not represent a number of clock cyclesbut instead indicates whether data is accepted or whether

th[ere] is a need to re-try at a later time. The Examiner

notes that that [sic] based on the programmedconfiguration, the accepting or retrying causes data to besampled at different clock cycles, however while the

configuration digit changes the number of clock cyclesthat must transpire, the configuration digit itself is not

indicative of the number of []clock cycles that will

have transpired before data is sampled.

* * * *[F]igures 32, 35 and 36, bring to light that the

Configuration Value of Wait Lines is notrepresentative of a number of clock cycles since the

number of wait lines does not correlate to a specificnumber of clock cycles.

(A1078-79 (emphases in original).)


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Based on this finding, the examiner correctly concluded that claims 15 and

16 are not anticipated by Bennett. (A1081.) Notably, in the quote above, the

examiner refers to Bennetts Figure 35, which shows a split-transaction large

memory read. (A1413[26:50-54].) Samsung had originally contended that the

Bennett wait-line configuration specified a data delay for both write and read

transactions. (A1585-86.) It is particularly clear from Figure 35 that request-to-

read data delay is unknowable in Bennetts split-transaction protocol, no matter

what the wait-line configuration is, because the memory must separately arbitrate

onto the bus, which requires an indeterminate amount of time (as indicated by the

vertical ellipses in Figure 35 (A1169)). Thus, Figure 35 supported the examiners

determination that the wait-line value in Bennett does not represent a stored,

programmable delay. (A1078-79.) Further discussion of Figure 35 has been

omitted in this brief, however, because the claims-at-issue focus on write

transactions, whereas Figure 35 discloses a read transaction.

5. The Boards Decision Reversing the ExaminersFinding that Bennett Does Not Anticipate Claims 15

and 16

On appeal, the Board reversed the examiners finding of no anticipation and,

specifically, the finding that Bennett does not disclose a value which is

representative of a programmable number of clock cycles. This was based in part


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on the Boards implicit misconstruction of the term representative and also on its

fundamental misunderstanding of Bennett.

The Board made no attempt to rebut that the same wait-line parameter in

Bennett results in different numbers of clock cycles transpiring in the transactions

shown in Figures 25b, 35, and 36. Instead, the Board dismissed this fact as

follows:

Rambuss response, comparing how the sameprogrammable digit 3 causes different delays in different

embodiments, simply does not defeat the anticipation byany single configured embodiment of Figures 25a-h,

which show the two choices for programmable digits for

those configurations, either 1 or 3.

(A40.)

Despite referring to several configurations (Figures 25a-h) as an alleged

single configured embodiment, the Board failed to demonstrate an embodiment

where the wait-line configuration represents the number of clock cycles between a

write request and sampled data. The Boards analysis focused instead on

comparing two hypothetical, generic transactions in two different bus

configurations in Bennett and noting how the change in wait-line value affects data

timing within these hypothetical transactions. (Id.) The Board focused primarily

on the hypothetical, generic transactions illustrated in Figures 25a-h. (See A39-41.)

The Boards analysis, however, failed to address the reality of Bennetts overall

system, where the timing of memory transactions depends on much more than the


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wait-line configuration, including arbitration, the pin settings and address block

size, the memorys own behavior, and the instantaneous behavior of other actors

on the bus. None of these factors serves the purpose of an intentional, stored

programmable number of clock cycles, as required in the claims-at-issue.

IV. SUMMARY OF ARGUMENTThe Board lacked jurisdiction to hear Microns appeal of the validity of

claims 15 and 16, and therefore should have dismissed the appeal. First, because

Micron did not raise the Bennett anticipation argument in its request for inter

partes reexamination and had no right to appeal that issue prior to the PTOs

merger, it could not have gainedthe right to do so merely by virtue of the PTOs

merger. In other words, the PTO does not have the authority to confer statutory

rights on a party through the administrative act of merging two reexamination

proceedings. Second, allowing Micron to step into Samsungs shoes in this

reexamination proceeding violated the prohibition of 35 U.S.C. 317(a) that a

third-party requester, having successfully initiated an inter partes reexamination of

a patent, cannot initiate a second inter partes reexamination of that same patent

while the first is still ongoing. Because standing is a jurisdictional prerequisite and

because the Board would not have had jurisdiction to decide the validity of claims

that were not appealed to it, the Board should never have reached the validity of

claims 15 and 16.


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Even if the Board had jurisdiction over Microns appeal (which it did not), it

erred by reversing the examiners finding that Bennett does not disclose a value

which is representative of the programmable number of clock cycles. The

Boards analysis was premised on an implicitly incorrect construction of

representative, which allowed the Board to conclude that, just because Bennetts

wait-line configuration can affect the number of clock cycles that will transpire,

this necessarily means the configuration is representative of the number of clock

cycles that will transpire. Under a proper construction of representative, no such

conclusion can properly be drawn. Moreover, the Boards factual findings lack

substantial evidence and are clearly rebutted by the examiners contrary findings

regarding Figures 25b, 32, and 36 of Bennett.

V. ARGUMENTA. The Board Erred in Determining that It Had Jurisdiction

over Microns Appeal

1. 35 U.S.C. 315 Does Not Give a Requester the Rightto Appeal Issues Raised by Another Requester in

Another Reexamination, Even If the Reexaminations

Are Merged

Under 37 C.F.R. 1.989, the PTO may, in its sole discretion, choose to

merge two or more pending inter partesreexaminations relating to the same patent

into a consolidated proceeding. The sole statutory authority for this rule is

35 U.S.C. 2(b)(2), which generally gives the PTO the authority to establish

regulations, not inconsistent with law, that govern the conduct of proceedings in


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the PTO. Nothing in 35 U.S.C. 2(b)(2), however, permits the PTO to promulgate

a regulation that confers statutory rights upon a party that it would not otherwise

have absent the regulation. Consistent with this fact, the PTO has referred to

merger merely as a procedural housekeeping issue. (A20204.)

The statutory right of a third-party requester of an inter partesreexamination

to appeal to the Board is established by 35 U.S.C. 315, which states in relevant

part:

(b) Third-Party Requester. A third-party requester [ofan inter partesreexamination]

(1) may appeal under the provisions of section 134 [to

the Board], and may appeal under the provisions ofsections 141 through 144 [to the CAFC], with respect to

any final decision favorable to the patentability of anyoriginal or proposed amended or new claim of the patent;

and

(2) may, subject to subsection (c), be a party to any

appeal taken by the patent owner under the provisions ofsection 134 [to the Board] or sections 141 through 144

[to the CAFC].

35 U.S.C. 315(b) (2002).3

Notably, section 315 of the patent statute does not contemplate, suggest, or

otherwise encompass the concept of merged reexamination proceedings, since

3Because the inter partes reexaminations-at-issue in this motion were instituted

before the America Invents Act (AIA), the statutes and rules in existence beforethe AIA was implemented should govern this issue.


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merger of reexamination proceedings is a creature of PTO regulation, not statute.

Thus, when section 315 refers to any final decision in subsection (b)(1) and any

appeal taken by the patent owner in subsection (b)(2), it is referring to any final

decision or appeal in the particular reexamination that the third party actually

requested. It does not, for instance, give Party A the right to appeal a final decision

in Party Bs separate and wholly distinct reexamination proceeding, merely

because both proceedings involve the same patent. Nor does it give Party A the

right to participate in an appeal to the Federal Circuit taken by the patent owner

from a differentreexamination requested by Party B, involving a differentpatent.

This is abundantly clear not only from the language of section 315 itself but

also from the context of the entire statute. See Kokoszka v. Belford,417 U.S. 642,

650 (1974) (holding that, when interpreting a statutory provision, the whole

statute must be considered). Throughout the statutory sections that implemented

the inter partesreexamination procedure in 2000, as amended in 2002, there is an

obvious and inescapable assumption that references to any (e.g., any appeal,

any document, any communication) pertain only to a particularreexamination

requested by aparticularthird party, not to all reexaminations generally involving

the same patent or patent owner.

For instance, section 314(b) states in part: With the exception of the inter

partes reexamination request, any document filed by either the patent owner or the


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third-party requester shall be served on the other party. 35 U.S.C. 314(b)(1)

(2000) (emphasis added). Does this mean that, if Requesters A and B are both

involved in unrelated reexaminations against the same patent owner, the patent

owner must serve both requesters with all filed documents, even if the

reexaminations involve unrelated patents? The answer is obviously no, and neither

the PTO nor Micron has ever suggested otherwise. And yet that would be the

absurd result of applying the PTOs sweeping interpretation of any in section

315(b) to the other provisions of this statute. Cf. Sullivan v. Stroop, 496 U.S. 478,

484 (1990) ([I]dentical words used in different parts of the same act are intended

to have the same meaning. (citation omitted)).

Moreover, because section 315(b) is a statute that grants appeal rights to

third-party requesters in specific circumstances, it should be narrowly construed.

See Office of Senator Mark Dayton v. Hanson, 550 U.S. 511, 515 (2007)

([S]tatutes authorizing appeals are to be strictly construed. (citing Perry Ed.

Assn v. Perry Local Educators Assn.,460 U.S. 37, 43 (1983); Fornaris v. Ridge

Tool Co., 400 U.S. 41, 42 n.1 (1970) (per curiam))). In Hanson, the Supreme

Court interpreted a statute that provided that [a]n appeal may be taken directly to

the Supreme Court of the United States from any interlocutory or final judgment,

decree, or order of a court upon the constitutionality of any provision of this

chapter. Hanson, 550 U.S. at 514 (quoting 2 U.S.C. 1412(a)). The Court


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declined to interpret this provision broadly enough to include an as applied

constitutional holding of an appellate court, relying in part on the doctrine that

statutes authorizing appeals are to be strictly construed. Id.

2. The PTOs Merger Procedure Cannot ConferStatutory Rights upon a Party that It Would Not

Otherwise Have Had Absent the Merger

Rambuss argument is best illustrated by considering Microns right to

appeal to the Board under 35 U.S.C. 315 in two distinct circumstances: (1) absent

merger and (2) with merger.

Absent merger of the two reexamination proceedings under 37 C.F.R.

1.989, the Micron-requested proceeding would have continued on its own path,

separate and distinct from the Samsung-requested proceeding. In the Micron-

requested proceeding, the examiner would have ultimately rejectedall of Microns

invalidity arguments, i.e., the proposed anticipation rejection based on the iAPX

Manual and the proposed obviousness rejections based on Gustavson in view of

either Bennett or Bowater. (A1105-06.) At that point, the only issues Micron

could have appealed to the Board and to this Court would have been the

examiners nonadoption of those proposed rejections. See 35 U.S.C. 315(b)(1)

(2002).

In the nonmerger scenario, the Samsung-requested proceeding would have

likewise continued on its own separate path. The examiner in that proceeding


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would have ultimately found claim 13 anticipated by Bennett and claims 15 and 16

allowable over Bennett. (A1102-04.) At that point, Rambus would have appealed

the claim 13 rejection to the Board (as it did), and Samsung would have had the

right (but for its earlier withdrawal) to appeal the examiners affirmance of claims

15 and 16. But since Samsung had already withdrawn from the reexamination

proceeding, it would not have appealed. Therefore, the only issue that would have

been appealed to the Board in the Samsung-requested proceeding would have been

the rejection of claim 13, appealed only by Rambus.

In the nonmerger scenario, Micron would nothave had any statutory right to

appeal anything in the Samsung-requested reexamination proceeding since Micron

was never a party to that proceeding. Thus, Micron could not have appealed the

examiners affirmance of claims 15 and 16 over Bennett. As explained above, 35

U.S.C. 315 only gives third-party requesters the right to appeal adverse decisions

in the reexaminations that they actually requested. There is no legitimate reading

of the statute that would have conferred on Micron the right to suddenly jump into

Samsungs reexamination proceeding and appeal issues to the Board that Micron

had never raised in its own proceeding. Nor is there any legitimate reading of the

statute that would have given Micron the right to step into Samsungs shoes after

Samsung withdrew from its reexamination proceeding, such that Micron could


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have somehow become the appellee in Samsungs reexamination proceeding,

taking up Samsungs would-be positions before the Board and this Court.

Compare the nonmerger scenario to what actually occurred below, i.e.,

where the PTO sua sponte merged the Samsung-requested proceeding and the

Micron-requested proceeding pursuant to 37 C.F.R. 1.989. In this merger

scenario, according to the Boards logic, Micron was suddenly endowed with new

statutory rights. According to the Board, by mere virtue of the merger procedure

a regulatory creature solely of the PTOs makingMicron now had the right to

appeal issues it never raisedin its reexamination request. According to the Board,

as soon as the two proceedings were merged, the scope of 35 U.S.C. 315

expanded such that Micron could not only appeal any final decision on issues it

had raised but also on issues that Samsung had raised. According to the Boards

logic, this significant expansion of Microns statutory rights occurred solely

because of the happenstance of the PTOs decision to merge the two proceedings.

As explained above, had there been no such merger, Micron would not have

enjoyed this alleged expansion of its statutory rights.

The problem with the Boards logic is that the PTO does not have the

authority to expand a partys statutory appeal rights in this manner. See

Koninklijke Philips Elecs. N.V. v. Cardiac Sci. Operating Co., 590 F.3d 1326, 1336

(Fed. Cir. 2010) (The PTO lacks substantive rulemaking authority.); see also


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Merck & Co. v. Kessler, 80 F.3d 1543, 1549-50 (Fed. Cir. 1996) ([T]he broadest

of the PTOs rulemaking powers35 U.S.C. 6(a) [now contained in 35 U.S.C.

2(b)]authorizes the Commissioner to promulgate regulations directed only to

the conduct of proceedings in the [PTO]; it does NOT grant the Commissioner

the authority to issue substantive rules. (third alteration in original) (citation

omitted)). Thus, the PTO cannot interpret its own merger rule in a manner that

would confer newsubstantive rights on Micron (e.g., the right to appeal Samsungs

proposed rejections) that Micron would not have enjoyed absent the merger.

Indeed, in litigation, consolidation of two cases does not give any party

greater or lesser rights that it would have had absent the consolidation. See

Johnson v. Manhattan Ry. Co., 289 U.S. 479, 496-97 (1933) ([C]onsolidation is

permitted as a matter of convenience and economy in administration, but does not

merge the suits into a single cause, or change the rights of the parties, or make

those who are parties in one suit parties in another.); New York v. Microsoft

Corp., No. Civ. A. 98-1233, 2002 WL 318565, at *4 (D.D.C. Jan. 28, 2002)

([R]ather than merging the rights of the parties, consolidation is a purely

ministerial act which, inter alia, relieves the parties and the Court of the burden of

duplicative pleadings. Hence, the mere fact of consolidation does not allow one

party to take advantage of a rule applicable to the other party. (footnote omitted));

S. Cal. Fed. Sav. & Loan Assn v. United States, 51 Fed. Cl. 676, 678 (Fed. Cl.


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2002) ([Consolidation] does not expand this Courts jurisdiction, which is

narrowly defined and statutorily prescribed by Congress. Our jurisdiction cannot

be enlarged by rule.).

By the same token, Micron should not be permitted to appeal issues raised

only by Samsung merely because of the ministerial act of merger, which is a

creature of regulation, not statute. If the Boards decision were allowed to stand,

the PTO will have effectively enlarged Microns statutory rights to appeal by

administrative fiat, contrary to the spirit and the letter of the patent statute.

Moreover, it is worth noting that the Board correctly ruled on this issue the

first time it was raised, although it later reversed itself on reconsideration.

Specifically, in merged proceeding 95/001,026 and 95/001,128, the Board

originally ruled that, in a notice of appeal (or cross appeal), a requester is limited

to presenting rejections previously proposed by that third party requester.

(A20028 (emphasis in original).) That ruling was based on the Boards

interpretation of MPEP 2674(B), which states that [a] notice of appeal by a third

party requester must identify each rejection that was previously proposed by that

third party requesterwhich the third party requester intends to contest. MPEP

2674(B) (8th ed. Rev. 7 July 2008). Rambus submits that the Board was correct

in this ruling, not only based on MPEP 2674(B), but also on 35 U.S.C. 315

and 2(b)(2), as explained above.


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Indeed, more recently, the PTO has further muddied its position in

reexaminations of other parties patents, stating that, although two inter partes

reexaminations were merged, [n]o inter partes requester has a right to comment

on any issue raised outside the confines of the statute, e.g. issues raised in . . . the

request and comments from another requester. (A20163.) The PTO has further

opined that, for appeals to the Board, each inter partes reexamination requesters

appeal must only be taken from the finding(s) of patentability of claims in the

[Right of Appeal Notice] that the individual third party requester proposed in the

request, and any that the individual third party requester properly added during the

examination stage of the merged proceeding. (A20163-64; compare A1694-95

(in present merger, including no discussion of comment rights or appeal rights).)

The PTOs lack of clarity on this issue demonstrates that this Courts guidance is

badly needed.

3. Because 35 U.S.C. 315 Clearly Sets Forth the Limitsof the Boards Jurisdiction, the PTO Is Not Entitled

to Chevron Deference in Interpreting This Statute

The Supreme Court recently addressed Chevron deference and held that

such deference applies to an agencys determination of its own jurisdiction, but

only when the agency has been granted the authority to make that determination in

the first place. City of Arlington, Texas v. FCC, No. 11-1545, slip op. at 16 (S. Ct.

May 20, 2013) (addressing application of Chevron U.S.A. Inc. v. Natural


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Resources Defense Council, Inc.,467 U.S. 837 (1984)). Thus, Chevron deference

does not apply to actions taken by an agency that are outside its statutory authority.

Id. at 15 ([F]or Chevron deference to apply, the agency must have received

congressional authority to determine the particular matter at issue in the particular

manner adopted.).

Congress gave the PTO authority only to establish regulations, not

inconsistent with law, which . . . shall govern the conduct of proceedings in the

Office. 35 U.S.C. 2(b)(2)(A) (emphasis added). Thus, the PTO has rulemaking

authority that is limited to procedural rules that are consistent with the law. Here,

Congress has spoken directly to the jurisdiction issue and made clear that a party

may appeal to the Board only issues that it raised in its own reexamination request.

Id. 315. Thus, Chevron deference is unwarranted, as Congresss intent was clear

and the Board does not have statutory authority to change th

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