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CAD LAB (ELECTRONIC CIRCUIT DESIGNING)
TOOLS USED
PSPICE- 5.4, 6.0
ORCAD-PSPICE- 9.1, 9.2, 10.
B.TECH-IV TH year ECE
8TH SEMESTER
SUBMITTD BY: INSTRUCTOR:
Shivani Tomar Mr. Sumit Joshi
Roll No.-: 08490102048
CONTENTS1.INTRODUCTION
1.1SCHEMATIC DESIGNING
1.2LAYOUT DESIGNING
1.3CIRCUIT SIMULATION
2.LIST OF CAD LAB PRACTICALS
2.1AND gate simulation(9.2)
2.2OR gate simulation(9.2)
2.3OP-AMP differential amplifier simulation(9.2)
2.4 OP-AMP integrator simulation(9.2)
2.5HALF-WAVE rectifier simulation(9.2)
2.6BRIDGE rectifier with capacitive filtering simulation(9.2)
2.7BRIDGE rectifier with L-C filtering simulation(9.2)
2.8PUSH-PULL amplifier simulation(9.2)
2.9PUSH-PULL amplifier with OP-AMP simulation(9.2)
1.INTRODUCTION
The practical methodology behind testing of any circuit is to physically implement the circuit. The most important change in circuit designing took place in around 70’s with the advent of miniaturized components coming into being like: transistors,diodes & other semiconductor products due to which size of components still became smaller & lead to development of IC’s later. Moreover it was not possible to design & test these on board & it was found that it would be better to test these in advance before implementation phase for compatible results . This on board implementation was not only costly but also time-consuming.
These all factors lead the scientits & engineers to believe that there is utmost requirement of a computer based design & analysis tool for the same purpose of circuit simulation. Thus arrived SPICE acronym for “Simulation Program for Integrated Circuit Emphasis.”
SPICE was developed as a part of efforts of University of California,Berkley during mid 1970’s as SPICE2 which later became widely popular and was developed as a part of initial SPICE program & CANCER simulator platform. It gained commercial importance very fastly because of simplistic & robust algorithms been deployed in it.
The most interesting part is that ,PSPICE offers two options to the users to either directly simulate the circuit by generating schematic over the PSPICE GUI or by writing SPICE code for generation of all the simulation & schematic files altogether.
In our present lab work we have followed direct approach of simulation via., PSPICE based on ORCAD 9.2 LITE EDITION & 9.1 STUDENT VERSION.
Some of popular pspice versions available earlier & today are as:
1. HSPICE from Meta Software.2. I.G SPICE from A.B Associates.3. RAD-SPICE FROM Meta Software.4. IS-SPICE from INTUSOFT.5. Z-SPICE from Z-TECH.6. SPICE PLUS from Analog Design Tools.7. DSPICE from DAISY SYSTEMS.8. PSPICE from MICROSIM.(AT PRESENT)9. LT SPICE IV (LATEST).
1.1 SCHEMATIC DESIGNING The fundamental circuit designing with all on board components depicting top layer of the board (PCB) is termed as schema or schematic. It gives information in relation to the number of components being used & why,what of circuit w.r.t application part.
A general schematic developed board in ORCAD-10.5 platform is shown as example below as:
Example schematic (top layer of board)
1.2 LAYOUT DESIGNING The bottom layer of the board dealing with individual components being connected depicting connections enabling communication between various passive & active entities placed over the board is termed as layout. An example Layout has been depicted as below:
Example layout(bottom layer)
1.3 CIRCUIT SIMULATION Circuit implementation can be done with utmost certainity only if the circuit has been tested before hand and this was made possible with the help of PSPICE. It facilitates software based simulation & testing of the circuit after netlisting of components performed. Thereafter, the circuit schematic with connections is tested for errors , if there are no errors during netlisting a clean output file is generated & probe window is opened which let’s user define kind of simulation settings prefferred w.r.t the application like whether a transient or d.c etc. kind of analysis to be performed. This is followed by defining step size & other input parameters for waveform generation at input end & on run simulation button being pressed output is depicted as defined.
C F 0 .1 u F
R F 2 0 0 k V
R o
7 5
0V
R L
1 0 k
0VV s
1 0 m V+-
0
+-
+-
E 1
2 E + 5 V /V
C i
1 .5 p F
0V
R 1
1 k
0V
R i
2 M e g
V
0V
Example circuit being simulated
Example response on log-scale for simulated circuit
LIST OF CAD LAB PRACTICALS
AND gate simulation(9.2) OR gate simulation(9.2) OP-AMP differential amplifier simulation(9.2) OP-AMP integrator simulation(9.2) HALF-WAVE rectifier simulation(9.2) BRIDGE rectifier with capacitive filtering simulation(9.2) BRIDGE rectifier with L-C filtering simulation(9.2) PUSH-PULL amplifier simulation(9.2) PUSH-PULL amplifier with OP-AMP simulation(9.2)
2.1 AND gate simulation
U 1 A
7 4 0 0
1
23
V0
CLKD S TM 1O F F TI M E = . 0 5 u S
O N TI M E = . 0 5 u SD E L A Y = S TA R TV A L = 1O P P V A L = 0
V
V
CL
K
D S TM 2O F F TI M E = . 0 5 u SO N TI M E = . 0 5 u SD E L A Y = S TA R TV A L = 0O P P V A L = 1
Output:
2.2 OR gate simulation
U 2 A
7 4 0 2
2
31
V0
CLKD S TM 1O F F TI M E = . 0 5 u S
O N TI M E = . 0 5 u SD E L A Y = S TA R TV A L = 1O P P V A L = 0
V
V
CL
KD S TM 2
O F F TI M E = . 0 5 u SO N TI M E = . 0 5 u SD E L A Y = S TA R TV A L = 0O P P V A L = 1
Output:
2.3 OP-AMP differential amplifier simulation
V C C1 5 V
+
-
V E E1 5 V
+
-
V
0
U 1u A 7 4 1
3
2
74
6
1
5+
-
V+
V-
OUT
OS1
OS2
0
15.00V
V
1.000V
R F 9 0 k
R s 5 k
-15.00V
R 1
1 0 k
R L
1 0 k
V s1 V+-
10.00V
Output:
2.4 OP-AMP integrator simulation
-12.00V
-62.00uV
12.00V
0
-58.00uV
V
R 1
1 k
0
R x 1 k
VV E E1 2 V+
-
0V
R F 2 0 0 k
V
-79.73uVV s+-
0V
V C C1 2 V+
-
C F 0 .1 u F
0 V
-2.000V
U 1
u A 7 4 1
3
2
74
6
1
5+
-
V+
V-
OUT
OS1
OS2
Output:
2.5 HALF-WAVE rectifier simulation
vsV B 1 2 V
+
-
2 :1 0V
V p+-
0V
0V
0
I
0
R s
1 m12.00V
R
4 .2 6
T X 1D 1
V p
2.6 BRIDGE rectifier with capacitive filtering simulation
3
2
D 40
D 3 V+
D 2
V-
323.8e-21VD 1
0V
323.7e-21V
V s6 0 H z2 0 V
+-
0V
R L
5 0 0
C
1 3 5 .4 8 u F
2.7 BRIDGE rectifier with L-C filtering simulation
D 1
2
D 2
4
3.252e-18V3
D 31
0
3.252e-18V
L
0 .5 H
D 4
0V
V s+- 0V
3.252e-18V V+
V-
C
2 6 .5 3 u F R L
5 0 0
2.8 PUSH-PULL amplifier simulation
C 11 0 u F704.1mV
R
1 .4 3 kR s 0 .0 1
14.21V
Q 1
Q 2 N 2 2 2 2
+ vo
0
15.00V
Q 2
Q 2 N 2 9 0 7 A
Q 3
Q 2 N 2 9 0 7 A
R B2 7 4 k
10.12V
V C C1 5 V
+
-
0 0
R L 2 5 0 k
V
0V
0V
V s
2 kh z1 m v+-
0V
C 2 1 0 u F
0V
2.9 PUSH-PULL amplifier with OP-AMP simulation
17.04uV
V
Q 2Q 2 N 2 9 0 7 A
0V
-12.00V
R 1
3 0 0R L
5 0
V C C
1 2 V
+
-
V E E1 2 V
+
-
0V
U 1
u A 7 4 1
3
2
74
6
1
5+
-
V+V-
OUT
OS1
OS2
440.5mV
12.00V
V i
D C = 5 V1 0 V1 kH z
+-
Q 1Q 2 N 2 2 2 2
