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CAD for VLSI 1 Pro ject - USAR T 1 Problem Serial data transmission is widely used in communications over long distances. Parallel communication requires many wires to be laid bet ween the t wo communicating points. Hence, usually data is converted to serial format and sent over fewer number of wires to the destination. Intel 8251 is a Universal Synchronous and Asynchronous Receiver T ransmitter (USAR T) which is a widely used peripheral communication device. USAR T receives serial data from the CPU and transmits serial data after conversion. The device can also receive serial data from the outside and transmit parallel data to the CPU. Thus, it is an ideal device to be used for long distance communication. 2 Description Refer to the book “Microprocessors and Interfacing : Programming and Hardware” by Dou- glas V. Hall, Glencoe McGraw Hill, ISBN-0070257426. The book has detailed description about 8251. The material is self-contained and has detailed description about using 8251 in both Asynchronous and Synchronous mode. The functional block diagram of 8251 is given in Figure 1. 2.1 Configuring an 8251 1. Send the device a Mo de Wor d. The mode word configures the data transfer as syn- chronous or asynchronous, the baud rate factor for asynchronous transfer, character length and stop bit specification and parit y control. 2. Load the Command Wor d. The command word selectively enables/disables v ari- ous operations and read/write flags for communication. Typically the device is set to transmit/receive and a sequence of command words are used for waiting to trans- mit/receive, to actually perform data transfer, to check for SYNC characters, to detect errors etc. A detailed understanding of these modes is necessary . Refer to the 8251 documentation. Y our design must stick to the mode/command specifications of the device. 2.2 Asynchronous Mode - Pages 442-448 F or asynchronous transmission, a start bit is used to identify the beginning of each character and at least one stop bit is used to identify end of data character. Effectively , the sender and receiver are synchronized on a character by character basis. In asynchronous mode, 8251 is first configured for a specific baud rate using the mode word. Y ou must also configure the parit y , number of stop bits and the character length. Once that is done, we can read 1

CAD for VLSI 1 Project USART - NPTELnptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/project2.pdf · CAD for VLSI 1 Project - USART 1 Problem Serial data transmission is widely

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Page 1: CAD for VLSI 1 Project USART - NPTELnptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/project2.pdf · CAD for VLSI 1 Project - USART 1 Problem Serial data transmission is widely

CAD for VLSI 1 Pro ject - USART

1 Problem

Serial data transmission is widely used in communications over long distances. Parallel communication requires many wires to be laid between the two communicating points. Hence, usually data is converted to serial format and sent over fewer number of wires to the destination. Intel 8251 is a Universal Synchronous and Asynchronous Receiver Transmitter (USART) which is a widely used peripheral communication device. USART receives serial data from the CPU and transmits serial data after conversion. The device can also receive serial data from the outside and transmit parallel data to the CPU. Thus, it is an ideal device to be used for long distance communication.

2 Description

Refer to the book “Microprocessors and Interfacing : Programming and Hardware” by Dou- glas V. Hall, Glencoe McGraw Hill, ISBN-0070257426. The book has detailed description about 8251. The material is self-contained and has detailed description about using 8251 in both Asynchronous and Synchronous mode. The functional block diagram of 8251 is given in Figure 1.

2.1 Configuring an 8251

1. Send the device a Mode Word. The mode word configures the data transfer as syn- chronous or asynchronous, the baud rate factor for asynchronous transfer, character length and stop bit specification and parity control.

2. Load the Command Word. The command word selectively enables/disables vari-

ous operations and read/write flags for communication. Typically the device is set to transmit/receive and a sequence of command words are used for waiting to trans- mit/receive, to actually perform data transfer, to check for SYNC characters, to detect errors etc.

A detailed understanding of these modes is necessary. Refer to the 8251 documentation. Your design must stick to the mode/command specifications of the device.

2.2 Asynchronous Mode - Pages 442-448

For asynchronous transmission, a start bit is used to identify the beginning of each character and at least one stop bit is used to identify end of data character. Effectively, the sender and receiver are synchronized on a character by character basis. In asynchronous mode, 8251 is first configured for a specific baud rate using the mode word. You must also configure the parity, number of stop bits and the character length. Once that is done, we can read

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Page 2: CAD for VLSI 1 Project USART - NPTELnptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/project2.pdf · CAD for VLSI 1 Project - USART 1 Problem Serial data transmission is widely

RESET CLK C/D RD WR

CS

DSR

DTR

CTS

RTS

D7−D0

DATA BUS BUFFER

READ/ WRITE CONTROL MODEM CONTROL

I TRANSMIT

N BUFFER T E R N A L

TRANSMIT CONTROL

B U S

RECEIVE BUFFER

RECEIVE CONTROL

TxD

TxRDY

TxEMPTY

TxC RxD

RxRDY RxC SYNDET/ BRKDET

Figure 1: Block Diagram of 8251 from/write to 8251 on an interrupt or a polling basis. For this project, you will use Interrupt basis for communicating between 8251 and the host processor.

2.3 Synchronous Mode - Pages 477-480

Asynchronous mode spends a significant time in sending stop and start bits. To overcome this, 8251 can be operated in a synchronous fashion. In this mode, the sender and receiver are synchronized and characters are transmitted in large blocks. Thus, no start or stop bits are necessary. However, there must be some way of signalling start and end of data transfer. For this purpose, SYNC characters are used. When there is no data transfer, the lines are held in mark condition. When data transfer is necessary, the transmitter sends SYNC characters. The receiver uses these characters to synchronize its internal clock based on the SYNC character.

In addition to data transfer schemes, a higher level protocol is necessary for orderly transfer of data. BISYNC, Binary Synchronous Communication Protocol, is a Byte Con- trolled Protocol in which specific ASCII characters are used for handshaking. Refer to the document on using 8251 for BISYNC communication.

3 Constraints

1. Design the 8251 device which should handle both asynchronous and synchronous

communication mechanisms.

2. For asynchronous mode, you must design the host computer system that uses Interrupt Mechanism for data transfer to/from the 8251 device.

3. For synchronous mode, you must use BISYNC protocol to communicate between two

hosts.

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Page 3: CAD for VLSI 1 Project USART - NPTELnptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/project2.pdf · CAD for VLSI 1 Project - USART 1 Problem Serial data transmission is widely

4 Pro ject Report You must turn in a neatly typed report that describes the project in brief. You must describe your design clearly. Explain the features that you have implemented. Design- ing the host computer is also a significant task and different groups may have different schemes. You must describe the host computer that you have designed clearly. Also, you must demonstrate how the host computer design is sufficient for data transfer. Make your own assumptions like how the data is stored in the host computer, how interrupt is handled etc. Your project will be graded as follows:

1. Introduction 5 Points

• Abstract;

• Table of Contents;

• Basic summary of your design and results.

2. Asynchronous Mode 30 Points

• Design of 8251;

• Design of the host computer and interrupt handling; • Demonstration of asynchronous communication. You must have two hosts each of

which are configured for asynchronous communication. Transfer binary numbers 1-200 from one host to another at 1X baud rate and with two stop bits. Write the necessary programs for configuring 8251 to do so.

• Well Annotated Verilog Code; • Detailed Simulation showing the data transfer mechanism and the handshaking

that goes on inside the two hosts. Waveforms should be clearly annotated. • The testbench is a crucial part of this project. Explain the test strategy that

you will use and clearly annotate your Verilog code.

3. Synchronous Mode 30 Points

• Design of host computer and 8251 device. • Demonstration of Synchronous Communication. You must have two hosts that

communicate using BISYNC protocol. Transfer binary numbers 1-200. Use the SYNC characters that are specified in the reference material.

• Well annotated Verilog Code for the same;

• Detailed Simulation showing the data transfer and handshaking. • As earlier, the testbench is a crucial part. Explain your test strategy and clearly

annotate your Verilog model and waveforms.

4. Synthesis 20 Points

• Synthesize your 8251 device using Quartus and Magma.

• More detailed specifications for synthesis will follow.

5. Report Format and Style 5 Points

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Page 4: CAD for VLSI 1 Project USART - NPTELnptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/project2.pdf · CAD for VLSI 1 Project - USART 1 Problem Serial data transmission is widely

6. Discussion 5 Points Talk to another group whose project was different from yours. Find out details about their project and explain briefly how they designed their project. Also, give details of their test strategy. Write a one-page report about the other group’s work. Clearly describe how you divided your tasks among your group members. Each of you must write a brief evaluation of the other members work. Be honest. Hand them back to us individually. Do not attach it with your project report. The review that you give about your partners will be held confidential.

7. Progress Report 5 Points Turn in a 2-page progress report that describes your preliminary studies and your strategy for designing and testing the USART. The progress report is due on April 13 2007 during class.

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