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A ADISCLAIMER: THIS CIRCUIT DESIGN ISPROVIDED AS REFERENCE ONLY,WITHOUT WARRANTY EXPRESSED ORIMPLIED. THE USER IS ENCOURAGEDTO PERFORM ALL DUE DILIGENCE WITHRESPECT TO DESIGN AND ANALYSIS. FOR COMMITTED PERFORMANCE ANDFUNCTIONALITY OF THE xxxx DEVICE,PLEASE REFER TO THE DEVICE DATAMANUAL.
Copyright (C) 20xx Texas Instruments Incorporated.All rights reserved.
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TOP
L2_GND
L3
L4_PWR
L5
L6_GND
L7_GND
L8
L9_PWR
L10
L11_GND
BOT
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3.6mils
4mils
4.8mils
5mils
4.4mils
4mils
4.4mils
5mils
4.8mils
4mils
3.6mils
p.p
core
core
p.p
p.p
core
p.p
core
core
p.p
p.p
1. PCB SIZE: 7.11" x 2.89" x 0.063"2. PCB MATERIAL: FR4_IT168G3. NUMBER OF LAYERS: 124. IMPEDANCE CONTROL: YES
1. RESISTANCE VALUES ARE IN OHMS.2. CAPACITANCE VALUES ARE IN MICROFARADS.3. PARTS NOT INSTALLED ARE INDICATED WITH 'NU'.4. SIGNAL NET NAMES WITH "#" SUFFIX, ARE ACTIVE LOW SIGNALS.
PCB MECHANICAL DETAILS :
NOTES, UNLESS OTHERWISE SPECIFIED :
TMDSEVM6657 SCHEMATIC
PCB LAYER STACK-UP DETAILS :
1.0
SCH. REV.PCB REV. DESCRIPTION DATE
Initial Draft0.6 03-FEB-2012
MAJOR REVISION HISTORY :
REF DES DESCRIPTION 7 BIT ADDRESS
EEPROM1 DSP EEPROM 0x50, 0x51
U264 0x50ETHERNET EEPROM
I2C ADDRESS TABLE :
1.1 Release for Alpha Boards 20-MAR-2012
2.5 Release for Beta Boards 26-JUL-20122.0
2.9 Redundant pull-up and termination NUon EMU_TCK
28-NOV-2013
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COVER PAGE
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COVER PAGE
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01 : COVER PAGE02 : TABLE OF CONTENTS03 : SYSTEM BLOCK DIAGRAM04 : PLACEMENT05 : POWER CONSUMPTION06 : POWER SEQUENCE07 : POWER DISTRIBUTION08 : CLOCK DIAGRAM09 : FPGA INTERFACE CONTROL10 : MANAGEMENT MAP11 : AMC CONNECTOR12 : MMC, HYPERLINK COMM13 : DSP - SERDES PORTS14 : DSP - DDR3 15 : DDR3 & ECC16 : DSP - EMIF & JTAG 17 : DSP - MISC18 : DSP - CLOCK & SMART REFLEX19 : CLOCK GENERATION20 : USB - JTAG21 : GIGABIT ETHERNET22 : FPGA - POWER, RESET CTRL, McBSP23 : FPGA - BOOT_MODE & SMART REFLEX24 : DSP - POWER 125 : DSP - POWER 226 : SMART REFLEX & CORE VOLT27 : POWER SUPPLY 128 : POWER SUPPLY 229 : REVISON HISTORY
SCHEMATIC PAGE DESCRIPTION :
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TABLE OF CONTENTS
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TABLE OF CONTENTS
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TABLE OF CONTENTS
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BLOCK DIAGRAM
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BLOCK DIAGRAM
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BLOCK DIAGRAM
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BLOCK DIAGRAM
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PLACEMENT
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PLACEMENT
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PLACEMENT
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PLACEMENT
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POWER CONSUMPTION
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POWER CONSUMPTION
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POWER CONSUMPTION
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POWER CONSUMPTION
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POWER SEQUENCE
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POWER SEQUENCE
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POWER SEQUENCE
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POWER SEQUENCE
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POWER DISTRIBUTION
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POWER DISTRIBUTION
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CLOCK DIAGRAM
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CLOCK DIAGRAM
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FPGA INTERFACE CONTROL DIAGRAM
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CLOCK DIAGRAM
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MANAGEMENT MAP
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MANAGEMENT MAP
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D D
C C
B B
A A
Front Panel and ESD Strip
Management Power
AMC CONNECTOR FAN CONNECTOR
OE# = 0DIR = 0 --> B to ADIR = 1 --> A to B
TR
IP1
TR
IP3
TR
IP2
MMC_PS_N1
MMC_PS_N1
MMC_PS_N0
DSP_SCL_AMCDSP_SDA_AMC
AMC_JTAG_TDI
AMC_JTAG_TDO
AMC_JTAG_TMS
AMC_JTAG_TCK
AMC_JTAG_RST#
DSP_SDADSP_SCL DSP_SCL_AMC
DSP_SDA_AMC
AMC_P12_McBSP_TX0AMC_P12_McBSP_TX1AMC_P12_McBSP_RX0AMC_P12_McBSP_RX1
DSP_SCL_AMCDSP_SDA_AMC
TRIP1
VCC3V3_MP_AMC
VCC3V3_AUX
VCC1V8
VCC3V3_AUX
VCC3V3_AUX
VCC12_AMC
VCC12
VCC3V3_AUX
VCC1V8_AUXVCC1V8
BISMB_SDA_IPMBL[12]
BIDSP_SDA[12,17]
INAMCC_P4_PCIe_TX1P[13]INAMCC_P4_PCIe_TX1N[13]
INAMCC_P5_PCIe_TX2P[13]INAMCC_P5_PCIe_TX2N[13]
IN AMC_JTAG_TDO [20]
INAMC_SGMII_TXP[21]INAMC_SGMII_TXN[21]
INMMC_GA0[12]
INMMC_GA1[12]
INMMC_GA2[12]
IN AMCC_P8_SRIO1_TXP [13]IN AMCC_P8_SRIO1_TXN [13]
IN AMCC_P9_SRIO2_TXN [13]IN AMCC_P9_SRIO2_TXP [13]
IN AMCC_P10_SRIO3_TXP [13]IN AMCC_P10_SRIO3_TXN [13]
IN AMCC_P11_SRIO4_TXP [13]IN AMCC_P11_SRIO4_TXN [13]
INDSP_SCL[12,17]
OUTAMC_SGMII_RXP[21]OUTAMC_SGMII_RXN[21]
OUTPCIE_REF_CLK_P[18]OUTPCIE_REF_CLK_N[18]
OUT AMCC_P11_SRIO4_RXP [13]OUT AMCC_P11_SRIO4_RXN [13]
OUTMMC_ENABLE_N[12]
OUT AMCC_P10_SRIO3_RXP [13]OUT AMCC_P10_SRIO3_RXN [13]
OUT AMCC_P8_SRIO1_RXP [13]OUT AMCC_P8_SRIO1_RXN [13]
OUT AMCC_P9_SRIO2_RXP [13]OUT AMCC_P9_SRIO2_RXN [13]
OUT AMC_JTAG_TDI [20]
OUT AMC_JTAG_TMS [20]OUT AMC_JTAG_RST# [20]
OUT AMC_JTAG_TCK [20]
OUTTCLKA_P[22]OUTTCLKA_N[22]
OUT TCLKC_P [22]OUT TCLKC_N [22]
OUTTCLKB_P[19]OUTTCLKB_N[19]
OUT TCLKD_N [22]OUT TCLKD_P [22]
OUTSMB_SCL_IPMBL[12]
OUTAMCC_P4_PCIe_RX1P[13]OUTAMCC_P4_PCIe_RX1N[13]
OUTAMCC_P5_PCIe_RX2P[13]OUTAMCC_P5_PCIe_RX2N[13]
IN DSP_McBSP0_TX [12,13]IN DSP_McBSP1_TX [12,13]
OUT DSP_McBSP1_RX [12,13]OUT DSP_McBSP0_RX [12,13]
INMcBSP_AMC_EN#[22]
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AMC CONNECTOR
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AMC CONNECTOR
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AMC CONNECTOR
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R157 0ENU
R90
4.7K
C326 100nF
R158 0ENU
C369 100nF
R175
4.7K
U13SN74AVC4T245PWR
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND18
GND29
2B210 2B111 1B212 1B113
2OE14 1OE15
VCCB16
R936 10M
R445 10K
R339100K
U245PCA9306DCUR
VREF12
SCL13
SDA14
GND1
EN8VREF27
SDA25SCL26
R160 0ENU
C1160
100nF
R446 10K
R1958
4.7K
R447 10K
FAN1
WB_3V_2.0mm
NU123
D3 B340A-13-F
AMC1GF-AMC-B
GND_11
GND_27
GND_310
PWR_12V_12
PS13
MP4
GA05
RSRVD66
RSRVD88
PWR_12V_29
Tx0+11
Tx0-12
GND_413
Rx0+14
Rx0-15
GND_516
GA117
PWR_12V_318
GND_619
Tx1+20
Tx1-21
GND_722
Rx1+23
Rx1-24
GND_825
GA226
PWR_12V_427
GND_928
Tx2+29
Tx2-30
GND_1031
Rx2+32
Rx2-33
GND_1134
Tx3+35
Tx3-36
GND_1237
Rx3+38
Rx3-39
GND_1340
ENABLE41
PWR_12V_542
GND_1443
Tx4+44
Tx4-45
GND_1546
Rx4+47
Rx4-48
GND_1649
Tx5+50
Tx5-51
GND_1752
Rx5+53
Rx5-54
GND_1855
SCL_L56
GND_1958
Tx6+59
Tx6-60
GND_2061
Rx6+62
Rx6-63
GND_2164
Tx7+65
Tx7-66
GND_2267
Rx7+68
Rx7-69
GND_2370
SDA_L71
PWR_12V_657
PWR_12V_772
GND_2473
TCLKA+74
TCLKA-75
GND_2576
TCLKB+77
TCLKB-78
GND_2679
FCLKA+80
FCLKA-81
GND_2782
PS083
PWR_12V_884
GND_2885
GND_2986Rx8-87Rx8+88
Tx8+91
Tx8-90
GND_3089
Rx9+94
Rx9-93
GND_3192
Tx9+97
Tx9-96
GND_3295
Rx10+100
Rx10-99
GND_3398
Tx10+103
Tx10-102
GND_34101
Rx11+106
Rx11-105
GND_35104
Tx11+109
Tx11-108
GND_36107
Rx12+112
Rx12-111
GND_37110
Tx12+115
Tx12-114
GND_38113
Rx13+118
Rx13-117
GND_39116
Tx13+121
Tx13-120
GND_40119
Rx14+124
Rx14-123
GND_41122
Tx14+127
Tx14-126
GND_42125
GND_43128
Rx15+130
Rx15-129
GND_44131Tx15-132Tx15+133GND_45134
TCLKC+136
TCLKC-135
TCLKD+139
TCLKD-138
GND_46137
Rx17+142
Rx17-141
GND_47140
Tx17+145
Tx17-144
GND_48143
Tx18+151
Tx18-150
GND_50149
Rx18+148
Rx18-147
GND_49146
Tx19+157
Tx19-156
GND_52155
Rx19+154
Rx19-153
GND_51152
Tx20+163
Tx20-162
GND_54161
Rx20+160
Rx20-159
GND_53158
GND_55164TCK165TMS166TRST167TDO168TDI169GND_56170
C526
1uFNU
R448 10K
R484 0E
C301 100nF
R161 0ENU
R449 10K
R937 10M
C355
100nF
C1128
100nF
C411
100nF
R487 0E
C302 100nF
ESD1
AMC-ESD-B
1 2 34
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MMC INTERFACE
MSP430 Power
SpyBiWire
IPASS+HD for HyperLink
DEBUG HEADER
(Red LED)
(Blue LED)
SPI Interface for FPGA debugging.
The NU resistors on these connections to the MSP430 are for debug use only and will be used only with the shunts removed from pins 1 and 2 of CN7
MMC_XTAL1
MMC_XTAL2
MMC_LED1MMC_LED2
MMC_GAPU
MMC_MOSIMMC_MISO
MMC_STE
MMC_P43
MMC_SCK
MMC_SBWTCKMMC_SBWTDIO
MMC_SBWTDIO
VCC3V3_MP
VCC3V3_MP_AMCVCC3V3_MP VCC3V3_AUX
VCC3V3_MP
VCC3V3_MP
VCC3V3_MP
VCC3V3_MP
BI SMB_SDA_IPMBL [11]
BI DSP_EMIFD4 [16]BI DSP_EMIFD5 [16]BI DSP_EMIFD6 [16]BI DSP_EMIFD7 [16]
BI DSP_EMIFD12 [16]BI DSP_EMIFD13 [16]BI DSP_EMIFD14 [16]BI DSP_EMIFD15 [16]
BI DSP_EMIFD8 [16]BI DSP_EMIFD9 [16]BI DSP_EMIFD10 [16]BI DSP_EMIFD11 [16]
BI DSP_EMIFD0 [16]BI DSP_EMIFD1 [16]BI DSP_EMIFD2 [16]BI DSP_EMIFD3 [16]
BI DSP_SDA [11,17]
BIDSP_GPIO_14[17,23]BIDSP_GPIO_15[17,23]
BIDSP_McBSP0_RXCLK[13,22]BIDSP_McBSP0_TXCLK[13,22]
IN MMC_RSTSTAT# [22]IN MMC_BOOTCOMP [22]
IN SMB_SCL_IPMBL [11]
IN UART_FT_TX [17,20]
IN MMC_SPI_MOSI [23]IN MMC_SPI_STE [23]
IN MMC_SPI_SCK [23]
IN HyperLink_RXFLCLK [13]
IN HyperLink_TXPMDAT [13]IN HyperLink_TXPMCLK [13]INHyperLink_RXFLDAT[13]
INHyperLink_TXP1[13]INHyperLink_TXN1[13]
INHyperLink_TXP0[13]INHyperLink_TXN0[13]
IN HyperLink_TXP2 [13]IN HyperLink_TXN2 [13]
IN HyperLink_TXP3 [13]IN HyperLink_TXN3 [13]
IN DSP_UART1_RTS [17]
IN DSP_UART1_TX [17]
INDSP_EMIFA00[16]INDSP_EMIFA01[16]INDSP_EMIFA02[16]
INDSP_EMIFA04[16]INDSP_EMIFA03[16]
INDSP_EMIFA06[16]INDSP_EMIFA05[16]
INDSP_EMIFA07[16]INDSP_EMIFA08[16]INDSP_EMIFA09[16]INDSP_EMIFA10[16]
INDSP_EMIFA12[16]INDSP_EMIFA11[16]
INDSP_EMIFA14[16]INDSP_EMIFA13[16]
INDSP_EMIFA15[16]INDSP_EMIFA16[16]INDSP_EMIFA17[16]INDSP_EMIFA18[16]
INDSP_EMIFA20[16]INDSP_EMIFA19[16]
INDSP_EMIFA21[16]
IN DSP_SSPMOSI [17,22]
IN DSP_EMIFOEZ [16]IN DSP_EMIFWEZ [16]
IN DSP_EMIFCE2Z [16]IN DSP_EMIFCE1Z [16]
IN DSP_TIMO0 [17,23]
IN DSP_SSPCS1 [17,22]IN PH_SSPCK [17]
IN DSP_TIMO1 [17,23]
IN DSP_EMIFRNW [16]
INDSP_EMIFA23[16]
IN DSP_EMIFBE0Z [16]IN DSP_EMIFBE1Z [16]INDSP_EMIFA22[16]
IN DSP_SCL [11,17]
IN MMC_ENABLE_N [11]
OUT MMC_WR_AMC# [22]OUT MMC_POR_AMC# [22]
OUT MMC_DETECT# [22]
OUT UART_FT_RX [17,20]
OUT MMC_SPI_MISO [23]
OUT MMC_GA0 [11]OUT MMC_GA1 [11]OUT MMC_GA2 [11]
OUTHyperLink_TXFLDAT[13]OUTHyperLink_RXPMDAT[13] OUT HyperLink_TXFLCLK [13]
OUTHyperLink_RXPMCLK[13]
OUTHyperLink_RXP0[13]OUTHyperLink_RXN0[13]
OUTHyperLink_RXP2[13]OUTHyperLink_RXN2[13] OUT HyperLink_RXP3 [13]
OUT HyperLink_RXN3 [13]
OUT HyperLink_RXP1 [13]OUT HyperLink_RXN1 [13]
OUT DSP_UART1_CTS [17]
OUT DSP_SSPMISO [17,22]
OUT DSP_UART1_RX [17]
OUT DSP_TIMI0 [17,23]
OUT DSP_TIMI1 [17,23]
OUT DSP_EMIFWAIT1 [16]
BIDSP_McBSP0_FST[13,22]BIDSP_McBSP0_FSR[13,22]OUTDSP_McBSP0_SLCLK[13,22]
BIDSP_McBSP1_FST[13,22]BIDSP_McBSP1_FSR[13,22]OUTDSP_McBSP1_SLCLK[13,22]
BIDSP_McBSP1_RXCLK[13,22]BIDSP_McBSP1_TXCLK[13,22]
INDSP_McBSP1_TX[11,13]OUTDSP_McBSP1_RX[11,13]
OUTDSP_McBSP0_RX[11,13]INDSP_McBSP0_TX[11,13]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
MMC, HYPERLINK & 80 CONN
C
12 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
MMC, HYPERLINK & 80 CONN
C
12 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
MMC, HYPERLINK & 80 CONN
C
12 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
R1186 33E
R15
3.3K
TP7
R960 0ENU
C4
100nF
R3
330E
R961 0ENU
C10100nF
R399 10E
R18
0ENU
C2
100nF
R1188 33E
C7
0.47uF
iPass Plus HD 1x1 Assy
Hyperlink1IPASS+HD_36H
<Characteristic>
sideband5D1
sideband6D2
GND_D3D3
Txp0D4
Txn0D5
GND_D6D6
Txp2D7
Txn2D8
GND_D9D9
sideband3B1
sideband1B2
GND_B3B3
Rxp0B4
Rxn0B5
GND_B6B6
Rxp2B7
Rxn2B8
GND_B9B9
sideband4C1
sideband2C2
GND_C3C3
Txp1C4
Txn1C5
GND_C6C6
Txp3C7
Txn3C8
GND_C9C9
sideband7A1
sideband0A2
GND_A3A3
Rxp1A4
Rxn1A5
GND_A6A6
Rxp3A7
Rxn3A8
GND_A9A9
NP
TH
1H
1
NP
TH
2H
2
R6 0ENU
R20
0ENU
R16
10K
TEST_PH1SFM-140-L2-S-D-LC
135791113151719
2468
101214161820
212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
H2
H1
R1189 33E
R1183 33E
D9 PMEG4005AEA21
R4
330E
TP8 TP9
C371
1000pF
R962 0ENU
SBW_MMC1W_4V_2.54mm
1234
G
S
DQ12N7002
1
32
R13
3.3K
R963 0ENU
R1
33K
D10 PMEG4005AEA21
C8 22pF
R11
10K
NU
TP17 R1177 33E
R7 0ENU
B1 120_100MHz
Y1
ABS10-32.768KHZ-T
12
R10
10K
R2
33K
R14
3.3K
MSP430F5435IPNRMMC1
P6.4/A41
P6.5/A52
P6.6/A63
P6.7/A74
P7.4/A125
P7.5/A136
P7.6/A147
P7.7/A158
P5.0/A8/VREF+/VEREF+9P5.1/A9/VREF-/VEREF-10
AVCC11
AVSS12
P7.0/XIN13
P7.1/XOUT14
DVSS115
DVCC116
P1.0/TA0CLK/ACLK17
P1.1/TA0.018
P1.2/TA0.119
P1.3/TA0.220
P1.4/TA0.321
P1.5/TA0.422
P1.6/SMCLK23
P1.724
P2.0/TA1CLK/MCLK25
P2.1/TA1.026P2.2/TA1.127P2.3/TA1.228P2.4/RTCCLK29
DVSS330
DVCC331
P2.532
P2.6/ACLK33
P2.7/ADC12CLK/DMAE034
P3.0/UCB0STE/UCA0CLK35
P3.1/UCB0SIMO/UCB0SDA36P3.2/UCB0SOMI/UCB0SCL37
P3.3/UCB0CLK/UCA0STE38
P3.4/UCA0TXD/UCA0SIMO39P3.5/UCA0RXD/UCA0SOMI40
P3.6/UCB1STE/UCA1CLK41P3.7/UCB1SIMO/UCB1SDA42
P4.0/TB0.043 P4.1/TB0.144 P4.2/TB0.245 P4.3/TB0.346 P4.4/TB0.447 P4.5/TB0.548
VCORE49
DVSS250
DVCC251
P4.6/TB0.652 P4.7/TB0CLK/SMCLK53
P5.4/UCB1SOMI/UCB1SCL54P5.5/UCB1CLK/UCA1STE55P5.6/UCA1TXD/UCA1SIMO56P5.7/UCA1RXD/UCA1SOMI57
P7.2/TB0OUTH/SVMOUT58
P7.3/TA1.259
P8.0/TA0.060
P8.1/TA0.161
P8.2/TA0.262
P8.3/TA0.363
P8.4/TA0.464
P8.5/TA1.065
P8.6/TA1.166
DVCC467
DVSS468
P5.2/XT2IN69P5.3/XT2OUT70
TEST/SBWTCK71
PJ.0/TDO72
PJ.1/TDI/TCLK73
PJ.2/TMS74
PJ.3/TCK75
RST#/NMI/SBWTDIO76
P6.0/A077
P6.1/A178
P6.2/A279
P6.3/A380
BD2 LED1 2
R1179 33E
C524100nF
C3
100nF
C6
100nF
C1
100nF
RD1 LED1 2
C5 22pF
R19
0ENU
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The HyperLink routes must have a max of 2 vias and no via stubs (Outer layer routing recommended)
SGMII
PCIE
HYPERLINK
SRIO
McBSP
VOLTAGE LEVEL TRANSLATOR
Place ALL SERDES DC-blocking caps on top layer adjacent to the DSP's RX pins so that there are no additional vias
HL_REF_CLKPHL_REF_CLKN
DSP_MDCDSP_MDIO
DSP_MDIODSP_MDC
VCC1V8VCC1V8
VCC2V5VCC3V3_AUX
BI ETH_MDIO [21]
BI DSP_McBSP1_FST [12,22]BI DSP_McBSP1_FSR [12,22]
BI DSP_McBSP1_TXCLK [12,22]BI DSP_McBSP1_RXCLK [12,22]
BIDSP_McBSP0_TXCLK[12,22]BIDSP_McBSP0_RXCLK[12,22]
BIDSP_McBSP0_FST[12,22]BIDSP_McBSP0_FSR[12,22]
INAMCC_P4_PCIe_RX1P[11]INAMCC_P4_PCIe_RX1N[11]
INAMCC_P5_PCIe_RX2P[11]INAMCC_P5_PCIe_RX2N[11]
INAMCC_P11_SRIO4_RXN[11]INAMCC_P11_SRIO4_RXP[11]
INAMCC_P8_SRIO1_RXP[11]
INAMCC_P10_SRIO3_RXP[11]
INAMCC_P8_SRIO1_RXN[11]
INAMCC_P9_SRIO2_RXP[11]INAMCC_P9_SRIO2_RXN[11]
INAMCC_P10_SRIO3_RXN[11]
INHyperLink_RXP0[12]INHyperLink_RXN0[12]
INHyperLink_RXP1[12]INHyperLink_RXN1[12]
INHyperLink_RXN3[12]INHyperLink_RXP3[12]
INHyperLink_RXN2[12]INHyperLink_RXP2[12]
IN HyperLink_TXFLCLK [12]IN HyperLink_TXFLDAT [12]
INHyperLink_RXPMCLK[12]INHyperLink_RXPMDAT[12]
INDSP_McBSP0_RX[11,12] IN DSP_McBSP1_RX [11,12]
IN DSP_McBSP1_SLCLK [12,22]INDSP_McBSP0_SLCLK[12,22]
INDSP_SGMII_RXP[21]INDSP_SGMII_RXN[21]
OUT AMCC_P9_SRIO2_TXN [11]OUT AMCC_P9_SRIO2_TXP [11]
OUT AMCC_P11_SRIO4_TXP [11]
OUT AMCC_P8_SRIO1_TXN [11]
OUT AMCC_P10_SRIO3_TXP [11]
OUT AMCC_P11_SRIO4_TXN [11]
OUT AMCC_P8_SRIO1_TXP [11]
OUT AMCC_P10_SRIO3_TXN [11]
OUT HyperLink_TXP0 [12]OUT HyperLink_TXN0 [12]
OUT HyperLink_TXP1 [12]OUT HyperLink_TXN1 [12]
OUT HyperLink_TXP2 [12]OUT HyperLink_TXN2 [12]
OUT HyperLink_TXP3 [12]OUT HyperLink_TXN3 [12]
OUTHyperLink_RXFLCLK[12]OUTHyperLink_RXFLDAT[12]
OUT HyperLink_TXPMCLK [12]OUT HyperLink_TXPMDAT [12]
OUTDSP_McBSP0_TX[11,12] OUT DSP_McBSP1_TX [11,12]
OUT AMCC_P4_PCIe_TX1P [11]OUT AMCC_P4_PCIe_TX1N [11]
OUT AMCC_P5_PCIe_TX2P [11]OUT AMCC_P5_PCIe_TX2N [11]
OUT DSP_SGMII_TXN [21]OUT DSP_SGMII_TXP [21]
OUT ETH_MDC [21]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP SERDES PORTS
C
13 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP SERDES PORTS
C
13 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP SERDES PORTS
C
13 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
C20 100nF
C168 100nF
TMS320C6657DSP1R
MCMRXN2J25 MCMRXP2K25
MCMRXN3K24 MCMRXP3L24
MCMRXN1M25 MCMRXP1N25
MCMRXN0P24 MCMRXP0N24
MCMRXFLCLKB24
MCMRXFLDATC24
MCMRXPMCLKE24
MCMRXPMDATD24
MCMTXP3K21
MCMTXN3J21
MCMTXP0N22
MCMTXN0P22
MCMTXP1M21
MCMTXN1N21
MCMTXN2K22MCMTXP2L22
MCMREFCLKOUTPG25
MCMREFCLKOUTNF25
MCMTXFLCLKE25
MCMTXFLDATD25
MCMTXPMCLKF24
MCMTXPMDATG24
C306 100nF
TMS320C6657DSP1P
RIORXN3AD4 RIORXP3AD5
RIORXN2AE5 RIORXP2AE6
RIORXP0AE8
RIORXN0AE9
RIORXN1AD8 RIORXP1AD7
RIOTXN2AC5RIOTXP2AC6
RIOTXN3AB4RIOTXP3AB5
RIOTXP1AB8
RIOTXN1AB7
RIOTXP0AC8
RIOTXN0AC9
C19 100nF
C170 100nFC171 100nF
TMS320C6657DSP1T
DX0AC22
FSX0AA20 FSR0AD24
CLKX0Y20
DR0AB21
CLKR0AA21
CLKS0AC23
CLKR1AD23
CLKX1AE24
CLKS1AC21
FSR1AD22
FSX1AE23
DR1AD21
DX1AE22
R85
4.7KNU
R2959
4.7K
C172 100nF
C470 100nF
C173 100nF
U244PCA9306DCUR
VREF12
SCL13
SDA14
GND1
EN8VREF27
SDA25SCL26
R316
100KR82
10K
C327
100nF
C511 100nF
C164 100nF
C401100nF
C505 100nF
TP5
C167 100nF
TMS320C6657DSP1O
SGMII0RXPAE3
SGMII0RXNAE2
SGMII0TXPAC3
SGMII0TXNAC2
MDIOAB16
MDCLKAA16
R2958
4.7K
TP6
C512 100nF
C165 100nF
R456 22E
C307 100nF
R83
10K
C12 100nF
C166 100nF
R457 22E
C308 100nF
TMS320C6657DSP1Q
PCIERXN1AD10 PCIERXP1AD11
PCIERXN0AE12 PCIERXP0AE11
PCIETXP1AB10
PCIETXN1AB11
PCIETXN0AC12PCIETXP0AC11
C169 100nF
C14 100nF
C305 100nF
R957
4.7KNU
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place these resistors at the end of the trace.
20 mil trace width
DDR3 INTERFACE
DDR3 Slew-Rate Setting (DDRSLRATE[1:0]):
00 Fastest01 Fast10 Slow11 Slowest
DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12DSP0_DDR3_EA13
DSP0_DDR3_EDQ0DSP0_DDR3_EDQ1DSP0_DDR3_EDQ2DSP0_DDR3_EDQ3DSP0_DDR3_EDQ4DSP0_DDR3_EDQ5DSP0_DDR3_EDQ6DSP0_DDR3_EDQ7DSP0_DDR3_EDQ8DSP0_DDR3_EDQ9
DSP0_DDR3_EDQ10DSP0_DDR3_EDQ11DSP0_DDR3_EDQ12DSP0_DDR3_EDQ13DSP0_DDR3_EDQ14DSP0_DDR3_EDQ15DSP0_DDR3_EDQ16DSP0_DDR3_EDQ17DSP0_DDR3_EDQ18DSP0_DDR3_EDQ19DSP0_DDR3_EDQ20DSP0_DDR3_EDQ21DSP0_DDR3_EDQ22DSP0_DDR3_EDQ23DSP0_DDR3_EDQ24DSP0_DDR3_EDQ25DSP0_DDR3_EDQ26DSP0_DDR3_EDQ27DSP0_DDR3_EDQ28DSP0_DDR3_EDQ29DSP0_DDR3_EDQ30DSP0_DDR3_EDQ31
U1_DDRSLRATE0U1_DDRSLRATE1
U1_DDRSLRATE0 U1_DDRSLRATE1
DSP0_DDR3_EA14
DSP0_DDR3_ECC0DSP0_DDR3_ECC1DSP0_DDR3_ECC2DSP0_DDR3_ECC3
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
DSP0_DDR3_ECS_0#
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
DSP0_DDR3_EODT_0
DSP0_DDR3_EWE#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECAS#
DSP0_DDR3_ECKE_0
DSP0_DDR3_EA14
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP_VREFSSTL
DSP0_DDR3_EA15
DSP0_DDR3_EA15
DSP0_DDR3_EMRESETN
VCC1V8 VCC1V8
VCC0V75
VCC0V75
VCC1V5
VCC1V5
VCC1V5
BIDSP0_DDR3_ECC[3:0][15]
BI DSP0_DDR3_EDQ[15:8] [15]
BI DSP0_DDR3_EDQ[7:0] [15]
BI DSP0_DDR3_EDQ[31:24] [15]
BI DSP0_DDR3_EDQ[23:16] [15]
OUT DSP0_DDR3_EA[15:0] [15]
OUTDSP0_DDR3_EBA_0[15]OUTDSP0_DDR3_EBA_1[15]OUTDSP0_DDR3_EBA_2[15]
OUTDSP0_DDR3_EDM_0[15]OUTDSP0_DDR3_EDM_1[15]OUTDSP0_DDR3_EDM_2[15]OUTDSP0_DDR3_EDM_3[15]OUTDSP0_DDR3_EDM_4[15]
OUTDSP0_DDR3_ECKP_0[15]OUTDSP0_DDR3_ECKN_0[15]
OUTDSP0_DDR3_EODT_0[15]
OUTDSP0_DDR3_EMRESETN[15]
OUTDSP0_DDR3_ECAS#[15]
OUTDSP0_DDR3_EWE#[15]OUTDSP0_DDR3_ERAS#[15]
OUTDSP0_DDR3_ECKE_0[15]
OUTDSP0_DDR3_ECS_0#[15]
OUTDSP0_DDR3_EDQSP_0[15]OUTDSP0_DDR3_EDQSN_0[15]
OUTDSP0_DDR3_EDQSN_1[15]OUTDSP0_DDR3_EDQSP_1[15]
OUTDSP0_DDR3_EDQSN_2[15]OUTDSP0_DDR3_EDQSP_2[15]
OUTDSP0_DDR3_EDQSN_3[15]OUTDSP0_DDR3_EDQSP_3[15]
OUTDSP0_DDR3_EDQSN_4[15]OUTDSP0_DDR3_EDQSP_4[15]
OUT DSP_VREFSSTL [15,28]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP DDR3
C
14 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP DDR3
C
14 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP DDR3
C
14 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
R41 39.2E
R56 39.2E
R51 39.2E
R38 39.2E
C33 10nF
R50 39.2E
C39 10nF
TMS320C6657DSP1K
DDRCLKOUTP0A14
DDRCLKOUTN0B14
DDRCLKOUTP1A21
DDRCLKOUTN1B21
DDRCKE0A16
DDRCKE1A20
DDRCE0zB15
DDRCE1zC14
DDRCASzD14
DDRRASzA15
DDRWEzE13
DDRBA0C18
DDRBA1D17
DDRBA2B19
DDRDQM0A8
DDRDQM1E7
DDRDQM2F5
DDRDQM3E1
DDRDQM8C12
DDRDQS0PD10
DDRDQS0NC10
DDRDQS1PB7
DDRDQS1NA7
DDRDQS2PB4
DDRDQS2NA4
DDRDQS3PA2
DDRDQS3NB2
DDRDQS8PB13
DDRDQS8NA13
DDRCB00D11
DDRCB01B12
DDRCB02C11
DDRCB03A12
DDRRESETzB16
DDRODT0E14
DDRODT1D12
DDRSLRATE0C22
DDRSLRATE1D22
VREFSSTLE12
PTV15F15
DDRA00D16
DDRA01A19
DDRA02E16
DDRA03E15
DDRA04B18
DDRA05A17
DDRA06C16
DDRA07A18
DDRA08D20
DDRA09E20
DDRA10E19
DDRA11B20
DDRA12D18
DDRA13C20
DDRA14E18
DDRA15E17
DDRD00A9
DDRD01C9
DDRD02D9
DDRD03B9
DDRD04E9
DDRD05E10
DDRD06A11
DDRD07B11
DDRD08E6
DDRD09E8
DDRD10A6
DDRD11A5
DDRD12D6
DDRD13C7
DDRD14D7
DDRD15B8
DDRD16E5
DDRD17B3
DDRD18F4
DDRD19E4
DDRD20A3
DDRD21B5
DDRD22C5
DDRD23D5
DDRD24E2
DDRD25F2
DDRD26B1
DDRD27C1
DDRD28D1
DDRD29D3
DDRD30C3
DDRD31E3
C42 100nF
R59 39.2E
R61 39.2E
R42 39.2E
R57 39.2E C40 100nF
C37 10nF
R62 39.2E
R43 39.2E
C44 100nF
C59
100nF10V
R60 39.2E
R45 39.2E
C43 10nF
R64 39.2E
C35 10nF
R37 39.2E
R77
1K
1%
R46 39.2E
C41 10nF
R65 39.2E
C38 100nF
R86 39.2E
R78
1K
1%
R44 39.2E
R69
2K
NU 1%
R63 39.2E
R66 4.7K1%
R52 39.2E
R58
45.3E
1%C114
100nF10V
R48 39.2E
R55 39.2E
C60
100nF10V
R49 39.2E
R53 39.2E
R71
2K
1%
C34 100nF
C36 100nF
C31 100nF
R47 39.2E
R70
2K
1%
R72
2K
NU1%
R54 39.2E
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
20 mil trace width
- Data bits can be swapped within the bytelane to ease routing.
- Address/Command/Control/Clock routing must be Fly-By in byte order ECC, 0, 1, 2, 3.
DDR3 MEMORY INTERFACE
MT41J128M16HA-125
Mfgr 1024MB (512MB x 2)
MT41J256M16RE-125Micron
Supported Memories (96 FBGA) :
512MB (256MB x 2)
20 mil trace width
DDR3 ECC INTERFACE
MT41J128M16HA-125
Mfgr
MT41J256M16RE-125Micron
Supported ECC Chip (96 FBGA) :
512MB
20 mil trace width
256MB
DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12
DSP0_DDR3_EDQ15
DSP0_DDR3_EDQ8DSP0_DDR3_EDQ9DSP0_DDR3_EDQ10DSP0_DDR3_EDQ11DSP0_DDR3_EDQ12DSP0_DDR3_EDQ13DSP0_DDR3_EDQ14
DSP_VREFSSTL
DSP0_DDR3_EDQ30DSP0_DDR3_EDQ31
DSP0_DDR3_EDQ24DSP0_DDR3_EDQ25DSP0_DDR3_EDQ26DSP0_DDR3_EDQ27DSP0_DDR3_EDQ28DSP0_DDR3_EDQ29
DSP0_DDR3_EDQ22DSP0_DDR3_EDQ23
DSP0_DDR3_EDQ16DSP0_DDR3_EDQ17DSP0_DDR3_EDQ18DSP0_DDR3_EDQ19DSP0_DDR3_EDQ20DSP0_DDR3_EDQ21
DSP0_DDR3_EDQ0DSP0_DDR3_EDQ1DSP0_DDR3_EDQ2DSP0_DDR3_EDQ3DSP0_DDR3_EDQ4DSP0_DDR3_EDQ5DSP0_DDR3_EDQ6DSP0_DDR3_EDQ7
DSP0_DDR3_EODT_0
DSP0_DDR3_EBA_0DSP0_DDR3_EBA_1DSP0_DDR3_EBA_2
DSP0_DDR3_EDQSP_1DSP0_DDR3_EDQSN_1
DSP0_DDR3_EMRESETN
DSP0_DDR3_EWE#DSP0_DDR3_ECAS#DSP0_DDR3_ERAS#DSP0_DDR3_ECS_0#
DSP0_DDR3_ECKP_0DSP0_DDR3_ECKN_0DSP0_DDR3_ECKE_0
DSP0_DDR3_EDQSP_0DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDM_0DSP0_DDR3_EDM_1
DSP0_DDR3_EDQSP_2DSP0_DDR3_EDQSN_2
DSP0_DDR3_EODT_0
DSP0_DDR3_EDQSP_3DSP0_DDR3_EDQSN_3
DSP0_DDR3_EBA_0DSP0_DDR3_EBA_1DSP0_DDR3_EBA_2
DSP0_DDR3_EDM_2DSP0_DDR3_EDM_3
DSP0_DDR3_EWE#DSP0_DDR3_ECAS#DSP0_DDR3_ERAS#DSP0_DDR3_ECS_0#
DSP0_DDR3_EMRESETN
DSP0_DDR3_ECKP_0DSP0_DDR3_ECKN_0DSP0_DDR3_ECKE_0
DSP_VREFSSTL
DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12
DSP0_DDR3_EA15DSP0_DDR3_EA15
DSP0_DDR3_EA13
DSP0_DDR3_EA14
DSP0_DDR3_EA13
DSP0_DDR3_EA14
DSP0_DDR3_EODT_0
DSP0_DDR3_EMRESETN
DSP0_DDR3_ECC2DSP0_DDR3_ECC3
DSP0_DDR3_ECC0DSP0_DDR3_ECC1
DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12DSP0_DDR3_EA13
DSP0_DDR3_EBA_0DSP0_DDR3_EBA_1DSP0_DDR3_EBA_2
DSP0_DDR3_EWE#DSP0_DDR3_ECAS#DSP0_DDR3_ERAS#DSP0_DDR3_ECS_0#
DSP0_DDR3_EA15DSP0_DDR3_EA14
DSP0_DDR3_EDQSP_4DSP0_DDR3_EDQSN_4
DSP0_DDR3_ECKP_0DSP0_DDR3_ECKN_0DSP0_DDR3_ECKE_0
DSP_VREFSSTL
DSP0_DDR3_EDM_4
VCC1V5
VCC1V5
VCC1V5VCC1V5
BI DSP0_DDR3_EDQ[15:8] [14]BI DSP0_DDR3_EDQ[31:24] [14]
BI DSP0_DDR3_EDQ[7:0] [14]BI DSP0_DDR3_EDQ[23:16] [14]
BI DSP0_DDR3_ECC[3:0] [14]
INDSP0_DDR3_EA[15:0][14,15]
INDSP0_DDR3_EODT_0[14,15]
INDSP0_DDR3_EBA_0[14,15]INDSP0_DDR3_EBA_1[14,15]INDSP0_DDR3_EBA_2[14,15]
INDSP0_DDR3_EDQSP_1[14]INDSP0_DDR3_EDQSN_1[14]
INDSP0_DDR3_EMRESETN[14,15]
INDSP0_DDR3_EWE#[14,15]INDSP0_DDR3_ECAS#[14,15]INDSP0_DDR3_ERAS#[14,15]INDSP0_DDR3_ECS_0#[14,15]
INDSP0_DDR3_ECKP_0[14,15]INDSP0_DDR3_ECKN_0[14,15]INDSP0_DDR3_ECKE_0[14,15]
INDSP0_DDR3_EDQSP_0[14]INDSP0_DDR3_EDQSN_0[14]
INDSP0_DDR3_EDM_1[14]INDSP0_DDR3_EDM_0[14]
INDSP0_DDR3_EDQSP_2[14]INDSP0_DDR3_EDQSN_2[14]
INDSP0_DDR3_EODT_0[14,15]
INDSP0_DDR3_EDQSP_3[14]INDSP0_DDR3_EDQSN_3[14]
INDSP0_DDR3_EBA_0[14,15]INDSP0_DDR3_EBA_1[14,15]INDSP0_DDR3_EBA_2[14,15]
INDSP0_DDR3_EDM_2[14]INDSP0_DDR3_EDM_3[14]
INDSP0_DDR3_ERAS#[14,15]INDSP0_DDR3_ECS_0#[14,15]
INDSP0_DDR3_EWE#[14,15]INDSP0_DDR3_ECAS#[14,15]
INDSP0_DDR3_EMRESETN[14,15]
INDSP0_DDR3_ECKP_0[14,15]INDSP0_DDR3_ECKN_0[14,15]INDSP0_DDR3_ECKE_0[14,15]
IN DSP_VREFSSTL [14,28]
INDSP0_DDR3_EA[15:0][14,15]INDSP0_DDR3_EA[15:0][14,15]
INDSP0_DDR3_EA[15:0][14,15]
INDSP0_DDR3_EDQSP_4[14]INDSP0_DDR3_EDQSN_4[14]
INDSP0_DDR3_EDM_4[14]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DDR3 & ECC
C
15 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DDR3 & ECC
C
15 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DDR3 & ECC
C
15 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
C113 100nF
C88100nF
C107100nF
R380 4.7K
R353 4.7K
C86100nF
R381 4.7K
R1487 4.7K
C7022uF
C109100nF
R87 240E
1%
C85100nF
C65100nF
R383 4.7K
C111100nF
R389 4.7K
C90100nF
C69100nF
C108100nF
C110100nF
R1160 4.7K
C67100nF
U16MT41J128M16HA-125
VDD_1B2
VDD_2D9
VDD_3G7
VDD_4K2
VDD_5K8
VDD_6N1
VDD_7N9
VDD_8R1
VDD_9R9
VDDQ_1A1
VDDQ_2A8
VDDQ_3C1
VDDQ_4C9
VDDQ_5D2
VDDQ_6E9
VDDQ_7F1
VDDQ_8H2
VDDQ_9H9
VREFCAM8
VREFDQH1
DQL0E3
DQL1F7
DQL2F2
DQL3F8
DQL4H3
DQL5H8
DQL6G2
DQL7H7
DQU0D7
DQU1C3
DQU2C8
DQU3C2
DQU4A7
DQU5A2
DQU6B8
DQU7A3
VSS_1A9
VSS_2B3
VSS_4G8
VSS_5J2
VSS_6J8
VSS_7M1
VSS_8M9
VSS_9P1
VSS_10P9
VSS_11T1
VSS_12T9
VSSQ_1B1
VSSQ_2B9
VSSQ_3D1
VSSQ_4D8
VSS_3E1
VSSQ_5E2
VSSQ_6E8
VSSQ_7F9
VSSQ_8G1
VSSQ_9G9
A0N3
A1P7
A2P3
A3N2
A4P8
A5P2
A6R8
A7R2
A8T8
A9R3
A10/APL7
A11R7
A12/BCN7
BA0M2
BA1N8
BA2M3
WEL3
CASK3
RASJ3
CSL2
DQSLF3
DQSLG3
DQSUC7
DQSUB7
DMLE7
DMUD3
CKJ7
CKK7
CKEK9
ODTK1
RESETT2
ZQL8
NC_1J1
NC_2J9
NC_3L1
NC_4L9
NC_5M7
A13T3
NC_7T7
C328 100nF
R382 4.7K
C163 100nF
R1484 4.7K
C66100nF
U5MT41J128M16HA-125
VDD_1B2
VDD_2D9
VDD_3G7
VDD_4K2
VDD_5K8
VDD_6N1
VDD_7N9
VDD_8R1
VDD_9R9
VDDQ_1A1
VDDQ_2A8
VDDQ_3C1
VDDQ_4C9
VDDQ_5D2
VDDQ_6E9
VDDQ_7F1
VDDQ_8H2
VDDQ_9H9
VREFCAM8
VREFDQH1
DQL0E3
DQL1F7
DQL2F2
DQL3F8
DQL4H3
DQL5H8
DQL6G2
DQL7H7
DQU0D7
DQU1C3
DQU2C8
DQU3C2
DQU4A7
DQU5A2
DQU6B8
DQU7A3
VSS_1A9
VSS_2B3
VSS_4G8
VSS_5J2
VSS_6J8
VSS_7M1
VSS_8M9
VSS_9P1
VSS_10P9
VSS_11T1
VSS_12T9
VSSQ_1B1
VSSQ_2B9
VSSQ_3D1
VSSQ_4D8
VSS_3E1
VSSQ_5E2
VSSQ_6E8
VSSQ_7F9
VSSQ_8G1
VSSQ_9G9
A0N3
A1P7
A2P3
A3N2
A4P8
A5P2
A6R8
A7R2
A8T8
A9R3
A10/APL7
A11R7
A12/BCN7
BA0M2
BA1N8
BA2M3
WEL3
CASK3
RASJ3
CSL2
DQSLF3
DQSLG3
DQSUC7
DQSUB7
DMLE7
DMUD3
CKJ7
CKK7
CKEK9
ODTK1
RESETT2
ZQL8
NC_1J1
NC_2J9
NC_3L1
NC_4L9
NC_5M7
A13T3
NC_7T7
C68100nF
R390 4.7K
U6MT41J128M16HA-125
NU
VDD_1B2
VDD_2D9
VDD_3G7
VDD_4K2
VDD_5K8
VDD_6N1
VDD_7N9
VDD_8R1
VDD_9R9
VDDQ_1A1
VDDQ_2A8
VDDQ_3C1
VDDQ_4C9
VDDQ_5D2
VDDQ_6E9
VDDQ_7F1
VDDQ_8H2
VDDQ_9H9
VREFCAM8
VREFDQH1
DQL0E3
DQL1F7
DQL2F2
DQL3F8
DQL4H3
DQL5H8
DQL6G2
DQL7H7
DQU0D7
DQU1C3
DQU2C8
DQU3C2
DQU4A7
DQU5A2
DQU6B8
DQU7A3
VSS_1A9
VSS_2B3
VSS_4G8
VSS_5J2
VSS_6J8
VSS_7M1
VSS_8M9
VSS_9P1
VSS_10P9
VSS_11T1
VSS_12T9
VSSQ_1B1
VSSQ_2B9
VSSQ_3D1
VSSQ_4D8
VSS_3E1
VSSQ_5E2
VSSQ_6E8
VSSQ_7F9
VSSQ_8G1
VSSQ_9G9
A0N3
A1P7
A2P3
A3N2
A4P8
A5P2
A6R8
A7R2
A8T8
A9R3
A10/APL7
A11R7
A12/BCN7
BA0M2
BA1N8
BA2M3
WEL3
CASK3
RASJ3
CSL2
DQSLF3
DQSLG3
DQSUC7
DQSUB7
DMLE7
DMUD3
CKJ7
CKK7
CKEK9
ODTK1
RESETT2
ZQL8
NC_1J1
NC_2J9
NC_3L1
NC_4L9
NC_5M7
A13T3
NC_7T7
R76 240E
1%
C8722uF
R379 4.7K
R132 240E
1%
R387 4.7K
R388 4.7K
C89100nF
C11222uF
R348 4.7K
R1361 4.7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
C6657 - EMIF NAND FLASH
C6657 - JTAG & EMU TI-60 Header
DSP_EMIFD0DSP_EMIFD1DSP_EMIFD2DSP_EMIFD3DSP_EMIFD4DSP_EMIFD5DSP_EMIFD6DSP_EMIFD7
DSP_EMIFBE0ZDSP_EMIFBE1Z
DSP_EMIFD8DSP_EMIFD9DSP_EMIFD10DSP_EMIFD11DSP_EMIFD12DSP_EMIFD13DSP_EMIFD14DSP_EMIFD15
DSP_EMIFRNW
DSP_EMIFOEZDSP_EMIFWEZ
DSP_EMIFWAIT0DSP_EMIFWAIT1
DSP_EMIFCE0ZDSP_EMIFCE1ZDSP_EMIFCE2Z
DSP_EMU_01
DSP_EMU_14
EMU_EMU_01
EMU_TRST#DSP_EMU_16
EMU_TCK
EMU_TDI_R
EMU_EMU_00
DSP_EMU_10
DSP_EMU_17
DSP_EMU_03DSP_EMU_02
DSP_TRST#
DSP_EMU_03
EMU_TDI
DSP_EMU_02
DSP_EMU_05
DSP_EMU_07DSP_EMU_06
DSP_EMU_04
EMU_RTCK
DSP_TDI
DSP_TDODSP_TCK
DSP_TMS
DSP_EMU_18
EMU_TMS_R
DSP_EMU_11
DSP_EMU_09
DSP_EMU_11DSP_EMU_10
DSP_EMU_13
DSP_EMU_15DSP_EMU_14
DSP_EMU_12
DSP_EMU_08
DSP_EMU_05
DSP_EMU_04
DSP_EMU_16
DSP_EMU_18DSP_EMU_17
DSP_EMU_07
EMU_TDO
EMU_01_R
EMU_TRST#_R
DSP_EMU_13
DSP_EMU_09
DSP_EMU_06
EMU_01_R
EXT_EMU_DET0
EMU_TCK_R
TRGRSTZ
DSP_EMU_15
EMU_TMS
DSP_EMU_00
EMU_TDO_R
EMU_00_R
DSP_EMU_08
DSP_EMU_12
EMU_TRST#_R
EMU_00_R
EMU_TMS_R
EMU_TDI_R
EMU_TDO_R
EMU_TCK_R
DSP_EMIFD0DSP_EMIFD1DSP_EMIFD2DSP_EMIFD3DSP_EMIFD4DSP_EMIFD5DSP_EMIFD6DSP_EMIFD7
DSP_EMIFOEZ
DSP_EMIFWAIT0
DSP_EMIFCE0Z
DSP_EMIFA12DSP_EMIFA11
DSP_EMIFWEZ
EMU_RTCK
EMU_TCK
VCC1V8
VCC1V8
VCC3V3_AUX
VCC1V8
VCC1V8
VCC1V8
VCC1V8
VCC1V8
VCC1V8
VCC1V8
VCC1V8
BIDSP_EMIFD0[12]BIDSP_EMIFD1[12]BIDSP_EMIFD2[12]BIDSP_EMIFD3[12]BIDSP_EMIFD4[12]BIDSP_EMIFD5[12]BIDSP_EMIFD6[12]BIDSP_EMIFD7[12]
BIDSP_EMIFD12[12]BIDSP_EMIFD13[12]BIDSP_EMIFD14[12]BIDSP_EMIFD15[12]
BIDSP_EMIFD8[12]BIDSP_EMIFD9[12]BIDSP_EMIFD10[12]BIDSP_EMIFD11[12]
BI DSP_EMU_00 [20]BI DSP_EMU_01 [20]
BIEMU_EMU_00[20]
BI EMU_EMU_01 [20]
INDSP_EMIFWAIT1[12]
INDSP_TDI[20]INDSP_TCK[20]
INDSP_TMS[20]INDSP_TRST#[20]
INEMU_TDO[20]
IN NAND_WP# [22]
OUT DSP_EMIFBE0Z [12]OUT DSP_EMIFBE1Z [12]
OUT DSP_EMIFA00 [12]OUT DSP_EMIFA01 [12]OUT DSP_EMIFA02 [12]OUT DSP_EMIFA03 [12]OUT DSP_EMIFA04 [12]OUT DSP_EMIFA05 [12]OUT DSP_EMIFA06 [12]OUT DSP_EMIFA07 [12]OUT DSP_EMIFA08 [12]OUT DSP_EMIFA09 [12]OUT DSP_EMIFA10 [12]OUT DSP_EMIFA11 [12]OUT DSP_EMIFA12 [12]OUT DSP_EMIFA13 [12]OUT DSP_EMIFA14 [12]OUT DSP_EMIFA15 [12]OUT DSP_EMIFA16 [12]OUT DSP_EMIFA17 [12]OUT DSP_EMIFA18 [12]OUT DSP_EMIFA19 [12]OUT DSP_EMIFA20 [12]OUT DSP_EMIFA21 [12]OUT DSP_EMIFA22 [12]OUT DSP_EMIFA23 [12]
OUT DSP_EMIFRNW [12]
OUT DSP_EMIFOEZ [12]OUT DSP_EMIFWEZ [12]
OUT DSP_EMIFCE1Z [12]OUT DSP_EMIFCE2Z [12]
OUTEXT_EMU_DET0[20]
OUTEMU_TMS[20]
OUT EMU_TRST# [20]
OUTTRGRSTZ[22]
OUTEMU_TDI[20]OUTDSP_TDO[20]
OUT EMU_TCK_BUF [20]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP EMIF & JTAG
C
16 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP EMIF & JTAG
C
16 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP EMIF & JTAG
C
16 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
R6749.9E1%
NU
R658 100E
R1119
4.7K
OR
U268SN74AUC1G32DCKR
B2
Y4
A1
VCC5
GND3
R293 10E
NAND1MT29F1G08ABCHC
NC7E6NC6E5NC5E4
IO0H4
IO1J4
IO2K4
IO3K5
NC4E3NC3D8NC2D7
VCC2H8
NC1D6
DU15M10
IO4K6
IO5J7
IO6K7
IO7J8
NC27F7
RED4
CEC6
NC25G4
VSS1C5
CLED5 ALEC4
WEC7 NC9
E8NC8E7
DU1A1
DU2A2
DU3A9
DU4A10
DU6B9
DU7B10
DU8L1
DU9L2
DU10L9
NC10F3
NC11F4
NC12F5
NC13F6
NC14F8
NC15G6
NC16G7
NC17G8
NC18G3
NC19H3
NC20H5
NC21H6
NC23J3
NC24J5
NC22H7
DU14M9
DU11L10
DU12M1
VCC1J6
NC28G5
DU13M2
NC26D3
VSS2K3
VSS3K8
DU5B1
R/BC8
WPC3
C1526100nF
TMS320C6657DSP1I
TRSTzAB19
TMSAE18
TDIAE17
TCKAD17
TDOAD19
EMU13AC25
EMU07Y23
EMU04W24
EMU00V24
EMU09Y22EMU08W22
EMU05Y25
EMU01V25
EMU10AA24
EMU06Y24
EMU02W25
EMU14AA23
EMU11AA25
EMU12AB25
EMU15AB22
EMU17AC24
EMU18Y21
EMU03W23
EMU16AD25
R268 10E
R2904.7K
R8964.7KNU
R294 10E
R282 10E
R1354.7K
R287 10E
R274 10E
C15288.2pF
C55547pFNU
R903
4.7K
R901
4.7K
C15810uF
R378 33E
A1B1
C1D1
PTH
PTH
EMU1BB_30x2V_S1.27mm
A1A2A3A4A5A6A7A8A9
A10A11A12A13A14A15
B1B2B3B4B5B6B7B8B9
B10B11B12B13B14B15
D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15
H1
H2
R269 10ER267 10E
TMS320C6657DSP1N
UPP_CH1_START/EMIFA21U1UPP_CH1_CLK/EMIFA20T5
UPP_CH1_ENABL/EMIFA22U2
UPP_CH0_CLK/EMIFA16R2
UPP_XD14/EMIFA14R3
UPP_XD15/EMIFA15R4
UPP_CH0_START/EMIFA17R1
UPP_XD13/EMIFA13R5
UPP_XD7/EMIFA07M1
UPP_CH0_ENABLE/EMIFA18T4
UPP_CH0_WAIT/EMIFA19T1
UPP_XD3/EMIFA03P5
EMIFBE1zL3
UPP_XD9/EMIFA09P3UPP_XD8/EMIFA08N2
UPP_XD10/EMIFA10N1
UPP_XD11/EMIFA11P2
UPP_XD12/EMIFA12P1
UPP_CH1_WAIT/EMIFA23U3
EMIFD13/UPP_D13AA1
EMIFD01/UPP_D1U5
EMIFD02/UPP_D2V1
EMIFD04/UPP_D4V3
EMIFD00/UPP_D0U4
EMIFD06/UPP_D6W1
EMIFD03/UPP_D3V2
EMIFD07/UPP_D7V5
EMIFD08/UPP_D8W2
EMIFD09/UPP_D9Y1
EMIFD10/UPP_D10W4
EMIFD11/UPP_D11Y2
EMIFD12/UPP_D12W5
EMIFD05/UPP_D5V4
EMIFD14/UPP_D14AB1
EMIFD15/UPP_D15AA2
EMIFCE2zJ2EMIFCE1zG1
EMIFOEzL4
EMIFCE3zM5
EMIFBE0zJ1
EMIFRnWL5
EMIFCE0zK5
UPP_XD2/EMIFA02L2
EMIFWEzK4
UPP_XD5/EMIFA05P4UPP_XD4/EMIFA04L1
EMIFWAIT0N5
EMIFWAIT1/UPP_2XTXCLKM4
UPP_XD0/EMIFA00K1
UPP_XD6/EMIFA06M2
UPP_XD1/EMIFA01M3 C159
100nF
R292 33E
R236 22E
R8974.7K
R281 10ER272 10E
R1831K
C519100nF
R1341K
R248 22E
R280 10E
R377 33E
R271 10E
R275 10E
OR
U269SN74AUC1G32DCKR
B2
Y4
A1
VCC5
GND3
R904 10KNU
C1527100nF
R249 22E
R288 10E
R276 10E
R266 10E
R295 10E
R273 10E
R9054.7K
R8934.7K
R902
4.7K
R270 10E
R279 10E
R8954.7K
R277 10ER278 10E
R1120
100E
R286 10E
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
JP-UART(1-3) & (2-4) : UART over USB Connector (Default)JP-UART(3-5) & (4-6) : UART over 3-Pin Header J5
I2C, TIMER[1:0], SPI
GPIO
Reset Control
Reserved
UART to RS232
32Mb SPI NOR Flash
Read Address: 1010 0001 (0x50), 1010 0011 (0x51)Write Address: 1010 0000 (0x50), 010 0010 (0x51)
1Mb I2C EEPROM
DIR = 0 --> B to ADIR = 1 --> A to B
DSP_SCLDSP_SDA
DSP_UARTRXD_V1P8
DSP_UART0_RXDSP_UART0_TX
DSP_HOUT
UART_MAX_TX UART_MAX_RX
UART_FT_TX UART_FT_RX
DSP_SSPCK
DSP_SSPMOSIDSP_SSPMISO
DSP_UARTRTS_V1P8DSP_UARTCTS_V1P8
DSP_GPIO_R_14
DSP_SSPCS0NOR_SSPCK
DSP_SSPMISODSP_SSPMOSI
DSP_BOOTCOMPLETEDSP_RESETSTAT#
DSP_SSPCK
NOR_SSPCKDSP_SSPCK
DSP_GPIO_09DSP_GPIO_10DSP_GPIO_11
DSP_GPIO_00
DSP_GPIO_12DSP_GPIO_13DSP_GPIO_R_14DSP_GPIO_R_15
DSP_GPIO_01DSP_GPIO_02DSP_GPIO_03DSP_GPIO_04DSP_GPIO_05DSP_GPIO_06DSP_GPIO_07DSP_GPIO_08
DSP_UARTTXD_V1P8
NOR_HD#DSP_SDA
UART_MAX_RX RS232_RX
UART_MAX_TX RS232_TX
DSP_SCL
DSP_PORZDSP_RESETFULLZDSP_RESETZ
DSP_LRESETNMIENZDSP_CORESEL0DSP_CORESEL1
DSP_NMIZDSP_LRESETZ
DSP_PORZDSP_RESETFULLZDSP_RESETZ
DSP_GPIO_R_15
DSP_LRESETNMIENZ
DSP_SSPCS0DSP_SSPCS1
DSP_UART0_RTSDSP_UART0_TX
DSP_UARTRXD_V1P8DSP_UARTCTS_V1P8
DSP_UARTTXD_V1P8DSP_UARTRTS_V1P8
DSP_UART0_CTSDSP_UART0_RX
VCC1V8
VCC1V8
VCC3V3_AUX VCC3V3_AUX
VCC1V8
VCC1V8
VCC1V8VCC1V8
VCC1V8
VCC1V8
VCC1V8
VCC1V8
VCC3V3_AUX
VCC1V8
BIDSP_SDA[11,12]
BIDSP_GPIO_00[23]BIDSP_GPIO_01[23]BIDSP_GPIO_02[23]BIDSP_GPIO_03[23]BIDSP_GPIO_04[23]BIDSP_GPIO_05[23]BIDSP_GPIO_06[23]BIDSP_GPIO_07[23]BIDSP_GPIO_08[23]BIDSP_GPIO_09[23]BIDSP_GPIO_10[23]BIDSP_GPIO_11[23]BIDSP_GPIO_12[23]BIDSP_GPIO_13[23]BIDSP_GPIO_14[12,23]BIDSP_GPIO_15[12,23]
IN UART_FT_RX [12,20]
IN DSP_SSPMISO [12,22]INDSP_TIMI0[12,23]INDSP_TIMI1[12,23]
IN EEPROM_WP [22]
INNOR_WP#[22]
INDSP_PORZ[22]INDSP_RESETFULLZ[22]INDSP_RESETZ[22]
INDSP_LRESETNMIENZ[22]INDSP_CORESEL0[22]INDSP_CORESEL1[22]
INDSP_LRESETZ[22]INDSP_NMIZ[22]
IN DSP_UART1_RX [12]
IN DSP_UART1_CTS [12]
OUTUART_FT_TX[12,20]
OUTDSP_SCL[11,12]
OUT DSP_HOUT [22]
OUT DSP_SSPCS1 [12,22]
OUT DSP_SSPMOSI [12,22]
OUT DSP_BOOTCOMPLETE [22]OUT DSP_RESETSTAT# [22]
OUTDSP_TIMO0[12,23]OUTDSP_TIMO1[12,23]
OUT FPGA_SSPCK [22]OUTPH_SSPCK[12]
OUT DSP_UART1_TX [12]
OUT DSP_UART1_RTS [12]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP MISC
C
17 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP MISC
C
17 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP MISC
C
17 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
U260N25Q032A11ESE40F
HOLD/DQ37 VCC8
S1
DQ12
W/Vpp/DQ23
VSS4
DQ05 SCK6
C5221uF
R349 0ENU
R357 0ENU
R459 4.7K
R202 33E
C472100nF
R467 4.7K
R1670E
R187
4.7K
R343 0ENU
U249MAX3221ECPWR
EN#1
C1+2
V+3
C1-4
C2+5
C2-6
V-7
RIN8
FORCEOFF#16 VCC
15
GND14
DOUT13
FORCEON12
DIN11
INVALID#10
ROUT9
R3294.7K
R1962
4.7K
R344 0ENU
R351 0ENU
R1650E
R340 10E
R460 4.7K
R2204
4.7K
R468 4.7K
R1603 0ENUR352 0ENU
R164
0E
NU
R1963
4.7K
R163
4.7K
C156 100nF
R1602 0ENU
R461 4.7K
COM_SEL1
TSM-103-01-S-DV
135
246
R358 0ENU
TP135
TMS320C6657DSP1S
RSV11H22
RSV12Y5
RSV13Y4
RSV01AA22
RSV02J3
RSV03H2
RSV04AC18
RSV05AB18
RSV06B23
RSV07A23
RSV08Y19
RSV09C23
RSV10G22
RSV14F21
RSV15G21
RSV16J20
RSV17AA7
RSV18AA11
RSV19AB3
R469 4.7K
R429
0E
NU
R341 10E
COM122-23-2031
123
C154 100nF
R369 33E
R1960
4.7K
R3844.7K
R342 0E
R354 0ENU
R337 10E
U255SN74ALVC125PWR
1OE1
1A2
1Y3
2OE4
2A5
2Y6
GND7
3Y83A93OE104Y114A124OE13VCC14
R462 4.7K
R359 0ENU
R347 10E
R953 10E
R470 4.7K
R355 0ENU
R166
4.7K
C303100nF
R200
4.7K
R1864.7K
EEPROM1AT24C1024BN-SH-T
NC1
A12
A23
GND4
VCC8
WP7
SCL6
SDA5
R463 4.7K
R952 10E
R428
0E
NU
R398 10E
R471 4.7K
B212200pF
1
2
3
TMS320C6657DSP1M
SCLAA17
SDAAA18
TIMI0/GPIO16AD20
TIMI1/GPIO17AE21
TIMO0/GPIO18AC19
TIMO1/GPIO19AE20
GPIO28/SPISCS0AA12
GPIO29/SPISCS1AA14
SPICLKAA13
GPIO30/SPIDINAB14
GPIO20/UARTRXDAB15
GPIO23/UARTRTSAB17
GPIO22/UARTCTSAC17
GPIO21/UARTTXDAA15
GPIO31/SPIDOUTAB13
GPIO27/UARTRTS1AD15
GPIO26/UARTCTS1AE16
GPIO25/UARTTXD1AC15
GPIO24/UARTRXD1AC14
R162
4.7K
C1368
100nF
R363 10E
TMS320C6657DSP1J
PORzY18
RESETFULLzJ4
RESETzH4
LRESETNMIENzF1
CORESEL0J5
CORESEL1G5
NMIzH1 LRESETzG4
RESETSTATzH5
BOOTCOMPLETEH3
HOUTG2
R427
0E
NU
C304100nF
R464 4.7K
R368 33E
R472 4.7K
R4000
4.7K
C1367100nF
R1961
4.7K
R1854.7K
R2960
4.7K
R1601 0ENU
R1964
4.7K
R180
4.7K
R3304.7K
C157 100nF
R345 0ENU
R455 4.7K
TP134
R465 4.7K
R964
4.7K
R1965
4.7K
R1227
4.7K
NU
C155 100nF
R346 0ENU
U24SN74AVC4T245PWR
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND18
GND29
2B210 2B111 1B212 1B113
2OE14 1OE15
VCCB16
R1604 0ENU
R356 0ENU
R458 4.7K
TMS320C6657DSP1L
GPIO00/LENDIANT25
GPIO13/BOOTMODE12V22
GPIO03/BOOTMODE02U25
GPIO04/BOOTMODE03T23
GPIO10/BOOTMODE09V23
GPIO08/BOOTMODE07U22
GPIO02/BOOTMODE01R23 GPIO01/BOOTMODE00R25
GPIO07/BOOTMODE06R21
GPIO12/BOOTMODE11T21
GPIO05/BOOTMODE04U24
GPIO09/BOOTMODE08U23
GPIO14/PCIESSMODE0W21
GPIO06/BOOTMODE05T22
GPIO15/PCIESSMODE1V21
GPIO11/BOOTMODE10U21
R466 4.7K
R188
4.7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
All blocking capacitors to be placed near DSP to keep connecting routes short and minimize vias
100.00MHz
250MHz
66.67MHz
100.00MHz
DSP CLOCK
SMART REFLEX
HIGH
SEL I/p PAIR SEL
LOW
PCI CLOCK MUX
250MHz
(HCSL)
(LVDS)
Reserved for future useNot supported at this time
DIR = 0 --> B to ADIR = 1 --> A to B
IN2/IN2#
IN1/IN1#
DSP_SYSCLKOUT
DSP_VIDADSP_VIDBDSP_VIDCDSP_VIDS
DSP_VD
DSP_PCIECLKPDSP_PCIECLKN
VID_OE#
DSP_VDDSP_VCL
DSP_VIDADSP_VIDBDSP_VIDCDSP_VIDS
PCI-E_P
PCI-E_N
DSP_PCIECLKP
CLK_MUX_SEL
PCIECLKP_R
PCIECLKP_R
PCIECLKN_R
DSP_PCIECLKNPCIECLKN_R
CLK_MUX_SEL
DSP_VCLVID_OE#
VCC1V8 VCC3V3_AUX
VCC1V8
VCC3V3_AUX
VCC1V8 VCC1V8VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUX_ICS557
VCC3V3_AUX_ICS557
VCC3V3_AUX_ICS557
VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUX
BI DSP_VD_3V3 [22]
INCORECLKP[19]INCORECLKN[19]
INSRIOSGMIICLKP[19]INSRIOSGMIICLKN[19]
INHyperLink_CLKP[19]INHyperLink_CLKN[19]
INDDRCLKP[19]INDDRCLKN[19]
INFPGA_VID_OE#[23]
IN PCA9306_EN [22]
INCLK_MUX_PD#[22]INCLK_MUX_OE[22]
INCLK_MUX_SEL[22]
INPCIE_REF_CLK_N[11]
INPCIE_REF_CLK_P[11]
INPCIECLKN[19]
INPCIECLKP[19]
OUT DSP_SYSCLKOUT [22]
OUT UCD9222_VIDA [26]OUT UCD9222_VIDB [26]OUT UCD9222_VIDC [26]OUT UCD9222_VIDS [26]
OUT DSP_VCL_3V3 [22]
INVCC1V8_PG[22,28]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP-CLOCK & SMART REFLEX
C
18 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP-CLOCK & SMART REFLEX
C
18 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP-CLOCK & SMART REFLEX
C
18 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
C502 100nF
R32610K
R2131 0E
R40 475E
C1226 100nF
C1810nF
R24 33E1%
C499 100nF
R453
10K
NU
R444 100E
R323
10K
C175100nF
TP12
R450 100E
C500 100nF
R47510K
U248PCA9306DCUR
VREF12
SCL13
SDA14
GND1
EN8VREF27
SDA25SCL26
C1225 100nF
R128
4.7K
R486
10K
C493 100nF
R425
150E
U1IDT5V41068APGGI
VDD_11
IN12
IN13
PD4
IN25
IN26
OE7
GND_18
IREF9
VDD_210
VDD_311
GND_212
GND_313
CLK14
CLK15
SEL16
C494 100nF
R426
150E
R39 33E1%
B22
2200pF
1
2
3
R436
10K
C174100nF
C520
100nF
U19SN74AVC4T245PWR
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND18
GND29
2B210 2B111 1B212 1B113
2OE14 1OE15
VCCB16
C495 100nF
R433
10K
R372 100E
C496 100nF
R129
4.7K
R434
1.2K
C52710uF
R32410K
R320
10K
C503 100nF
R32710K
R442
10K
R2130 0ENU
R130
4.7K
R321
10K
TMS320C6657DSP1G
VCNTL0E22
VCNTL1E23
VCNTL2F23
VCNTL3G23
VCLF22
VDD23
C504 100nF
C1610nF
R32510K
C501 100nF
G
S
DQ62N7002
1
32
R328100K
R131
4.7K
C42110uF
TMS320C6657DSP1H
CORECLKPAD18
CORECLKNAE19
DDRCLKPA22
DDRCLKNB22
SRIOSGMIICLKPAD13
SRIOSGMIICLKNAE14
PCIECLKPAD14
PCIECLKNAE15
MCMCLKNB25 MCMCLKPC25
SYSCLKOUTAA19
R322
10K
C1710nF
C521
100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLOCK GEN2
100.00MHz
50.00MHz
These caps should be locatednear CDCE62005(CLK2)
These caps should be locatednear CDCE62005(CLK2)
250.00MHz
250.00MHz
100.00MHz
REFCLK2_XTALIN
TCLKB_PTCLKB_N
VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUXVCCPLLA2A
VCC3V3_AUX VCC_VCO2A
VCCPLLA2A
VCC3V3_AUX VCC_VCO2B
VCC3V3_AUX
VCC_VCO2A
VCC3V3_AUX
VCCPLLA2B
VCC_VCO2B
VCCPLLA2C
VCCPLLA2B
VCCPLLA2CVCC3V3_AUX
VCC3V3_AUX
INREFCLK2_PD#[23]
INCLOCK2_SSPCK[23]INCLOCK2_SSPSI[23]
INCLOCK2_SSPCS1[23]
INTCLKB_P[11]INTCLKB_N[11]
OUT CLOCK2_PLL_LOCK [23]
OUT CORECLKP [18]OUT CORECLKN [18]
OUT DDRCLKP [18]OUT DDRCLKN [18]
OUTCLOCK2_SSPSO[23]
OUT TCLKB_P_R [22]OUT TCLKB_N_R [22]
OUT HyperLink_CLKP [18]OUT HyperLink_CLKN [18]
OUT SRIOSGMIICLKP [18]OUT SRIOSGMIICLKN [18]
OUT PCIECLKN [18]OUT PCIECLKP [18]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
CLOCK GENRATION
C
19 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
CLOCK GENRATION
C
19 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
CLOCK GENRATION
C
19 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
C309100nF
TP44
C320 1uF
C331100nF
TP36
C311100nF
R173
10K
C366 47pFNU
R170
10K
NU
CLK2
CDCE62005RGZT
AUXIN43AUXOUT13
EPAD49
EXT_LFN41 EXT_LFP40
GND_VCO36
PLL_LOCK37
Power_Down#12
PRIREF-46 PRIREF+45
REF_SEL31
REG_CAP14
REG_CAP238
SECREF-2 SECREF+3
SPI_CLK24 SPI_LE25
SPI_MISO22 SPI_MOSI23
SYNC14
TEST_MODE33
TESTOUTA30
U0N28U0P27
U1N20U1P19
U2N17U2P16
U3N10U3P9
U4N7U4P6
VB
B48
VC
C_A
UX
IN44
VC
C_A
UX
OU
T15
VC
C_I
N_P
RI
47
VC
C_I
N_S
EC
1
VC
C_O
UT
18
VC
C_O
UT
211
VC
C_O
UT
318
VC
C_O
UT
421
VC
C_O
UT
526
VC
C_O
UT
629
VC
C_O
UT
732
VC
C_V
CO
134
VC
C_V
CO
235
VC
C1_
PLL
15
VC
C1_
PLL
239
VC
C1_
PLL
342
C314100nF
B12
2200pF
1
2
3
Y57A-25.000MAAJ-T
B14
2200pF
12
3
C312100nF
B15
2200pF
1
2
3
R1721K
C313100nF
B13
2200pF
1
2
3
TP37
C3301uF
TP45
C315100nF
C604 100nF 10V NU
C605 100nF 10V
C3361uF
C333 1uF
C3241uF
C329100nF
C598 100nF 10V NU
C316100nF
C334 1uF
C335100nF
C323100nF
C310100nF
C3221uF
C606 100nF 10V
C319100nF
C318100nF
C321100nF
B11
2200pF
1
2
3
C317100nF
TP29
R36610K
C3321uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
90 OHM DIFF. IMPEDANCE CONTROL
USB, JTAG
Switch for JTAG emulationFT2232HL_RESET# = 0 --> AMCFT2232HL_RESET# = 1 --> Mini USB
Switch for JTAG emulationEXT_EMU_DET = 0 --> External / Mezzanine EmulatorEXT_EMU_DET = 1 --> On board emulation
OR GATE
FT2232HL_RESET#
GPIOL2
GPIOL3
GPIOL1
FT_EMU0
FT_EMU1
FT_TDKFT_TDIFT_TDOFT_TMS
VPHY
VPLL
1V8_TRST#
1V8_TDO
1V8_TCK1V8_TDI
1V8_TMS3V3_TMS
3V3_TDI3V3_TCK
3V3_TDO
3V3_TRST#
3V3_EMU_013V3_EMU_00
1V8_EMU_011V8_EMU_00
FT_TRST#
USB_DMUSB_DP
AMC_JTAG_TDIAMC_JTAG_TCK
AMC_JTAG_TMSAMC_JTAG_TDO
AMC_JTAG_RST#
FT_TRST#
FT_TDOFT_TMS
FT_TDI
FT_EMU0FT_EMU1
FT_TDK
3V3_TMS
3V3_TDI3V3_TCK
3V3_TDO
3V3_TRST#
3V3_EMU_013V3_EMU_00
FT2232HL_RESET#
1V8_TRST#
1V8_TDO
1V8_TCK
1V8_TMS
1V8_TDI
1V8_EMU_001V8_EMU_01
GND_USB
GND_USB
VCC5_VBUS
VCC5_VBUS
VCC3V3_AUXVCC3V3_AUX
VCC3V3_AUXVCC3V3_AUX
VCC3V3_AUX
VCC1V8_AUX
VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUX
VCC1V8
VCC1V8_AUX
VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUXVCC3V3_AUXVCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUXVCC3V3_AUX
IN UART_FT_TX [12,17]
INAMC_JTAG_RST#[11]
INAMC_JTAG_TDI[11]
INAMC_JTAG_TMS[11]
INAMC_JTAG_TCK[11]
OUT UART_FT_RX [12,17]
OUTAMC_JTAG_TDO[11]
BI DSP_EMU_00 [16]BI DSP_EMU_01 [16]
BIEMU_EMU_00[16]BIEMU_EMU_01[16]
INEMU_TCK_BUF[16]INEMU_TDI[16]
INEMU_TMS[16]INEMU_TRST#[16]
INEXT_EMU_DET0[16]
IN DSP_TDO [16]OUTEMU_TDO[16]OUT DSP_TDI [16]
OUT DSP_TMS [16]OUT DSP_TRST# [16]
OUT DSP_TCK [16]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
USB-JTAG
C
20 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
USB-JTAG
C
20 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
USB-JTAG
C
20 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
R2044.7K
R95 4.7K
U259TS3L301DGG
A02
A14
A28
A310
A415
A517
A621
A723
0B148
1B147
0B245
1B244
2B142
3B141
2B239
3B238
4B135
5B134
4B232
5B231
6B129
7B128
6B226
7B225
VDD[1]1
VDD[2]6
VDD[3]12
VDD[4]19
VDD[5]36
GND[1]3
GND[2]5
GND[3]7
GND[4]9
GND[5]11
GND[6]13
GND[7]16
GND[8]18
GND[9]20
GND[10]22
GND[11]27
GND[12]30
GND[13]33
GND[14]37
GND[15]40
GND[16]43
GND[17]46
NC14
SEL24
TP11
C126
10nF
D5PGB1010603
R2107
4.7K
R88 22E
C2226
100nF
R92 22E
TP10
C127
100nF
C161
100nF
R104 4.7K
C118
100nF
B6 120_100MHz
R102 2.2K
R984.7K
C132100nF
C119
100nF
AND
U266SN74LVC1G08DCKR
B2
Y4
A1
VCC5
GND3
R91 22E
C601
10uF
R101 22E
R94
12.1K
1%
U254TS3L301DGG
A02
A14
A28
A310
A415
A517
A621
A723
0B148
1B147
0B245
1B244
2B142
3B141
2B239
3B238
4B135
5B134
4B232
5B231
6B129
7B128
6B226
7B225
VDD[1]1
VDD[2]6
VDD[3]12
VDD[4]19
VDD[5]36
GND[1]3
GND[2]5
GND[3]7
GND[4]9
GND[5]11
GND[6]13
GND[7]16
GND[8]18
GND[9]20
GND[10]22
GND[11]27
GND[12]30
GND[13]33
GND[14]37
GND[15]40
GND[16]43
GND[17]46
NC14
SEL24
R93 22E
C2227
100nF
J5TSW-102-07-S-S
1 2
R908 4.7K
R96
4.7K
C116
100nF
U9FT2232HL
VC
CIO
120
VC
CIO
231
VC
CIO
342
VC
CIO
456
VCORE112
VCORE237
VCORE364V
RE
GIN
50
VREGOUT49
DM7
DP8
REF6
RESET14
OSCI2
OSCO3
EECS63
EECLK62
EEDATA61
TE
ST
13
GN
D1
1
GN
D1
5
GN
D1
11
GN
D1
15
GN
D1
25
GN
D1
35
GN
D1
47
GN
D1
51
TCK16
TDI17
TDO18
TMS19
GPIOL021
GPIOL122
GPIOL324
GPIOL223
GPIOH026
GPIOH127
GPIOH228
GPIOH329
GPIOH430
GPIOH532
GPIOH633
GPIOH734
BDBUS0/TXD38
BDBUS1/RXD39
BDBUS240
BDBUS341
BDBUS443
BDBUS544
BDBUS645
BDBUS746
BCBUS048
BCBUS152
BCBUS253
BCBUS354
BCBUS455
BCBUS557
BCBUS658
BCBUS759
PWREN60
SUSPEND36
VPLL9
VPHY4
AG
ND
10
C133
100nF
U11ASN74AHC00PWR
1
23
147
R9564.7K
B5120_100MHz
C124
100nF
D4PGB1010603
R909 4.7K
B4120_100MHz
U11DSN74AHC00PWR
12
1311
C396
10uF
C365
100nF
U10TXS0108EPWR
A11
VCCA2
A23
A34
A45
A56
A67
A78
A89
OE10
B120
VCCB19
B218
B317
B416
B515
B614
B713
B812
GND11
C117
100nF
R138 10K
OR
U267SN74LVC1G32DCKR
B2
Y4
A1
VCC5
GND3
R2108
4.7K
C122
100nF
USB154819-0519
VBUS1
D-2
D+3
GND_14
GND_25
PT
H1
6P
TH
27
U11BSN74AHC00PWR
4
56
C135 100nF
R1370E
R89 22E
C129 100nF
C121
100nF
U11CSN74AHC00PWR
9
108
R955
4.7K
C125
100nF
U12AT93C46DN-SH-T
CS1
SK2
DI3
DO4
GND5 ORG6 NC7 VCC8
R1106
4.7K
C115
10nF
C134
100nF
R2109
4.7K
R103
10K
R1910
4.7K
R97
4.7K
C120
100nF
C131 33pF
Y2
ABM3B-12.000MHZ-B2-T1
3
2
4
R100 22E
R2110
4.7K
R171
1K
C123
100nF
C130 33pF
J4
TSW-102-07-S-S
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
01
If both fiber (SGMII) and copper (1000BASE-X) cables areconnected, the preferred media will be selected based onvalue of register 16_2.11:10. If it is:
00: Link with 1st media to establish link01: Prefer fiber media10: Prefer copper media
01
00
10
00
Read Address: 1010 0001 (0x50)Write Address: 1010 0000 (0x50)
256 Bytes EEPROM
ETHERNET PHY
EEPROM[1]
CONFIG2
CONFIG3
SGMII_CLK
CONFIG4
SEL_TWSI
CONFIG5 MODE[1]
PIN BIT[1]
CONFIG0 PHYADR[1]
EEPROM[0]
PHYADR[4]
SEL_VTT
MODE[0]
BIT[0]
PHYADR[0]
Pin to Configuration Bit Mapping
STATUS[1]
VSS
01
00
PIN VALUE
VDD0 11
01
CONFIG2
CONFIG3
01
CONFIG4
00
CONFIG5 10
PIN VALUE
CONFIG0 00
STATUS[1]
STATUS[1]
VSS
STATUS[0]
CONNECTION
VSS
SGMII_CLK not supplied; PHY Address[4] is 1
Start reading from address 0
PHY Address[1:0] is 00
MDC/MDIO mode; S_VTT & F_VTT int supplied
SGMII MAC Int to Auto Media select (Cu/SGMII)
INTERPRETATION
STATUS[0]10CONFIG1
CONFIG1 PHYADR[3] PHYADR[2] STATUS[0] 10
PHY Address[3:2] is 10
10
POL_RST RESET=0 RESET=1
1 or Floating ResetNormal
FOR EMI
ETHERNET JACK
0 Reset Normal
LED (Colour) 1Gbps
Activity No Activity
100Mbps
Activity No Activity
10Mbps
Activity No Activity
Status 0 (Green)
Status 1 (Orange) OFF OFF
OFF OFFBLINK
BLINK BLINK
BLINK SOLID ON
SOLID ON SOLID ON
SOLID ON
LED (Colour) Link
ON OFFLOS (Orange/Green)
No Link
ETH_CONFIG4
MDI3_N
MDI0_P
STATUS_1STATUS_0
ETH_LOS/LED
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
ETH_CONFIG1ETH_CONFIG2ETH_CONFIG3ETH_CONFIG4
ETH_CONFIG0
ETH_CONFIG5
DSP_SGMII_TXN_CDSP_SGMII_TXP_CDSP_SGMII_RXNDSP_SGMII_RXP
STATUS_0STATUS_1
AMC_SGMII_RXN_CAMC_SGMII_RXP_CAMC_SGMII_TXNAMC_SGMII_TXP
MDI0_NMDI0_PMDI1_NMDI1_PMDI2_NMDI2_PMDI3_NMDI3_P
ETH_LOS/LED
ETH_SDAETH_SCL
ETH_CONFIG3
ETH_CONFIG5
ETH_CONFIG1
ETH_CONFIG2
ETH_CONFIG0
LAN_RST
ETH_SDAETH_SCL
ETH_WP
STATUS_1
STATUS_0
LAN_RST
GND_LAN
GND_LAN
VCC2V5
VCC2V5VCC2V5
VCC2V5
P1_TCT
P1_TCT
P1_TCT
VCC2V5
P1_TCT
P1_TCT
VCC2V5
VCC2V5
VCC1V2
VCC1V2
VCC2V5 AVCC2V5
VCC2V5AVCC2V5
VCC2V5
VCC2V5
VCC2V5
BIETH_MDIO[13] IN DSP_SGMII_TXN [13]IN DSP_SGMII_TXP [13]
IN AMC_SGMII_RXN [11]IN AMC_SGMII_RXP [11]
INETH_MDC[13]
OUT DSP_SGMII_RXP [13]OUT DSP_SGMII_RXN [13]
OUT AMC_SGMII_TXP [11]OUT AMC_SGMII_TXN [11]
OUTPHY_INT#[23]
INPHY_RST[23]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
GIGABIT ETHERNET
C
21 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
GIGABIT ETHERNET
C
21 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
GIGABIT ETHERNET
C
21 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
C24 470pF
NU
R2226
10K
B7120_100MHz
R34
49.9ETP23
U26424LC02B-I/ST
A01
A12
A23
VSS4
SDA5SCL6
WP7
VCC8 PHY1
88E1112
SOUT_N1
SOUT_P2
S_V
TT
3
SCLK_N4
SCLK_P5
VD
DA
L_1
6
VD
DA
H_1
7
SIN_N8
SIN_P9
FOUT_N10
FOUT_P11
F_V
TT
12
VD
DA
L_2
13
VD
DA
H_2
14
FIN_N15
FIN_P16
NC
32
MDI[3]_N31
MDI[3]_P30
VD
DA
_429
MDI[2]_N28
MDI[2]_P27
HSDAC_N26
HSDAC_P25
VD
DA
_324
VD
DA
_223
MDI[1]_N22
MDI[1]_P21
VD
DA
_120
MDI[0]_N19
MDI[0]_P18
RS
ET
17
NORMAL49
PWRDN50
PO
L_R
ST
51
RESET52
SDA53 SCL54
VS
S_1
55
VD
DO
_256
MDC57
MDIO58
LOS59
SDET60
INIT61
DV
DD
_462
VS
S_2
63
DV
DD
_564
CONFIG[2]45
CONFIG[3]44
DV
DD
_243
CONFIG[4]42
CONFIG[5]41
DV
DD
_139
VD
DO
_137
XTAL136
XTAL235 TSTPT
34
VD
DA
_533
CONFIG[0]48
DV
DD
_347
CONFIG[1]46
ePA
D65
STATUS[0]40
STATUS[1]38
B3120_100MHz
C1372100nF
C136 100nF
R431
1M1% NU
C144
100nF
TP133
C1146
100nF
C29100nF
R35 100E
C30100nF
C143
10nF
R146
10K
R764
10K
C145
4.7uF
R1657
4.7K
C151
10nF
Y3
ABM3B-25.000MHZ-B2-T
13
2
4R1273
4.7K
R776 0E
R391 4.99K
C22100nF
C23 33pF
C152
100nF
R147 4.99K
1%
C1147
100nF
C21100nF
C25 33pF
R774 0E
R27
49.9E
B37120_100MHz
C1149
10nF
R779 0E
R1656
4.7K
R36 100E
R1658 4.7K
C50100nF
R777 0E
C62100nF
C353 100nF
C150
4.7uF
R778 0E
R1130 100E
R32
49.9E
C57100nF
C149
100nF
C1148
10nF
R775 0E
C1370 100nF
R26
49.9E
VCC
GND
U252SN74LVC1G07DBVR
123 4
5
C148
10nFC58100nF
C141
100nF
R392 4.99K
R28
49.9E
TP162
R33
49.9E
R99
10K
C61100nF
O/G
SHIELD GND
1000pF 2kV
75RO
4
7
6
2
8
3
1
5
TX1-
TX2-
TX2+
TX1+
TX3+
TX3-
TX4+
TX4-
G
LAN1
J0G-0001NL or J0G-0003NL
14
13
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17 H3H4
H1H2
R2203
10KNU
C142
4.7uF
R765
10K
R31
49.9E
C137 100nF
C140
10nF
R29
49.9E
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DSP
C6657
C6657 SPI
High active
DSP McBSPCLK & FS
NOR Flash
60 Pin Header
EEPROM
Power Sequence
Reset Switch
UCD9222
AMC TCLK
VCL/VDA Enable
MMC
FPGA - POWER & RST CTRL, McBSP FPGA - POWER, JTAG
PUDC (User I/O Pull-Up Control)If its value during configuration is:
0: enable PUs in all I/O pins to resp VCCO1: No pull-ups
Place near FPGA
Must be High During Configuration to allow configuration to start
Cold_RESET WARM_RESET FULL_RESET
DSP McBSPSCLK
Reserved for future use
FPGA_PUDC
SYS_PGOOD
FPGA_PUDC
Cold_RESETSW1-P1 WARM_RESETSW7-P1
WARM_RESETCold_RESET
DSP_VCL_FPGADSP_VD_FPGA
FULL_RESETSW8-P1
FULL_RESET
SYS_PGOOD
TCLKD_P TCLKD_NTCLKC_P TCLKC_N
TCLKB_N_RTCLKA_N
TCLKB_P_RTCLKA_P
DSP_PORZDSP_RESETFULLZDSP_RESETZ
PMBUS_CLKPMBUS_DAT
DSP_VD_FPGADSP_VCL_FPGA
FPGA_JTAG_RST#
FPGA_PROG
FPGA_JTAG_TMSFPGA_JTAG_TDO
FPGA_JTAG_TCK
FPGA_DONE
FPGA_PROG
FPGA_DONE
FPGA_JTAG_TDOFPGA_JTAG_TDI
FPGA_JTAG_TMSFPGA_JTAG_RST#
FPGA_JTAG_TCK
FPGA_JTAG_TDI
VCC3V3_FPGA VCC3V3_FPGA VCC3V3_FPGA
VCC3V3_FPGA
VCC1V8_AUX
VCC3V3_FPGA
VCC1V8_AUXVCC1V8_AUX
VCC3V3_FPGA
VCC1V2_FPGA
VCC3V3_FPGA
VCC3V3_FPGA
VCC3V3_AUX
VCC3V3_FPGA
VCC1V2_FPGAVCC1V2 VCC3V3_FPGAVCC3V3_AUX
BIPMBUS_DAT[26]
BI DSP_VD_3V3 [18]
INTCLKA_P[11]INTCLKA_N[11]
INTCLKC_N[11]INTCLKC_P[11]
INTCLKB_N_R[19]INTCLKB_P_R[19]
INTCLKD_N[11]INTCLKD_P[11]
IN DSP_SSPCS1 [12,17]IN FPGA_SSPCK [17]
IN DSP_SSPMOSI [12,17]
IN DSP_HOUT [17]
IN DSP_SYSCLKOUT [18]
INVCC5_PG[27]
IN DSP_BOOTCOMPLETE[17]
IN DSP_RESETSTAT# [17]IN TRGRSTZ [16]
INPGUCD9222[26]
INPMBUS_ALT[26]
IN DSP_VCL_3V3 [18]
INVCC2V5_PG[28]INVCC3V3_AUX_PG[27]INVCC0V75_PG[28]INVCC1V5_PG[27]
INUCD9222_PG2[26]
INUCD9222_PG1[26]
INMMC_WR_AMC#[12]INMMC_POR_AMC#[12]
INMMC_DETECT#[12]
OUT DSP_LRESETNMIENZ [17]OUT DSP_CORESEL0 [17]OUT DSP_CORESEL1 [17]
OUT DSP_NMIZ [17]OUT DSP_LRESETZ [17]
OUT DSP_SSPMISO [12,17]
OUT XDS560_IL [27]
OUT DSP_RESETZ [17]
OUT DSP_PORZ [17]OUT DSP_RESETFULLZ [17]
OUT NAND_WP# [16]
OUT EEPROM_WP [17]OUT NOR_WP# [17]
OUTCLK_MUX_PD#[18]
OUTFPGA_DONE[23]
OUT McBSP_AMC_EN# [11]
OUTVCC1V5_EN[27]
OUTUCD9222_RST#[26]
OUTCLK_MUX_OE[18]OUTVCC1V8_EN1[28]OUTVCC0V75_EN[28]OUTVCC2V5_EN[28]OUTVCC_5V_EN[27]
OUTUCD9222_ENA2[26]
OUTUCD9222_ENA1[26]
OUTPMBUS_CLK[26]
OUTPMBUS_CTL[26]
OUTCLK_MUX_SEL[18]
OUTPCA9306_EN[18]OUTMMC_BOOTCOMP[12]
OUTMMC_RSTSTAT#[12]
OUT DSP_McBSP0_TXCLK [12,13]OUT DSP_McBSP0_RXCLK [12,13]OUT DSP_McBSP1_TXCLK [12,13]OUT DSP_McBSP1_RXCLK [12,13]
OUT DSP_McBSP1_FST [12,13]OUT DSP_McBSP1_FSR [12,13]
OUT DSP_McBSP0_FST [12,13]OUT DSP_McBSP0_FSR [12,13]
OUT DSP_McBSP0_SLCLK [12,13]OUT DSP_McBSP1_SLCLK [12,13]
IN VCC1V8_PG [18,28]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
FPGA-POWER,RESET,McBSP
C
22 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
FPGA-POWER,RESET,McBSP
C
22 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
FPGA-POWER,RESET,McBSP
C
22 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
TP15
R79 1K
C417
100nF
C534
100nF
R140 100E
R424
4.7K
R182
10K
NU
R154 0E
R478 0E
R218
4.7K
TP13
R1379 0E
R1173 33E
R5
10K
C391
100nF
C1310nF
R414
4.7K
C533100nF
C476
100nF
R8 100E
R153 0E
R184
330E
R482 0E
R1175 33E
C418
100nF
C416
100nF
R318 100E
R965 22E
RST_COLD1
EVQ-PF003M
AB
G1G2
R217
1K
R319 100E
R1174 33E
R1185 33E
R317 100E
RST_WARM1
EVQ-PF003M
AB
G1G2
R394 0ENU
R139
10K
R413
4.7K
C412
100nF
R480 0E
C475
100nF
C384100nF
R1176 33E
B26 120_100MHz
R156 0E
TP16
B
SYSPG_D1
YEL
12
R409 0ENU
R481 0E
R966 22E
C535
100nF
R370
4.7K
C415
100nF
R1187 33E
C386
100nF
B33 120_100MHz
R479 0E
TP14
B34 120_100MHz
C599100nF
R967 22E
C1110nF
C394
100nF
C15
100nF
R155 0E
R74
10K
C414
100nF
C385
10uF
R181
10K
RST_FULL1
EVQ-PF003M
AB
G1G2
R400 10E
R371
1K
NU
FPGA1C
XC3S200AN-4FTG256C
DONET15
PROGA2
TCKA15
TDIB1
TDOB16
TMSB2
VCCAUX_1E11
VCCAUX_2F5
VCCAUX_3L12
VCCAUX_4M6
VCCINT_1G7
VCCINT_2G9
VCCINT_3H8
VCCINT_4J9
VCCINT_5K8
VCCINT_6K10
GND_1A1
GND_2A16
GND_3B7
GND_4B11
GND_5C3
GND_6C14
GND_7E5
GND_8E12
GND_9F2
GND_10F6
GND_11G8
GND_12G10
GND_13G15
GND_14H9
GND_15J8
GND_16K2
GND_17K7
GND_18K9
GND_19L11
GND_20L15
GND_21M5
GND_22M12
GND_23P3
GND_24P14
GND_25R6
GND_26R10
GND_27T1
GND_28T16
R477 0E
R68 100E
R219
330E
NU
C392
10uF
C600100nF
C546100nF
C383100nF
R81 1K
C413
100nF
R3154.7K
R220
100K
NU
C910nF
R410 0ENU
C393
100nF
C400
100nF
C532100nF
G
D11
GRN
NU
12
R80 1K
R159 0E
R228 100E
C425
100nF
C531100nF
B25 120_100MHz
R474 0E
R395 0ENU
C419
100nF
TAP_FPGA1TSW-108-07-S-S
12345
76
8
R84 1K
Bank0Bank1
FPGA1A
XC3S200AN-4FTG256C
IO_L01N_0C13
IO_L01P_0D13
IO_L02N_0B14
IO_L02P_0/VREF_0_1B15
IO_L03N_0D11
IO_L03P_0C12
IO_L04N_0A13
IO_L04P_0A14
IO_L05N_0A12
IO_L05P_0B12
IO_L06N_0/VREF_0_2E10
IO_L06P_0D10
IO_L07N_0A11
IO_L07P_0C11
IO_L08N_0A10
IO_L08P_0B10
IO_L09N_0/GCLK5D9
IO_L09P_0/GCLK4C10
IO_L10N_0/GCLK7A9
IO_L10P_0/GCLK6C9
IO_L11N_0/GCLK9D8
IO_L11P_0/GCLK8C8
IO_L12N_0/GCLK11B8
IO_L12P_0/GCLK10A8
IO_L13N_0C7
IO_L13P_0A7
IO_L14N_0/VREF_0_3E7
IO_L14P_0F8
IO_L15N_0B6
IO_L15P_0A6
IO_L16N_0C6
IO_L16P_0D7
IO_L17N_0C5
IO_L17P_0A5
IO_L18N_0B4
IO_L18P_0A4
IO_L19N_0B3
IO_L19P_0A3
IO_L20N_0/PUDCD5
IO_L20P_0/VREF_0_4C4
IP_0_1D6
IP_0_2D12
IP_0_3E6
IP_0_4F7
IP_0_5F9
IP_0_6F10
IP_0_7/VREF_0_5E9
VCCO_0_1B5
VCCO_0_2B9
VCCO_0_3B13
VCCO_0_4E8
IO_L01N_1/LDC2N14
IO_L01P_1/HDCN13
IO_L02N_1/LDC0P15
IO_L02P_1/LDC1R15
IO_L03N_1/A1N16
IO_L03P_1/A0P16
IO_L05N_1/VREF_1_1M14
IO_L05P_1M13
IO_L06N_1/A3K13
IO_L06P_1/A2L13
IO_L07N_1/A5M16
IO_L07P_1/A4M15
IO_L08N_1/A7L16
IO_L08P_1/A6L14
IO_L10N_1/A9J13
IO_L10P_1/A8J12
IO_L11N_1/RHCLK1K14
IO_L11P_1/RHCLK0K15
IO_L12N_1/TRDY1/RHCLK3J16
IO_L12P_1/RHCLK2K16
IO_L14N_1/RHCLK5H14
IO_L14P_1/RHCLK4J14
IO_L15N_1/RHCLK7H16
IO_L15P_1/IRDY1/RHCLK6H15
IO_L16N_1/A11F16
IO_L16P_1/A10G16
IO_L17N_1/A13G14
IO_L17P_1/A12H13
IO_L18N_1/A15F15
IO_L18P_1/A14E16
IO_L19N_1/A17F14
IO_L19P_1/A16G13
IO_L20N_1/A19F13
IO_L20P_1/A18E14
IO_L22N_1/A21D15
IO_L22P_1/A20D16
IO_L23N_1/A23D14
IO_L23P_1/A22E13
IO_L24N_1/A25C15
IO_L24P_1/A24C16
IP_L04N_1/VREF_1_2K12
IP_L04P_1K11
IP_L09N_1J11
IP_L09P_1/VREF_1_3J10
IP_L13N_1H11
IP_L13P_1H10
IP_L21N_1G11
IP_L21P_1/VREF_1_4G12
IP_L25N_1F11
IP_L25P_1/VREF_1_5F12
SUSPENDR16
VCCO_1_1E15
VCCO_1_2H12
VCCO_1_3J15
VCCO_1_4N15
R201
10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Boot Device
Sleep/EMIF16
Boot PLL Settings
BM_GPIO
0 0 0 0
VID Enable
PHY 88E1112
CLOCK GEN
MMC SPI
UCD9222 VID CTRL
FPGA EEPROM
BOOT MODESWITCH
DSP GPIOTO FPGA
For FPGA internal reset.
DEBUG_LED
Reserved for future use
FPGA, BOOT MODE & SMART REFLEX
SRIO0 0 0 1
X 0 1 0 Ethernet
0 0 1 1 NAND
0 1 0 0 PCIe
I2C MasterX 1 0 1
0 1 0 1 I2C Slave
X 1 1 0 SPI
0 1 1 1 Hyperlink
1 0 0 0 UART
[4:1]Boot DeviceBM_GPIO
50.00
BM_GPIO
0 0 0
66.670 0 1
0 1 0 80.00
0 1 1 100.00
156.251 0 0
1 0 1 250.00
1 1 0 312.50
1 1 1 122.88
[13:11]BM_GPIO [13:11]
Input Clock(in MHz) (in MHz)
Input Clock
Boot Device
PCIESSEN
PCIe module disabled
BM_GPIO16
0
PCIe module enabled1
PCIe Status
PCIe Mode Selection PCIESSMODE[1:0]
End-point mode
BM_GPIO
0 0
Legacy End-point mode (support for legacy INTx)0 1
1 0 Root complex mode
1 1 Reserved
[15:14]PCIe Mode
GPIO0
DIP Switch
BM_GPIO00 - Big Endian1 - Little EndianENDIANESS
BM_GPIO
Boot Configuration
GPIO[4:1]BM_GPIO[4:1] Boot DeviceBOOTMODE[3:0]
GPIO[10:5] Boot Device ConfigBOOTMODE[9:4]BM_GPIO[10:5]
PLL Multiplier/I2CGPIO[13:11]BM_GPIO[13:11]
Endpt/RootComplexPCIESSMODE[1:0]GPIO[15:14]BM_GPIO[15:14]
DSP Primary Function
[4:1]
Note: GPIO[10:5] bit definitions depend on the bootmode.
BOOT STRAP CONFIGURATION
BOOTMODE[12:10]
FPGA_M1
PCIESSEN
FPGA_INIT#
FPGA_M2
FPGA_SPI_CS#FPGA_SPI_SI
FPGA_SPI_SO
DEBUG_LED_1DEBUG_LED_0
FPGA_INIT#
BM_GPIO_00BM_GPIO_01BM_GPIO_02BM_GPIO_03
FPGA_M2
DEBUG_LED_3
BM_GPIO_05
BM_GPIO_14BM_GPIO_13
BM_GPIO_08BM_GPIO_07BM_GPIO_06
BM_GPIO_00
BM_GPIO_12BM_GPIO_11BM_GPIO_10BM_GPIO_09
BM_GPIO_15
BM_GPIO_04BM_GPIO_03BM_GPIO_02BM_GPIO_01
PCIESSEN
FPGA_VS1
MAIN_48MHZ_CLK_R
FPGA_SPI_CS#
FPGA_SPI_SIFPGA_SPI_WP#FPGA_SPI_SO
FPGA_SPI_SCKFPGA_SPI_HD#
FPGA_VS0
DEBUG_LED_2
DEBUG_LED_0
FPGA_VS2
BM_GPIO_12BM_GPIO_13BM_GPIO_14BM_GPIO_15
User_define
FPGA_SPI_SCK
MAIN_48MHZ_CLK_R
BM_GPIO_04BM_GPIO_05BM_GPIO_06BM_GPIO_07
FPGA_M0
FPGA_M0
DEBUG_LED_1
User_define
BM_GPIO_08BM_GPIO_09BM_GPIO_10BM_GPIO_11
FPGA_M1
DEBUG_LED_2DEBUG_LED_3
VCC3V3_FPGA VCC3V3_FPGA VCC3V3_FPGA
VCC1V8_AUX
VCC1V8_AUX
VCC3V3_FPGA
VCC3V3_FPGA
VCC3V3_FPGA
VCC3V3_FPGAVCC3V3_FPGA
VCC3V3_AUX
BIDSP_GPIO_00[17]BIDSP_GPIO_01[17]BIDSP_GPIO_02[17]BIDSP_GPIO_03[17]BIDSP_GPIO_04[17]BIDSP_GPIO_05[17]BIDSP_GPIO_06[17]BIDSP_GPIO_07[17]BIDSP_GPIO_08[17]BIDSP_GPIO_09[17]BIDSP_GPIO_10[17]BIDSP_GPIO_11[17]BIDSP_GPIO_12[17]BIDSP_GPIO_13[17]BIDSP_GPIO_14[12,17]BIDSP_GPIO_15[12,17]
IN CLOCK2_SSPSO [19]
IN MMC_SPI_MISO [12]
IN FPGA_DONE [22]
INDSP_TIMO0[12,17]INDSP_TIMO1[12,17]
IN PHY_INT# [21]
IN CLOCK2_PLL_LOCK [19]
OUT CLOCK2_SSPCK [19]OUT CLOCK2_SSPSI [19]
OUT CLOCK2_SSPCS1 [19]
OUT REFCLK2_PD# [19]
OUT MMC_SPI_SCK [12]OUT MMC_SPI_STE [12]
OUT MMC_SPI_MOSI [12]OUT UCD9222_VID2A [26]OUT UCD9222_VID2B [26]OUT UCD9222_VID2C [26]
OUTDSP_TIMI0[12,17]
OUT FPGA_VID_OE# [18]
OUTDSP_TIMI1[12,17]
OUT PHY_RST [21]
OUT UCD9222_VID2S [26]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
FPGA & BM & SMART REFLEX
C
23 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
FPGA & BM & SMART REFLEX
C
23 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
FPGA & BM & SMART REFLEX
C
23 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
R296 10K
R312 10K
R289 100E
R313 100E
R407 10K
R213 10K
R208 330E
R298 10KR309 10K R310 100E
R192
330E
R265 10K
R473 10E
R193
330E
NU
R1894.7K
Bank2Bank3
FPGA1BXC3S200AN-4FTG256C
IO_L01N_2/M0P4
IO_L01P_2/M1N4
IO_L02N_2/CSOT2
IO_L02P_2/M2R2
IO_L03N_2/VS2T3
IO_L03P_2/RDWRR3
IO_L04N_2/VS0P5
IO_L04P_2/VS1N6
IO_L05N_2R5
IO_L05P_2T4
IO_L06N_2/D6T6
IO_L06P_2/D7T5
IO_L07N_2P6
IO_L07P_2N7
IO_L08N_2/D4N8
IO_L08P_2/D5P7
IO_L09N_2/GCLK13T7
IO_L09P_2/GCLK12R7
IO_L10N_2/GCLK15T8
IO_L10P_2/GCLK14P8
IO_L11N_2/GCLK1P9
IO_L11P_2/GCLK0N9
IO_L12N_2/GCLK3T9
IO_L12P_2/GCLK2R9
IO_L13N_2M10
IO_L13P_2N10
IO_L14N_2/MOSI/CSIP10
IO_L14P_2T10
IO_L15N_2/DOUTR11
IO_L15P_2/AWAKET11
IO_L16N_2N11
IO_L16P_2P11
IO_L17N_2/D3P12
IO_L17P_2/INITT12
IO_L18N_2/D1R13
IO_L18P_2/D2T13
IO_L19N_2P13
IO_L19P_2N12
IO_L20N_2/CCLKR14
IO_L20P_2/D0/DIN/MISOT14
IP_2_1L7
IP_2_2L8
IP_2_3/VREF_2_1L9
IP_2_4/VREF_2_2L10
IP_2_5/VREF_2_3M7
IP_2_6/VREF_2_4M8
IP_2_7/VREF_2_5M11
IP_2_8/VREF_2_6N5
VCCO_2_1M9
VCCO_2_2R4
VCCO_2_3R8
VCCO_2_4R12
IO_L01N_3C1
IO_L01P_3C2
IO_L02N_3D3
IO_L02P_3D4
IO_L03N_3E1
IO_L03P_3D1
IO_L05N_3E2
IO_L05P_3E3
IO_L07N_3G4
IO_L07P_3F3
IO_L08N_3/VREF_3_1G1
IO_L08P_3F1
IO_L09N_3H4
IO_L09P_3G3
IO_L10N_3H5
IO_L10P_3H6
IO_L11N_3/LHCLK1H1
IO_L11P_3/LHCLK0G2
IO_L12N_3/IRDY2/LHCLK3J3
IO_L12P_3/LHCLK2H3
IO_L14N_3/LHCLK5J1
IO_L14P_3/LHCLK4J2
IO_L15N_3/LHCLK7K1
IO_L15P_3/TRDY2/LHCLK6K3
IO_L16N_3L2
IO_L16P_3/VREF_3_2L1
IO_L17N_3J6
IO_L17P_3J4
IO_L18N_3L3
IO_L18P_3K4
IO_L19N_3L4
IO_L19P_3M3
IO_L20N_3N1
IO_L20P_3M1
IO_L22N_3P1
IO_L22P_3N2
IO_L23N_3P2
IO_L23P_3R1
IO_L24N_3M4
IO_L24P_3N3
IP_L04N_3/VREF_3_3F4
IP_L04P_3E4
IP_L06N_3/VREF_3_4G5
IP_L06P_3G6
IP_L13N_3J7
IP_L13P_3H7
IP_L21N_3K6
IP_L21P_3K5
IP_L25N_3/VREF_3_5L6
IP_L25P_3L5
VCCO_3_1D2
VCCO_3_2H2
VCCO_3_3J5
VCCO_3_4M2
R308 10K
R199
0E
R299 10K
R198
0E
NU
R264 10K
R303 100E
C439100nF
ONSW9
SDA02H1SBD
12
43
R211 100E
C387100nF
R397 10E
Y7
ASFL1-48.000MHZ-EC-T
VCC4
OUT3
GND2
OE1
R302 100E
C440100nF
C435100nF
R215 10K
R396 10E
R924
0E
NU
R205 330E
R1904.7K
R403 100E
R194
4.7K
R195
4.7K
C436100nF
R285 100E
R196
4.7KR304 10K
R301 10K
R197
0E
NU
R210 10K
R402 100E
R923
1K
R423 10K
R422 10K
ON
SW5SDA08H1SBD
12345678
109
161514131211
R207 330E
B
FPGA_D1 GRN1 2
B36120_100MHz
R206 330E
R216 100E
R212 100E
C530100nF
ON
SW3SDA08H1SBD
12345678
109
161514131211
C390100nF
B
FPGA_D2 GRN1 2
B
FPGA_D4 GRN1 2
R306 10K
R305 100E
C388100nF
R178 33E
R214 100E
R421 10K
R209 10K
B24
120_100MHz
B
FPGA_D3 GRN1 2
C389100nF
R297 100E
R408 10K
R307 100E
R283 100E
U26
AT25128B-SSHL-B
CS1
SO2
WP3
GND4
SI5SCK6HOLD7VCC8
R311 100E
B35120_100MHz
C382
100nF
R284 10K
R191
330E
R300 100E
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.8V
1.5V
0.9V - 1.1V (SMART REFLEX) Place near to DSP
Place near to DSP
Place near to DSP
VCC1V8_AVDD2
VCC1V8_AVDD1
CVDDCVDD
VCC1V8VCC1V8
VCC1V8
VCC1V5VCC1V5
VCC1V5VCC1V5
VCC1V8
VCC1V5 VCC1V5
VCC1V8
CVDD
CVDD
CVDD
CVDD
VCC1V8
VCC1V8VCC1V8
VCC1V5
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP POWER 1
C
24 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP POWER 1
C
24 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP POWER 1
C
24 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
TMS320C6657DSP1D
DVDD18_1A24
DVDD18_2E21
DVDD18_3G3
DVDD18_4G6
DVDD18_5H7
DVDD18_6H19
DVDD18_7H24
DVDD18_8J6
DVDD18_9K3
DVDD18_10K7
RSV0AG19
RSV0BG20
AVDDA1Y15
AVDDA2F20
DVDD18_11L6
DVDD18_12M7
DVDD18_13N3
DVDD18_14N6
DVDD18_15P7
DVDD18_16R6
DVDD18_17R20
DVDD18_18T3
DVDD18_19T7
DVDD18_20T19
DVDD18_21T24
DVDD18_22U6
DVDD18_23U20
DVDD18_24V7
DVDD18_25V19
DVDD18_26W6
DVDD18_27W14
DVDD18_28W16
DVDD18_29W18
DVDD18_30W20
DVDD18_31Y3
DVDD18_32Y13
DVDD18_33Y17
DVDD18_34AB23
DVDD18_35AC16
DVDD18_36AC20
C1262
100nF
C1216
100nF
C1208
560pF
C1186
560pF
C1707
100nF
C1204
560pF
C1241
560pF
C1200
100uF
C1261
100nF
C1221
10nF
C1248
10nF
C1253
10nF
C1704
100nF
B132
2200pF
1
2
3
C1233
560pF
R364 0ENU
C1235
560pF
C1192
560pF
C1712
10nF
C1199
1000pF
C1217
100nF
C1185
100nF
C1270
100nF
C1228
560pF
C1191
560pF
C1240
560pF
C1274
100nF
C1256
10nF
C1213
1000pF
C1258
100nF
TMS320C6657DSP1A
CVDD_1H9
CVDD_2H11
CVDD_3H13
CVDD_4H15
CVDD_5H17
CVDD_6J10
CVDD_7J12
CVDD_8J14
CVDD_9J16
CVDD_10K11
CVDD_11K13
CVDD_12K15
CVDD_14L10
CVDD_15L12
CVDD_17L16
CVDD_18L18
CVDD_22M15
CVDD_23M17
CVDD_24N8
CVDD_25N10
CVDD_26N12
CVDD_27N14
CVDD_28N16
CVDD_29N18
CVDD_30P9
CVDD_31P11
CVDD_32P13
CVDD_33P15
CVDD_34P17
CVDD_35P19
CVDD_36R10
CVDD_40R18
CVDD_41T11
CVDD_42T13
CVDD_43T15
CVDD_44U10
CVDD_46U14
CVDD_47U16
CVDD_48V9
CVDD_49V11
CVDD_50V13
CVDD_51V15
CVDD_52V17
CVDD_13L8
CVDD_16L14
CVDD_21M13
CVDD_19M9
CVDD_37R12
CVDD_38R14
CVDD_39R16
CVDD_45U12
CVDD_20M11
C1184
100nF
C1201
4.7uF
C1237
560pF
C1259
100nF
C1255
10nF
C1263
100nF
C1257
10nF
C1556
100uF
C1557
100uF
C1222
10nF
C1210
560pF
C1194
100nF
C1273
100nF
C1251
10nF
C1705
1000pF
C1229
560pF
C1250
10nF
C1568
2.2uF
C1207
560pF
C1703
1000pF
C1711
10nF
C1234
560pF
C1198
1000pF
C1281
10nF
C1700
2.2uF
C1230
560pF
C1260
100nF
C1218
100nF
C1197
100nF
C1558
10uF
C1278
100nF
C1269
100nF
C1212
1000pF
C1231
560pF
C1196
1000pF
C1223
10nF
C1232
560pF
C1249
10nF
C1179
2.2uF
C1205
100nF
C1177
100uF
C1227
2.2uF
C1193
1000pF
C1706
10uF
C1279
100nF
C1211
560pF
C1254
10nF
C1220
10nF
C1180
1000pF
C1290
10nF
C1238
560pF
B131
2200pF
1
2
3
C1272
100nF
C1178
10uF
C1214
1000pF
C1182
10nF
C1206
10nF
C1710
10nF
C1181
1000pF
C1190
560pF
C1560
100nF
C1189
560pF
C1708
100nF
C1282
10nF
C1183
10nF
C1219
100nF
C1203
10nF
C1224
10nF
C1571
10uF
C1702
10nF
C1187
560pF
C1266
2.2uF
C1236
560pF
C1202
100nF
C1570
10uF
R365 0ENU
C1188
560pF
C1252
10nF
C1709
100nF
C1176
100uF
C1286
10nF
C1195
10nF
C1239
560pF
C1271
100nF
C1209
560pF
TMS320C6657DSP1C
DVDD15_1B10
DVDD15_2C6
DVDD15_3C17
DVDD15_4C21
DVDD15_5D2
DVDD15_6D4
DVDD15_7D8
DVDD15_8D13
DVDD15_9D15
DVDD15_10D19
DVDD15_11F7
DVDD15_12F9
DVDD15_13F11
DVDD15_14F13
DVDD15_15F17
DVDD15_16F19
DVDD15_17G8
DVDD15_18G10
DVDD15_19G12
DVDD15_20G14
DVDD15_21G16
DVDD15_22G18
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.0V 1.0V & 1.5V for SERDES
GROUND
Place near to DSPVCC1V0VCC1V0
VCC1V0
VCC1V5
VCC1V0
VCC1V5
VCC1V0
VCC1V5 VCC1V5
VDDR1 VDDR2 VDDR3 VDDR4
VDDT1
VDDR1
VDDT1
VDDT2
VDDT2
VDDR2
VDDR3 VDDR4
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP POWER 2
C
25 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP POWER 2
C
25 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
DSP POWER 2
C
25 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
C1481
560pF
C12954.7uF
C1294
560pF
B127
2200pF
1
2
3
TMS320C6657DSP1E
VDDT1_1K19
VDDT1_2L20
VDDT1_3M19
VDDT1_4N20
VDDR1M20
VDDT2_1W8
VDDT2_2W10
VDDT2_3W12
VDDT2_4Y7
VDDT2_5Y9
VDDT2_6Y11
VDDR2AA9
VDDR3AA3
VDDR4AA5
C1277
10nF
TMS320C6657DSP1B
CVDD1_1J8
CVDD1_2J18
CVDD1_3K9
CVDD1_4K17
CVDD1_5T9
CVDD1_6T17
CVDD1_7U8
CVDD1_8U18
C1479
10nF
C1489
560pF
C13004.7uF
C1288
10nF
C1492
1000pF
C1477
560pF
C1486
100nF
B190
2200pF
1
2
3B110
2200pF
1
2
3
C1296
100nF
C1488
10nF
C1280
10nF
B130
2200pF
1
2
3
C1490
100nF
C1299
560pF
C1484
10nF
C1284
100nF
TMS320C6657DSP1F
VSS_165AD6
VSS_166AD9
VSS_167AD12
VSS_168AD16
VSS_169AE1
VSS_170AE4
VSS_171AE7
VSS_172AE10
VSS_173AE13
VSS_174AE25
VSS_1A1
VSS_2A10
VSS_3A25
VSS_4B6
VSS_5B17
VSS_6C2
VSS_7C4
VSS_8C8
VSS_9C13
VSS_10C15
VSS_11C19
VSS_12D21
VSS_13E11
VSS_14F3
VSS_15F6
VSS_16F8
VSS_17F10
VSS_18F12
VSS_19F14
VSS_20F16
VSS_21F18
VSS_22G7
VSS_23G9
VSS_24G11
VSS_25G13
VSS_26G15
VSS_28H6
VSS_29H8
VSS_30H10
VSS_31H12
VSS_32H14
VSS_33H16
VSS_34H18
VSS_35H20
VSS_36H21
VSS_37H23
VSS_38H25
VSS_39J7
VSS_40J9
VSS_41J11
VSS_42J13
VSS_43J15
VSS_44J17
VSS_45J19
VSS_46J22
VSS_47J23
VSS_48J24
VSS_49K2
VSS_50K6
VSS_51K8
VSS_52K10
VSS_53K12
VSS_54K14
VSS_55K16
VSS_56K18
VSS_57K20
VSS_58K23
VSS_59L7
VSS_60L9
VSS_61L11
VSS_62L13
VSS_63L15
VSS_64L17
VSS_65L19
VSS_66L21
VSS_67L23
VSS_68L25
VSS_69M6
VSS_70M8
VSS_71M10
VSS_72M12
VSS_27G17
VSS_73M14
VSS_74M16
VSS_75M18
VSS_76M22
VSS_77M23
VSS_78M24
VSS_79N4
VSS_80N7
VSS_81N9
VSS_82N11
VSS_83N13
VSS_84N15
VSS_85N17
VSS_86N19
VSS_87N23
VSS_88P6
VSS_89P8
VSS_90P10
VSS_91P12
VSS_92P14
VSS_93P16
VSS_94P18
VSS_95P20
VSS_96P21
VSS_97P23
VSS_98P25
VSS_99R7
VSS_100R8
VSS_101R9
VSS_102R11
VSS_103R13
VSS_104R15
VSS_105R17
VSS_106R19
VSS_107R22
VSS_108R24
VSS_109T2
VSS_110T6
VSS_111T8
VSS_112T10
VSS_113T12
VSS_114T14
VSS_115T16
VSS_116T18
VSS_117T20
VSS_118U7
VSS_119U9
VSS_120U11
VSS_121U13
VSS_122U15
VSS_123U17
VSS_124U19
VSS_125V6
VSS_126V8
VSS_127V10
VSS_128V12
VSS_129V14
VSS_130V16
VSS_131V18
VSS_132V20
VSS_133W3
VSS_134W7
VSS_135W9
VSS_136W11
VSS_137W13
VSS_138W15
VSS_139W17
VSS_140W19
VSS_141Y6
VSS_142Y8
VSS_143Y10
VSS_144Y12
VSS_145Y14
VSS_146Y16
VSS_147AA4
VSS_148AA6
VSS_149AA8
VSS_150AA10
VSS_151AB2
VSS_152AB6
VSS_153AB9
VSS_154AB12
VSS_155AB20
VSS_156AB24
VSS_157AC1
VSS_158AC4
VSS_159AC7
VSS_160AC10
VSS_161AC13
VSS_162AD1
VSS_163AD2
VSS_164AD3
C1478
100nF
B128
2200pF
1
2
3
C1287
100nF
C1267
1000pF
C1291
10nF
B129
2200pF
1
2
3
C1289
560pF
C1297
10nF
C1487
1000pF
C1292
100nF
C1480
1000pF
C1482
100nF
C1283
100nF
C1491
10nF
C1493
1000pF
C1298
560pF
C1483
1000pF
C1485
560pF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place next to UCD9222
PMBus RESISTANCE ( K ohm )
OPEN
11
10
9
8
7
6
5
4
3
2
1
0
SHORT
--
205
178
154
133
115
100
86.6
75
64.9
56.2
48.7
42.2
--
Corresponding "EA" Pins MUST be routed as differential signals and connectednext to DSP for specific rails
Series resistors on EA nets to be placed at the load for proper voltage feedback.
Provide min 25 thermal vias for IC
CVDD/CVDD1
PMBUS Address: 78 (6*12+6)
Each 10nF and 22uF cap needs to be tightly coupled to Vin and PGND of the UCD7242.
SMART REFLEX
PMBus Address Bins
1.0V@ 1.1ACVDD @2.7A
Inductor Calculation for CVDD
L= ( 12.5 - 1 ) / (2.7) * (1/12.5) / 750K = 0.46 uH
Inductor Calculation for CVDD1
L= ( 12.5 - 1 ) / (1.1) * (1/12.5) / 750K = 1.11 uH
Reserved forfuture use
- C444 and C372 should be mounted adjacent to UCD9222 and connected without a via- Components related to Isense pins should be located adjacent to UCD9222 with tightly coupled gnds.
EAP110E
10E
10E
10E
750E
560pFEAN1
CVDD
GND
EAP1
EAN1
VCC1V0
GND
EAP2 750E
560pFEAN2 EAN2
EAP2
DSP UCD9222
Resistor Calculation for Isense
Rmon = Vmon/ (Imax x 20 uA/A)Vmon = 12*1.5/(1.5+10.2) = 1.53V
Rmon1 = 1.53*1000/(2.7*20) K = 28.49K
Rmon2 = 1.53*1000/(1.1*20) K = 69.93K
- Vin cap, Pgnd connection and Vout bulk caps must all be connected by a continuous copper pour on outer layer where UCD7242 is mounted. - If these connections are broken into islands, inductance of vias will degrade the performance of power stage resulting in increased ripple
Vin = 11.5V to 12.5VFsw = 750kHz
Ref Ind for CVDD = 1.2uHRef Ind for VCC1V0 = 2.3uH
PMBus Address
EAP1
FF-1APWM-1A
PWM-1A
SRE_A
FF-1A
Isense-1A
TE
MP
1_2
PWM-2A
FF-2A
SRE_B
Isense-2A
FF-2APWM-2A
EAN2
EAP2
Isense-2A
UCD9222_PG1UCD9222_PG2
CS2A
CS1A
EAN1
9222_TCK
9222_TRST#
UCD9222_LINMON
PMBUS_RST#
PMBUS_RST#
UCD9222_LINMON
TEMP1_2
9222_TDO9222_TDI
9222_TMS
PMBUS_ALTPMBUS_DAT
PMBUS_CTL
PMBUS_CLK
Isense-1A
VCC3V3_AUX
VCC12
CVDD
VCC12
VCC1V0
VCC3V3_AUX
VCC12
CVDD
VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUX V33A_9222
VCC3V3_AUX
VCC3V3_AUX
VCC1V0
VCC3V3_AUX
BIPMBUS_DAT[22]
IN UCD9222_ENA1 [22]
INPMBUS_CTL[22]
INPMBUS_CLK[22]
IN UCD9222_ENA2 [22]
INUCD9222_RST#[22]
INUCD9222_VIDA[18]INUCD9222_VIDB[18]INUCD9222_VIDC[18]INUCD9222_VIDS[18]INUCD9222_VID2A[23]INUCD9222_VID2B[23]INUCD9222_VID2C[23]INUCD9222_VID2S[23]
OUTPMBUS_ALT[22]
OUT UCD9222_PG1 [22]
OUT UCD9222_PG2 [22]
OUT PGUCD9222 [22]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
UCD9222RGZR
C
26 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
UCD9222RGZR
C
26 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
UCD9222RGZR
C
26 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
R260 10E
R2552K
R262
10K
C607
4.7uF
R263
1K1%
C461
47uF
R417 100E1%
UCD9222RGZRU32
VinMon4 Vtrack
45
Temp1/AuxADC146
Temp2/AuxADC22
ADC_REF48
EAp137
EAn138
EAp239
EAn240
JTAG_TRST31JTAG_TMS30
JTAG_TDI/SYNC_IN29
JTAG_TDO/SYNC_OUT28
JTAG_TCK27
PMBus_ADDR044
PMBus_ADDR143
PowerGood17
PMBUS_CLK10
PMBUS_DATA11
PMBUS_ALERT19
PMBUS_CNTRL20
RESET5
V33FB41
V33A34
V33DIO33
BPCAP35
VID1A16
VID1B18
VID1C21
VID1S7
VID2A22
VID2B23
VID2C24
VID2S9
CS1A42
DPWM1A12
ENA125
FLT1A6
PG113
IinMon1
CS2A3
DPWM2A14
ENA226
FLT2A8
PG215
AGND236
AGND347
DGND332
PowerPad49
R451 10K
R257100K
R253 100K1%
C460
10nF25V
C444 1uF
R406 10E
R420
1K
1%C462
47uF
R452 10K
R43910K
R338 10E
R258
1M
R405 750E
C370
100nF
R566 2E
C451 0.22uF
R373 22.1K1%
L16 1.2uH
3.0 Irms
TP19
C60210nF
C452 0.22uF
R440 10K
R438 10K
R454 10K
C464
4.7uF
C372
1uF
C447 10nF
C459
100uF
C454
47uF
R259
10K
R441 10K
U34
UCD7242RSJT
PWM_B1
SRE_B2
BST_B3
BSW_B4
VG
G5
VG
G_D
IS6
IMON_B7
test
mod
e8
FLT_B9
PGND_110
NC-PGND_111 PGND_212
SWB13
SWA14
FLT_A18
TM
ON
19
IMON_A20
AG
ND
21
BP
322
BSW_A23
BST_A24
SRE_A25
PWM_A26
VIN
_327
NC
-VIN
_228
VIN
_429
VIN
_130
NC
-VIN
_131
VIN
_232
PGND_315
NC-PGND_216PGND_417
R251 22.1K1%
R37610K
C449
22uF25V
R418 10K
C448
10nF
Q13
MCP9700AT-E/LT
NC11VOUT3
GN
D2
VDD4
NC25
C445 100nF
R331 10K
R40410K
R416 100E1%
R252
1.5K
R437
10K
NU
C609 10nF
C518
1000pF
C457
10nF25V
C455
10uF
C608 10nF
R247 0ENU
C603100nF
TP18
R411 10E
R254 100K1%
C446 560pF
C450
22uF25V
PMBUS1TSW-105-07-S-S
12345
C443 10nF
R415 2KNU
R419 10K
R261 750E
C458
100uF
C4631uF
R250
10.2K
1%
R2562K
L15 2.3uH
1.97A Irms
C467 560pF
R246 2KNU
C453
47uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC12
12V to 5V Generation
12V to 3.3_AUX Generation
3.3V_AUX @ 2.75A
5V @ 0.8A
12V to 1.5V Generation
1.5V @ 2A
Vin = 11.5V to 12.5VFsw = 900kHz
XDS560 v2 Mezzanine Power
Snubber Circuit
Vin = 11.5V to 12.5VFsw = 900KHz
Snubber Circuit
Snubber Circuit
Over Current Protection
TVS
Voltage BreakDown = 13.3V
I(hold) = 3AI(trip) = 6ATrip time= 10.8s
Ref Ind = 22uHRef Cap = 32uF
Lmin = ((12.5 - 5)/(0.8 * 0.3) * (5 / (12.5 * 570kHz)) = 21.87uH
Co_min = 1/( 2 * 3.14 * (5/0.8)* 570kHz) = 44.7nF
Lmin = ((12.5 - 3.3)/(3 * 0.3) * (3.3 / (12.5 * 900kHz)) = 2.96uH
Co_min = (2*1) / (900kHz*0.0825) = 2.69uF
Rrt = 48000 x 900^(-0.997) - 2 = 53.6K
Ref Ind = 2.2uHRef Cap = 32uF
Lmin = ((12.5 - 1.5)/(2 * 0.3)) * (1.5 / (12.5*900kHz)) = 2.44uH
Co_min = (2*1)/(900kHz*0.075) = 29.62uF
Ref Ind = 1.2uHRef Cap = 122uF
Rrt = 48000 x 900^(-0.997) - 2 = 53.6K
Vin = 11.5V to 12.5VFsw = 570kHz
VCC12VCC12_AMC
VCC5
VCC3V3_AUX
VCC12 VCC3V3_AUX
VCC3V3_AUXVCC5VCC12
VCC12
VCC1V5
VCC3V3_AUX
VCC5VCC3V3_AUX
VCC3V3_AUX
INVCC_5V_EN[22]
INVCC1V5_EN[22]INXDS560_IL[22]
OUT VCC3V3_AUX_PG [22]
OUT VCC5_PG [22]
OUT VCC1V5_PG [22]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
POWER SUPPLY 1
C
27 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
POWER SUPPLY 1
C
27 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
POWER SUPPLY 1
C
27 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
TP26
C424
1200pF
C1437
10uF25V
C551
100nF
L118 2.2uH 3.7A Irms
R244
1.69K
1%
L3 1.2uH 2.3A Irms
R1182 10ENU
R1181 10ENU
R143
1K
C2325
10uF25V
R238
10K
1%
C438
10nF16V
C431 100nF10V
R240
10K
C1129 100nFNU
R136
10K
C1127 100nFNU
C428
10nF16V
R2106
2.2K
R241
1.87K
1%
R374
31.6K
1%
+CT6
100uF
R237
33K
NU
R314
10K
L2 22uH 2.2A Irms
TP27
R333
2K
1%
C427
56pF
R334
31.6K
1%
C420 100nF10V
C422
22uF10V
R332
53.6K
1%
C536100nF
DC_IN1
RAPC712X
3
21
C549
22uF25V
C434
8200pF
R483 0E
C545
4.7uF25V
U29TPS54231D
BOOT1
VIN2
EN3
SS4
PH8
GND7COMP6
VSENSE5
B158 120_100MHz
R242
53.6K
1%
C529
100nF25V
R1573 10ENUC432
22uF10V
D7
B340A-13-F12
D18
SMBJ12A
C53710uF
C1126 100nFNU
560V2_PWR1TSW-104-14-F-D1 23 45 67 8
U36TPS54620RGYR
RT/CLK1
GND12
GND23
PVIN14
PVIN25
VIN6
VSENSE7
PWRGD14
BOOT13
PH212
PH111
EN10
SS/TR9
COMP8
EPAD15
R375
10K
R350
10K
B164 120_100MHz
C430
22uF10V
D17
LED
F9 1A
R336
10K
1%
R2009 0E
R239
22.6K
1%
C539
100uF6.3V
F8 4A
C423
10uF25V
C553
10uF
C538
100nF25V
B165 120_100MHz
C542
22uF25V
R335
10K
1%
TP30
C429 100nF 10VC541
4.7uF25V
TP25
C32
10nF
R243
9.09K
1%
R245
10K
1%C433
10nF16V
F7 3A
U30TPS54620RGYR
RT/CLK1
GND12
GND23
PVIN14
PVIN25
VIN6
VSENSE7
PWRGD14
BOOT13
PH212
PH111
EN10
SS/TR9
COMP8
EPAD15
C544
22uF25V
F6 RUEF300
VCC
GND
U253SN74LVC1G07DBVR
123 4
5C426
100nF25V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
R1
R2
R1
R2
R1
R2
R1
R2
3.3V_AUX to 1.2V Generation 3.3V_AUX to 1.8V_AUX Generation
3.3V_AUX to 1.8V Generation3.3V_AUX to 2.5V Generation
3.3V_AUX to 0.75V Generation
Vout = (R1+R2)/R2*1.204 = (0+10k)/10k*1.204 = 1.204V
1.8V @ 0.14A
1.8V_AUX @ 0.31A
2.5V @ 0.35A
0.75V @ 0.16A
Vth = 1.67V
1.8V Superviser Circuit
20 mil trace width
1.2V @ 0.6A
Vout = (R1+R2)/R2*1.204 = (28k+56.2k)/56.2k*1.204 = 1.804V
Vout = (R1+R2)/R2*1.204 = (39.2k+36.5k)/36.5k*1.204 = 2.50V
Vout = (R1+R2)/R2*1.204 = (28k+56.2k)/56.2k*1.204 = 1.804V
VCC3V3_AUXVCC1V2
VCC3V3_AUX VCC1V8_AUX
VCC3V3_AUX VCC2V5
VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUX
VCC2V5
VCC1V5
VCC3V3_AUX
VCC0V75
VCC1V8
VCC3V3_AUX
VCC1V8
VCC1V8_AUX
INVCC2V5_EN[22]
INVCC1V8_EN1[22]
INVCC0V75_EN[22]
OUT VCC0V75_PG [22]
OUT VCC2V5_PG [22]
OUT VCC1V8_PG [18,22]
INDSP_VREFSSTL[14,15]
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
POWER SUPPLY 2
C
28 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
POWER SUPPLY 2
C
28 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
POWER SUPPLY 2
C
28 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
R2231
4.7K
C2557
100nF
Q4TPS73701DRBT
EN5
GND4
VIN8
VOUT1
FB3
EPAD9
NC12
NC26NC37
R141
10K
R221
0E
TP34
C409
10uF
TP28
R222
28K
1%
C523
100nF
C507
10uF
C398
10uF
C410
100nF
C517
10uF
Q2TPS73701DRBT
EN5
GND4
VIN8
VOUT1
FB3
EPAD9
NC12
NC26NC37
C513
100nF
C407
10uF
TP31
R21 10K
R2227 0E
C506
100nF
C509
10uF
R2229 0E
R2230 0E
C547
100nF
C403
10nF
R227
36.5K
1%
C405
10uF
R25 10K
Q5TPS73701DRBT
EN5
GND4
VIN8
VOUT1
FB3
EPAD9
NC12
NC26NC37
C514
10uF
R225
39.2K
1%
C395
10uF
C406
100nF
R385
28K
1%
C397
10uF
TP32
U27TPS51200DRCT
REFIN1
VLDOIN2
VO3
PGND4
VOSNS5
REFOUT6
EN7
GND8
PGOOD9VIN
10
EPAD11
R230
10K
C515
100nF
Q3TPS73701DRBT
EN5
GND4
VIN8
VOUT1
FB3
EPAD9
NC12
NC26NC37
C554
100nF
R3226 0E
TP21C399
10uF
R75
10K
C408
10uF
R142 1K
R223
10K
1%
R2228 0E
U1131TPS3808G18DBVR
RESET#1
GND2
MR#3
CT4
SENSE5
VDD6
TP20
VCC
GND
U251SN74LVC1G07DBVR
123 4
5
TP33
R22
10K
R23
10K
C510
100nF
R386
56.2K
1%
C508
100nF
C2556
100nF
TP24
TP22
R224
56.2K
1%
C548
100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
eInfochips
1.0
TMDSEVM6657 - REVISION HISTORY
SCH. REV.PCB REV. CHANGE DESCRIPTION DATE AUTHOR
- CLK3 removed- Series Termination removed from GPIO0 to GPIO13 lines
0.63-FEB-2012
0.1- Clock buffer U1132 removed. 2 OR gates (U268, U269) and the corresponding circuitry to buffer EMU_TCK added.- 4 Test Points for Gnd added.- ETH_SCK net renamed to ETH_SDA- SIGDETunconnected with LOS; its directly pulled high. R145 and R146 removed - SYSPG_D1 LED changed to Yellow colour from Green
02-APR-2012 eInfochips
- D9 and D10 part changed with one with higher current capacity.- R134 changed to 1K from 4.7K- NU resistors R433 and R434 changed to 10K and 1.2K resp. They are to be mounted.- R12 and R17 replaced by 100nF caps C1225 and C1226- R70 and R71 mounting status changed from NU to populated.- U6 (DDR3 ECC chip) made NU.- DDR3 Clock frequency from Clock Gen changed to 50 MHz (software change only).
1.1
20-MAR-2012 eInfochips
AMC Hole
On Board Fiducials
2.0
Mounting Holes
Dummy Components
0.2
- 10 nF capacitors (C457 and C460) added on VCC12 input rail of U34. - Capacitors on CVDD rail optimized from two 220uF, two 100uF and four 47uF to two 100uF and two 47uF. - Capacitors on VCC1V0 rail optimized from one 220uF, three 47uF and one 10uF to two 47uF and one 10uF.- An additional 22uF cap (C549) added on VCC12 input for U29. C426 changed from 10nF to 100nF.- R183 changed to 1K from 4.7K. - SIGDET connected to VCC2V5 using R146. - R1273 changed to 4.7K from 10K.
02-MAY-2012 eInfochips
0.3
- L15 and L16 changed to 2.3uH and 1.2uH respectively- R251 and R373 changed to 22.1K- C549 moved before B158 on 12V plane- C2325 changed from 100nF to 10uF- R2203 made NU and R2226 to be mounted
07-MAY-2012 eInfochips
0.4 - NOR Flash density label corrected to 32 Mb from 16MB. 20-JUL-2012 eInfochips
26-JUL-2012- DISCLAIMER Changed0.5 eInfochips
0.6- Asthetical Change Name swap between LVDS and HCSL on page 18
06-DEC-2012 eInfochips
0.7eInfochips29-JAN-2013
- Asthetical Change Note for DDR3 Slew-Rate setting corrected on page 14
0.8 - R82 and R83 changed to 10K- R85 and R957 made NU
eInfochips22-FEB-2013
0.9 - The Resistors R896,R67 and capacitor C555 are redundant components on EMU_TCK and can be NU from design.- Pull-up resister R1119 on EMU_TCK change from 10K to 4.7K eInfochips28-NOV-2013
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
REVISION HISTORY
C
29 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
REVISION HISTORY
C
29 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
Title
Size
Project
Rev
Date:
Document Number
ofSheet
Designed for TI by eInfochips
REVISION HISTORY
C
29 29Thursday, November 28, 2013
TMDSEVM6657
16_00132_02 2.9
DM15
US AC Mains Cable
BRK1SOCKET_CSBGA625
NU
DM4
UART Custom Cable
DM12
Board Stud
DM14
Universal Travel Adaptor
DM19
Shorting Link
STC02SYAN DM10
Board Stud
H4
H35-NPTH
1
DM2
LAN cable
H2
H35-NPTH
1
DM9
Board Screw
FM4
Fiducial
FM2
Fiducial
DM13
Board Stud
DM3
Heat-Sink
DM8
Board Screw
DM5
USB miniB cable
H5
H27P35-MTH
1DM18
Shorting Link
STC02SYAN
DM17
Shorting Link
STC02SYAN
H1
H35-NPTH
1
H3
H35-NPTH
1
DM11
Board Stud
DM16
Shorting Link
STC02SYAN DM6
Board Screw
DM1
Power Adaptor
AS300-120-AQ250-E0902
FM3
Fiducial
FM1
Fiducial
DM7
Board Screw
