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Tetsuya Tatsumi
Sony Semiconductor Solutions Corporation
半導体微細加工における プラズマ応用について
1. Introduction
2. High etch rate & Selectivity
3. Suppression of CD variation
4. Minimization of plasma induced damage
5. Summary
Outline
2017.12.22 原子分子データ応用フォーラムセミナー 特別セッション「半導体製造・プラズマプロセスと原子分子過程・分光研究とのかかわり」
Moore’s Law
Number of transistors increased exponentially
Gate
Source Drain
SiO2
MOS transistor
Poly-Si
Si-sub.
Transistor size
0.7 x every 2 years
ITRS 2009
1995 2005 2000 2010 2015 2020 2025
1000
100
10
1
Gat
e le
ngth
(nm
)
Production year
Requirement of plasma technologies for miniaturization of transistors
International Technology Roadmap for Semiconductors 2009 Edition
Poly-Si
Si-sub.
Outline
1. Introduction
2.1990～ : High etch rate & Selectivity
3.2000～ : Suppression of CD variation
4.2010～ : Minimization of damage
5.Summary
Requirements (1990～）
1995 2005 2000 2010 2015 2020 2025
1000
100
10
1
Gat
e le
ngth
(nm
)
Production year
Gate
Source Drain
SiO2 ITRS 2009 Poly-Si
Si-sub.
Gate length > 100nm Anisotropic profile High etch rate High selectivity 100-200mmφ wafer
Process flow
Si
Si-substrate
SiO2
Gate SiO2
Poly-Si
Doped poly-Si
Si
Mask Poly-Si
SiO2
Resist mask Plasma etching SiO2 deposition
Etch back & Doping
Gate
Source Drain
SiO2
Poly-Si
Si-sub.
B.P.
Si 2700℃
SiBr4 154℃ SiCl4 58℃ SiF4 -86℃
Dry etching of poly-Si gate on thin oxide film
HBr/O2 plasma
Si （solid） ＋ 4Br（gas） → SiBr4 （gas）
Si
Surface reaction of Si etching
Plasma ?
Si
Mask Poly-Si
SiO2
Resist mask Plasma etching
Wafer
Gas
Pump
～
～
Dry etching system
Sheath
Plasma ?
Si-Si < Si-Br < Si-O Binding energy:
Poly-Si
Si
Br
O Sidewall film (SiBrxOy)
SiO2
Dry etching of poly-Si gate on thin oxide film Sidewall film Anisotropic profile
Low ion energy High selectivity to SiO2
Main etch Over etch (Low ion energy)
SiBrx
Surface reaction of Si etching
Etching systems
iii) Capacitive Inductive Wave heating
Current loss to walls ↓
High density plasma Independent control of ion energy
～
CCP CCP
13MHz
～
N S
MERIE ME-RIE
13MHz
～
～
2f-CCP 2f-CCP
60/13MHz
ICP
～
～
ICP
13/13MHz
～
ECR ECR
2.45GHz 400kHz
i) Higher frequency
ii) Magnetic field
Collision rate↑ (ionization)
time
x, y, z
e
e
e
e
Plas
ma
dens
ity
Ion energy
1990～
Vertical profile High etch rate High selectivity
HBｒ/O2 High density source Low ion energy
1. Introduction
2.1990～ : High etch rate & Selectivity
3.2000～ : Suppression of CD variation
4.2010～ : Minimization of damage
5.Summary
Outline
1995 2005 2000 2010 2015 2020 2025
1000
100
10
1
Gat
e le
ngth
(nm
)
Production year
Gate length <100nm 300mmφ wafer High etch rate Anisotropic profile High selectivity Uniformity High-k/Metal Gate
Requirements (2000～）
193nm (ArF LASER)
Mask size
Physical gate length
Photo lithography
Resist mask Poly-Si
ITRS 2009
Mask size
Gate length
Slimming
Fluctuation of CD (Critical Dimension)
Narrow pattern Mask roughness
70nm
40nm±10% (CD)
Edge roughness
Top view of resist mask
Poly-Si
LWR (Line width roughness)
LWR is improved by HBr plasma cure Resist
HBr/O2 plasma w/ bias
Etching
HBr plasma w/o bias
HBr cure
Poly-Si
Poly-Si
O
O
O
O
O
O
O
OR4 R5
R1 R2 R3
O
O
O
O
O
O
O
OR4 R5
R1 R2 R3
Tg = 402.6 K
Tg=High (w/o cure)
O
O
OH
O
O
O
O
OR4 R5
R1 R2 R3
O
O
OH
O
O
O
O
OR4 R5
R1 R2 R3Tg=Low (with cure)
Tg = 364.6 K
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0 3 6 9 12 15 18 21 24 27 30
LWR [nm]
Freq
uenc
y
W/O HBr Cure W/ HBr Cure
Improvement of LWR
HBr cure
“Softening” of resist surface by HBr plasma treatment A. Ando, DPS2005 & Thin Solid Films 515 (2007) 4928
Mask size
Gate length
Slimming
Narrow pattern Mask roughness
70nm
40nm±10%
Edge roughness (Molecular size )
Wiggling ( Plasma Modification)
Top view of resist mask
Fluctuation of CD (Critical Dimension)
Poly-Si
Bending/Wiggling
Kurihara, DPS2004
C-F polymer
Fluorination
VUV, ion bombardment, and temperature
D. Nest , Plasma Process. Polym. 6 (2009) 649
Stress between softened layer of resist and deposition layer I. Sakai, JJAP 46 (2007) 4286
SiBrx
Nagase, DPS2001
CD non-uniformity within a wafer
Slimming, Surface cure, etc. Small pattern with less LWR
Uniformity within a wafer ?
CD non-uniformity within a wafer HBr/O2 plasma
SiBrx
Poly-Si
Si-sub.
SiO2
ICP
Control Knobs
～
～ Spatial distribution of Plasma density, Gas flow & Wafer temperature
Power
Gas flow
Sub. temperature
L. Chen, AVS2004
Center 37℃
Edge 30℃
CD uniformity
2000~
40nm±10%
Gat
e le
ngth
Mask size
Plasma cure, Control Knobs, EES Minimization of CD variation
within a chip
within a wafer
within a lot
1. Introduction
2.1990～ : High etch rate & Selectivity
3.2000～ : Suppression of CD variation
4.2010～ : Minimization of damage
5.Summary
Outline
Requirements (2010～）
Gate length <30nm Less damage 450mmΦ wafer High etch rate Anisotropic profile High selectivity Uniformity High-k/Metal gate Fin transistor
1995 2005 2000 2010 2015 2020 2025
1000
100
10
1
Gat
e le
ngth
(nm
)
Production year
ITRS 2009
http://www.intel.co.jp
Resist mask
Poly-Si
SiO2 (1.4nm)
Si-Sub.
Sel. > 100
Main etch Over etch DHF treatment
Si recess
Damaged layer formed during gate etching
(High selectivity ≠ Less Damage)
T. Ohchi., JJAP 47 (2008) 5324
Si recess
Si recess induces fluctuation of Vth or Id
Resist mask
Poly-Si
SiO2 (1.4nm)
Si-Sub.
Sel. > 100
Main etch Over etch DHF treatment
Si recess
0
4
8
12
16Dep
th fr
om th
e su
rface
(nm
)
BrO
1000 atomic%
O
Oxidizedlayer
5 nmTEM
Oxidized layer
Dislocated Si
HRBS
Damaged layer formed during gate etching
(High selectivity ≠ Less Damage)
HBr ?
Ion energy (eV)
Rp: 0.5 nm 2 nm 5 nm 10 nm15 nm
10
5
0
After injection of 1000atoms
50 30010 100
Quantitative control of IEDF
Minimization of ion induced damage
0
500
1000
1500
2000
2500
0 50 100 150 200 250 300
IED
[arb
. uni
ts]
Energy [eV]
Vpp=400 V 270 V 160 V
50 V HBr/O2, 60mT Bias=67W
50V
Vpp=400V
270V
160V
0
5
10
15
0 400 800 Exposure time [s]
Dam
age
thic
knes
s [n
m]
50 V
Vpp=400 V
160 V
270 V
Suppression of Si recess
～
～
2f-CCP 2f-CCP
60/13MHz
T. Ohchi., DPS2007
Sidewall etching
Sidewall etching
SiO2 or High-k
SiN/SIO2
× × × × × ×
CF4/O2
Poly-Si
D it (×
1010
eV-1
cm-2
)
300
0
600
900
0 50 100
initial
Remaining thickness of SiO2 (nm)
Dit caused by Ion or Photon Dit: Interface trap density
Si
SiO2
Si
SiO2 Damage Si-sub
Sidewall etching
SiO2 or High-k
SiN/SIO2
× × × × × ×
CF4/O2 D it (
×10
10eV
-1cm
-2)
300
0
600
900
0 50 100
initial
Remaining thickness of SiO2 (nm)
Dit caused by Ion or Photon
Poly-Si
Dit: Interface trap density
Si
SiO2
Si
SiO2 Damage Si-sub
SiO2 Si-sub
Si
SiO2
Si
SiO225nm SiN
0 50 100
D it (eV
-1cm
-2) Si/SiO2
Si/SiO2/SiN 1011
1012
1013
initial 0 50 100
1010
Remaining thickness of SiO2, SIN(nm)
Damage at SiO2/Si interface
Dit (SiN) < Dit (SiO2)
0
20
40
60
80
100Pene
trat
ion
dept
h (n
m)
100
20
40
60
80
100 150 200 300 50 0
250
Si
SiO2
Wavelength (nm)
Dose(mJ/cm2)
D it (n
orm
alize
d X=
0)
UV (λ=248nm,KrF)
0 600 1200 0.5
1.0
1.5
100
20
40
60
80
0
× × × × × × × ×
UV induced damage
VUV is absorbed at top surface of SiO2 (or SiN)
2010～
Quantitative control of IEDF Prediction of ion and UV/VUV penetration Minimization of physical & radiation damage
Ion energy (eV)
Rp: 0.5 nm 2 nm 5 nm 10 nm15 nm
10
5
0
After injection of 1000atoms
50 30010 100
1995 2005 2000 2010 2015 2020 2025
1000
100
10
1
Gat
e le
ngth
(nm
)
Production year
ITRS 2009
Miniaturization limit ?
2020～ （？） Gate length <10nm? Less damage 450mmΦ wafer High etch rate Anisotropic prpfile High selectivity Uniformity High-k/Metal gate Fin transistor 3D CNT/Graphene Spin device・・・
‘85 ‘90 ‘95 ‘00 ‘05 ‘10
2t
g-line
60t
EUV
10t
ArF
5t
KrF
3t
i-line
10
8
6
4
2
Cos
t (Bi
llion$
）
‘15
25t
Immersion
0
Further miniatuarization Price of Lithography tools
Cost limit ?
SADP, SAQP・・・
ITRS 2013
Self-Aligned Double/Quadra Patterning
Further miniatuarization
3D LSI
High rate etching for TSV
Several chips are stacked and coupled to each other using “through Si via (TSV) ”
MRAM / Spin electronics
New device, New materials
WL WL
BL
BL
Buffer layerFree layerDielectric layerPinning layerAnti-ferromagnaetic layer
MTJ"0":Low
"1":High
(AFM layer)<MRAM> <MTJ device>
CoFeB
Graphene
New requirement for plasma process & system
Carbon electronics
(Ferromagnetic materials)
(CNT, graphene)
Toward future device fabrication
Monitoring ?
Control ?
Prediction ?
Data base ?
Quantitative understanding of plasma and surface reactions Quantitative manipulation of electrons, ions and photons
Fine pattern, TSV, New materials & structures
Summary
1990～ High etch rate & Selectivity ・HBr/O2 ・High density / low ion energy plasma
2000～ Suppression of CD fluctuation ・Suppression of LWR and Wiggling of mask ・Knobs for plasma uniformity control
2010～ Minimization of plasma induced damage ・IEDF control, UV/VUV control ・Advanced monitoring & simulation 2020～ New plasma processes for future devices ・Quantitative control of electrons, ions and photons
