C ern A nd RIOC urrent A mplifier

Werner Riegler CERN, Feb. 20th, 2003

CCernernAAndndRIOCRIOCurrenturrentAAmplifiermplifier

An 8 channel ASD front end for the LHCb muon system

Preliminary Design Review

February 20th

CERN


Purpose of the ReviewPurpose of the Review

See if we are on the right track for See if we are on the right track for submitting a final prototype by middle 2003.submitting a final prototype by middle 2003.

Get comments from designers who went Get comments from designers who went through the entire chip development and through the entire chip development and production phase.production phase.

Point out critical items or worries.Point out critical items or worries.

Find points that we might have overlooked. Find points that we might have overlooked.


LHCb Muon SystemLHCb Muon System

5 muon stations, one in front (M1), 4 behind (M2-M5) the calorimeter

A muon trigger requires the coincidence of hits in all 5 stations within the bunchcrossing time of 25ns in a certain spatial window that selects the muon momentum.

Granularity 1x2 cm to 10x20cm.


DetectorDetector

‘Standard’ Multi Wire Proportional ChamberWire pitch 1.5mm, Cathode distance 5mm, 30um wire diameter

Wires are connected to form ‘wire pads’, negative signal. Cathodes are segmented to form ‘cathode pads’ positive signal, factor two smaller.

Many ‘different’ chamber types


Many ‘different’ chamber types with different capacitance, grounding, signal flow …The chip has to be tested on ALL chamber types


DetectorDetector

We carefully studied readout and guardtrace geometries to minimize crosstalk.


DetectorDetector2 chamber layers are connected into one frontend.4 layers of MWPCs are combined into one station.


Detector and Signal CharacteristicsDetector and Signal Characteristics

I(t) = I0/(t+1.5ns), I(t) = I0/(t+1.5ns), positive (cathode readout) and negative (wire readout) input polaritypositive (cathode readout) and negative (wire readout) input polarity Around 100 primary electrons (in two layers)Around 100 primary electrons (in two layers) 30ns average arrival time of last electron 30ns average arrival time of last electron 2020s ion tail s ion tail 101055 gas gain gas gain 1MHz per channel maximum count rate (including safety)1MHz per channel maximum count rate (including safety) 3.4kV through 1nF … input protection3.4kV through 1nF … input protection Detector Capacitance 20-220pFDetector Capacitance 20-220pF 50fC average muon signal at the working point (for 10ns peaking time 50fC average muon signal at the working point (for 10ns peaking time

amplifier)amplifier) Background signals are factor 2-3 larger.Background signals are factor 2-3 larger. 125k front end channels.125k front end channels. 8 channels/chip8 channels/chip 1MRad radiation1MRad radiation


SpecificationsSpecifications

Positive/negative input polarityPositive/negative input polarity ttpp=10-15ns in front of the discriminator=10-15ns in front of the discriminator Detector capacitance 20-220pFDetector capacitance 20-220pF Input resistance <50 OhmInput resistance <50 Ohm Gain of 5mV/fC (delta input)Gain of 5mV/fC (delta input) <50ns average output pulse width<50ns average output pulse width Unipolar signal shaping Unipolar signal shaping Fully differentialFully differential Noise <1fC up to 100pF: 5fC cathode pad thresholdNoise <1fC up to 100pF: 5fC cathode pad threshold <2fC up to 200pF: 10fC wire pad threshold<2fC up to 200pF: 10fC wire pad threshold Baseline StabilityBaseline Stability


Baseline StabilityBaseline Stability

Average Cathode Signal (DC coupled)Ions take >20us to reach the cathode

Average Anode Signal (AC coupled)HV loading resistor of 100k together with decoupling capacitor of 680pF givestime constant of 68us.

The long ion drift (20us) together with the long HV recharge time affects the baseline from a signal for >100us. At 1MHz rate this causes baseline shift of 4fC and baseline fluctuation of 10fC r.m.s.


Project HistoryProject History

In Jan. 2000 we had no frontend chip that satisfied the needs In Jan. 2000 we had no frontend chip that satisfied the needs for the LHCb muon system.for the LHCb muon system.

Requirements: tRequirements: tpp=10ns, C=10ns, Cdetdet=10-200pF, R=10-200pF, Rinin<50<50, +- polarity, +- polarity Pierre Jarron et. al. (CERN) had just designed a preamp in Pierre Jarron et. al. (CERN) had just designed a preamp in

0.250.25m for silicon detectors. m for silicon detectors. The idea came up to adapt this chip for LHCb. Danielle Moraes The idea came up to adapt this chip for LHCb. Danielle Moraes

(UFRJ, CERN) started this project within her thesis work.(UFRJ, CERN) started this project within her thesis work. Late 2000, Anatoli Kachtchouk developed the ASDQ++ idea. He Late 2000, Anatoli Kachtchouk developed the ASDQ++ idea. He

adapted the ASDQ (Fermilab COT) to our needs by adding an adapted the ASDQ (Fermilab COT) to our needs by adding an external transistor to each channel. This solution satisfies our external transistor to each channel. This solution satisfies our specifications. Drawback: ‘Large’ cost (3.75$/chan. packaged specifications. Drawback: ‘Large’ cost (3.75$/chan. packaged and tested)and tested)

We decided to continue the CARIOCA development because of We decided to continue the CARIOCA development because of cost reasons and the fact that we have two other 0.25cost reasons and the fact that we have two other 0.25m CMOS m CMOS chips in the muon system (DIALOG, SYNC)->one production. It chips in the muon system (DIALOG, SYNC)->one production. It also opens the possibility of DIALOG-CARIOCA integration.also opens the possibility of DIALOG-CARIOCA integration.

The CARIOCA is our preferred solution, ASDQ++ is our The CARIOCA is our preferred solution, ASDQ++ is our fallback.fallback.


CARIOCA Block DiagramCARIOCA Block Diagram

Signal tail cancellation2x pole/zero, t0=1.5ns,topology from ASDQ

Preamp tail cancellation 1x pole/zero,topology fromATLAS MDT

Topology fromATLAS MDT

Preamp

LVDS,standard cell

topology fromATLAS MDTprototype


Baseline RestorerBaseline Restorer

The signal AC coupling (wire), the long signal tail (20us) together with high rate (1MHz) result in baseline fluctuations.

Solution: 1) Bipolar Shaping -> long dead time, wrong polarity crosstalk 2) Unipolar Shaping - Nonlinear Elements …nonlinear feedback loop: Originally we decided on a time constant of 2us. This was changed to 200ns.


Prototypes produced so farPrototypes produced so far


Prototypes produced so farPrototypes produced so far

We had many prototypes because we built up the blocks in a We had many prototypes because we built up the blocks in a step by step approach and step by step approach and NOTNOT because there were problems. because there were problems.

Up to CARIOCA6 we continuously built up the blocks without Up to CARIOCA6 we continuously built up the blocks without encountering problems.encountering problems.

Only on CARIOCA6 some serious problems appeared.Only on CARIOCA6 some serious problems appeared.

CARIOCA7 was booked already before receiving CARIOCA6, CARIOCA7 was booked already before receiving CARIOCA6, and there was no possibility to cancel it – there was not and there was no possibility to cancel it – there was not enough time to fix the problems.enough time to fix the problems.

CARIOCA8 was the first submission to really correct a CARIOCA8 was the first submission to really correct a problem.problem.

We see the submission in Q2 /2003 as the final prototype We see the submission in Q2 /2003 as the final prototype submission. submission.


People involved up to nowPeople involved up to now(very discontinuous)(very discontinuous)

Walter Bonivento (CERN, INFN Cagliari)Walter Bonivento (CERN, INFN Cagliari) Anatoli Kachtchouk (CERN, PNPI)Anatoli Kachtchouk (CERN, PNPI) Danielle Moraes (CERN, UFRJ)Danielle Moraes (CERN, UFRJ) Nicolas Pelloux (CERN)Nicolas Pelloux (CERN) Werner Riegler (CERN)Werner Riegler (CERN) Delia Rodriguez (CERN)Delia Rodriguez (CERN) Burkhard Schmidt (CERN)Burkhard Schmidt (CERN) Filipe Vinci (CERN)Filipe Vinci (CERN)

Up to now we didn’t have a real problem of manpower or Up to now we didn’t have a real problem of manpower or a lack of clever people.a lack of clever people.

We had the big problem of non-continuity of people.We had the big problem of non-continuity of people. In addition the people involved were ‘newcomers’ to the In addition the people involved were ‘newcomers’ to the

business of high speed analog fronted ASIC design.business of high speed analog fronted ASIC design. Although we are in frequent contact with the MIC group Although we are in frequent contact with the MIC group

we were lacking the continuous involvement of a we were lacking the continuous involvement of a ‘senior’ designer.‘senior’ designer.


Problems encountered in 2002Problems encountered in 2002

ProblemsProblems Offset variations Shaping: Very large pulse width ‘Instability‘ (output to input coupling) Gain difference from specification

Specification changesSpecification changes We integrated positive and negative preamp into

one chip.


Offsets VariationsOffsets Variations


OffsetsOffsets

CARIOCA6CARIOCA6 (March 2002) showed DC offset variations of (March 2002) showed DC offset variations of 48mV48mV r.m.s at the discriminator. r.m.s at the discriminator.

On On CARIOCA7CARIOCA7 (September 2002) this was reduced to (September 2002) this was reduced to 12mV12mV r.m.s. r.m.s.

On On CARIOCA8CARIOCA8 (Jan. 2003) we have (Jan. 2003) we have 4.3mV4.3mV r.m.s. r.m.s. corresponding to about 1fC.corresponding to about 1fC.

Our typical threshold is 5fC, cutting on 2 sigma (90% Our typical threshold is 5fC, cutting on 2 sigma (90% yield) gives 3-7fC threshold. yield) gives 3-7fC threshold.

We decided to use individual thresholds to be safe from We decided to use individual thresholds to be safe from the offset problem.the offset problem.


ShapingShaping


Shaping, mathematicalShaping, mathematicalMathematical 1/(t+1.5ns) with 2 pole/zero filters 9,2.57ns and 80/40ns, 10ns peaking time amplifier with n=2.

‘Signal tail around 1% at 240ns’,


Shaping, CARIOCA4Shaping, CARIOCA4CARIOCA4: preamp+shaper on chamber, Am241, external analog buffer AC coupled

Tail cancellation is ‘perfect’, but …Small bump at 70ns, even smaller bump at 280ns, below baseline


Shaping, CARIOCA5Shaping, CARIOCA5CARIOCA5: preamp+shaper+discriminator on chamber, shaper to discriminator internally AC coupled, Am241 2.9kV

Tail cancellation is ‘perfect’


Shaping, CARIOCA6 Shaping, CARIOCA6 CARIOCA6: preamp+shaper+BLR+discriminator, fully DC coupled

pos, Am, 3.10, 10mV

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 250 500 750 1000 1250 1500 1750 2000

Time (ns)

averaged discriminator output signal

average pulse width of more than 1us !


Shaping, CARIOCA8Shaping, CARIOCA8

The The AC couplingAC coupling of the analog output of CARIOCA4 and of the analog output of CARIOCA4 and internal AC coupling of the discriminator on CARIOCA5 internal AC coupling of the discriminator on CARIOCA5 ‘killed’‘killed’ the remaining 1% signal the remaining 1% signal tailtail..

With the full DC coupling of CARIOCA6, this 1% tail causes With the full DC coupling of CARIOCA6, this 1% tail causes very long dead time for large background pulses.very long dead time for large background pulses.

For CARIOCA8 we speeded up the BLR to 200ns in order to For CARIOCA8 we speeded up the BLR to 200ns in order to eliminate this tail (‘nonlinear AC coupling’). eliminate this tail (‘nonlinear AC coupling’).


ASDQ, Am2800V, thr 7fC ASDQ, Am3000V, thr 7fC

CARIOCA8, Am2800V, thr 7fC CARIOCA8, Am3000V, thr 7fC

Cathode Pad


ASDQ, Am3200V, thr 7fC ASDQ, Am3300V, thr 7fC

CARIOCA8, Am3200V, thr 7fC CARIOCA8, Am3300V, thr 7fC

Cathode Pad


ASDQ, Am241, Average Discriminator Output, threshold 7fC

-0.1

-0.08

-0.06

-0.04

-0.02

0

0.02

-10 10 30 50 70 90 110 130 150 170 190

ns

ASDQ,Am,2800V

ASDQ,Am,3000V

ASDQ,Am,3200V

ASDQ,Am,3300V

CARIOCA, Am241, Average Discriminator Output, threshold 7fC

-0.35

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

-10 10 30 50 70 90 110 130 150 170 190

ns

CARIOCA,pos,Am,2800V




Cathode Pad


ShapingShaping

We are close to our goal of about 50ns pulse width. We are close to our goal of about 50ns pulse width.

The detector signal is well defined, therefore signal tail The detector signal is well defined, therefore signal tail cancellation is well defined 1/(t+1.5ns).cancellation is well defined 1/(t+1.5ns).

The difficult problem is preamp tail cancellation since the The difficult problem is preamp tail cancellation since the tail is different for positive/negative amplifier and it also tail is different for positive/negative amplifier and it also changes with the detector capacitance.changes with the detector capacitance.

For the final submission we have to optimize once more For the final submission we have to optimize once more the Shaper and BLR parameters (fine tuning).the Shaper and BLR parameters (fine tuning).


‘‘Instability’ Instability’

Output to Input CouplingOutput to Input Coupling


InstabilityInstability

For CARIOCA6, all channels went into coherent oscillation For CARIOCA6, all channels went into coherent oscillation for Capacitance >40pF.for Capacitance >40pF.

Connecting preamp AND dummy preamp to a capacitor Connecting preamp AND dummy preamp to a capacitor made the chip perfectly stable up to 220pF.made the chip perfectly stable up to 220pF.

We are faced with ground (or substrate) coupling and not We are faced with ground (or substrate) coupling and not with instability due to small phase margin of the chip.with instability due to small phase margin of the chip.

At 220pF, a 20uV ground signal will trigger the 5fC At 220pF, a 20uV ground signal will trigger the 5fC threshold !threshold !

Due to the large detector capacitance our life is very Due to the large detector capacitance our life is very difficult.difficult.


What causes the ‘instability’What causes the ‘instability’

We monitored the analog discriminator input signal on the probe station We monitored the analog discriminator input signal on the probe station and connected all 8 inputs to 220pF capacitance -> the board went into and connected all 8 inputs to 220pF capacitance -> the board went into oscillationoscillation

The ‘oscillation’ signal could be seen on the analog output.The ‘oscillation’ signal could be seen on the analog output.

Removing the 100 Ohm LVDS termination didn’t make a differenceRemoving the 100 Ohm LVDS termination didn’t make a difference

Removing the output bond wires from the chip didn’t make a differenceRemoving the output bond wires from the chip didn’t make a difference

Switching off the LVDS driver decreased the amplitude by about 20%.Switching off the LVDS driver decreased the amplitude by about 20%.

Switching off the discriminator (by raising the threshold) made the Switching off the discriminator (by raising the threshold) made the ‘oscillation’ disappear.‘oscillation’ disappear.

The discriminator switching is mainly responsible for the ‘instability’The discriminator switching is mainly responsible for the ‘instability’

The discriminator switching injects a signal to the preamp through a The discriminator switching injects a signal to the preamp through a voltage drop in the supply and ground lines across the wire bonds.voltage drop in the supply and ground lines across the wire bonds.


Cathode pad, CARIOCA8 positive, Am 3300V

Top: dummy preamp buffer output (47pF)Middle: averaged dummy preamp output (47pF)Bottom: discriminator Output

The discriminator switching causes a signal with 3mV peak -> 4.2 fC !!!


Symmetric TerminationSymmetric Termination

With symmetric termination the chip becomes less sensitive to this effect. Penalty: larger noise, but we can live with it !


CARIOCA6 resultsCARIOCA6 results Measured 2500+45e-/pF symmetric loading and 2500+32e-/pF asymmetric loading

threshold at 5 times noise:

Cdet thrsym thrasym

0 pF 2 fC 2 fC50 pF 3.8 fC 3.3 fC100 pF 5.6 fC 4.6 fC 150 pF 7.4 fC 5.8 fC200 pF 9.2 fC 7.1 fC250 pF 11 fC 8.4 fC

The difference in terms of minimum threshold is small, and in terms of stability the symmetric loading is much much better !


Full size prototype for M2R1Full size prototype for M2R1


Symmetric TerminationSymmetric Termination

CERN/RIO M2R1prototype with CARIOCA7 on a board produced in Cagliari. cathode pads: 42-55pF,dummy capactors on board (56pF),Single board

Setup is perfectly stable without any ‘special’ grounding or shielding (‘plug and play’). Testbeam with many boards in October.

Noise <1fC on the 16 measured channels

Idea looks promising and could make our life much much easier. Tests with large capacitance pads will be done later this year.


CARIOCA7 Chamber test with dummy capacitanceCARIOCA7 Chamber test with dummy capacitance (50pF cathode pads, 7fC threshold)(50pF cathode pads, 7fC threshold)

Result meets specification


‘‘Instability’Instability’

Using symmetric termination we can reduce common Using symmetric termination we can reduce common mode noise.mode noise.

We identified the discriminator switching as the source for We identified the discriminator switching as the source for the ‘instability’.the ‘instability’.

For the next submission we will use massive ‘on chip’ For the next submission we will use massive ‘on chip’ filtering of the discriminator power and ground lines in filtering of the discriminator power and ground lines in order to reduce this effect.order to reduce this effect.


Gain difference from specificationGain difference from specification

On CARIOCA6 and CARIOCA7 the positive amplifier On CARIOCA6 and CARIOCA7 the positive amplifier showed very strong nonlinearity at small charges.showed very strong nonlinearity at small charges.

The reason was a too small ‘feedback current’ that The reason was a too small ‘feedback current’ that put the amplifier on the very edge of the linear put the amplifier on the very edge of the linear range. This was solved by simply increasing this range. This was solved by simply increasing this current from 6 to 18uA.current from 6 to 18uA.


ConclusionConclusion

The LHCb muon system uses a large variety of detector The LHCb muon system uses a large variety of detector geometries.geometries.

In addition the specifications for the frontend performance In addition the specifications for the frontend performance are very tight (large Care very tight (large Cdetdet, High Speed, High Rate etc.)., High Speed, High Rate etc.).

With CAIOCA8 we have a prototype that seems not too far With CAIOCA8 we have a prototype that seems not too far from our final goal.from our final goal.

The final prototype has to be submitted in June 2003. The final prototype has to be submitted in June 2003.

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C ern A nd RIOC urrent A mplifier