C. Beigbeder Final design Review ECAL/HCAL Frond End FE board : current prototype Test results Qualification Clock adjustment Noise analysis FE board

Final design Review C . BeigbederC . Beigbeder

ECAL/HCAL Frond EndECAL/HCAL Frond EndFE board : current prototypeTest results

QualificationClock adjustmentNoise analysis

FE board : Final version Evolution Planning

Production testsTakaya and/or boundary scan Single board test to full-crate testSoftware aspects

Questions

Final Design ReviewFinal Design Review Sept 200Sept 20055

The FE board in the FE crate.The FE board in the FE crate.

250 boards including 250 boards including sparesspares

will be produced will be produced

366.7 mm366.7 mm

280mm280mm

25 x ‘9U‘ Crates25 x ‘9U‘ Crates


Block diagram of the FE Block diagram of the FE board.board.

M axC lu s te r

Serializ er2 1 /4

E x tC h an n e l 1 2 . . 4 & C o r n er

C h an n el 7 . .0 & C o r n er

J ta g

P o w e rSuppl i e s

L E ds

7 2

Serializ er2 1 /4

3 2C h an n el : 7 - 1 5 - 2 3 - 3 11 6

E x tC h an n e l 3 2 1 0

3 2D es erializ er2 1 /4 1 6

Sha p e r A D C1 2 bit s /4 0 M h z

Serializ er2 1 /4

T im in g Ad ju s tm en tS etu p

D elay ch ip

Ad a

ptat

ion

Del

ay li

n es

An a lo g I n p u tc o n n ec to r s

L 0 D a ta

T rigger D a ta

1 2 8

S iden eigh bou rsLVTTL

7 2

F E _ Pg a

I2C

S eq_P ga

N eig h b o u r sto p & b o tto m

T o C roc

T o V a lida tion2 1

V ersion 1 7 /01 /2 005

3 2 C ha nne lsfrom P m s

E ven tF orm ater

2 0

3 2 Tri g _ Pg a

L 0 & trig g e r da ta pro ce s s

7 2

I2C

Fifo S py

I2C

C om m an ds

2 1

C om m an ds

S e qu e n ce r

R e g u la to rs /D e la tch e r

G lu eL e ds

S ilico n Ex plo re r

Pro be

P robe

P robe

clo ck dis t ibu t io ne le m e n ts

E C S

Sp e c s

Fifo S py

I2C

I2C

8

C orner

Pro be O u tpu tM U X

D elay ch ip

Serializ er2 1 /4 T o V a lida tion2 1


Calorimeter FE board.Calorimeter FE board.


Details Details

Delay linesDelay lines

Analog chipAnalog chip

ADCADC

Delay chipDelay chip

FE_FE_PgaPga

Trig_PGA Trig_PGA

SeqSeq_Pga_Pga

GlueGlue_Pga_Pga

SerializersSerializers + +DeserializersDeserializers

Rad-hard regulatorsRad-hard regulators

Clock Clock Receiver/Receiver/driversdrivers

Analog inputAnalog inputconnectorsconnectors

JtagJtagconnectorconnector

LemoLemo(Probes)(Probes)


A zoom on the socket …A zoom on the socket …

Home-made socket :

FPGA BGA contact through golden foam ( no

soldering needed)


ECAL/HCAL FE CARD WITH

• 2 FEPGA

• 1 SEQPGA

• 1 GLUE PGA for ECS

on sockets.


Analog part.Analog part.

http://lhcb-calo.web.cern.ch/lhcb-calo/html/PRR/PRR_tobeprinted.dochttp://lhcb-calo.web.cern.ch/lhcb-calo/html/PRR/PRR_tobeprinted.doc

10 meters ( same for all )10 meters ( same for all )

On-detector clippingOn-detector clipping

Delay lineDelay line

BufferBuffer

Cable effect cancellationCable effect cancellation

Pedestal adjustment to ~128binsPedestal adjustment to ~128bins

P m

B uffe r In te gra tor

Vs s

Vd d

A na log C hip

B IC M O S 0.8 um Inte gra te d c irc u it 4 c ha nne ls pe r c hip

+

-

5 n s

5 0

6 5

2 7

4 5

1 2 M 3 3

3 7 1 0 0

3 3

3 3 0

3 .3 k1 .5 K

2 5 n s

11 0

2 2 n F

4 7 0 p F

2 7

2 2 n F

1 .0 7 k

A D C1 2 b its 4 0 M h z

4 p F

2 .7 k


Delay ChipDelay Chip

0,00E+00

5,00E-09

1,00E-08

1,50E-08

2,00E-08

2,50E-08

3,00E-08

0 5 10 15 20 25 30

Série1

Linéaire (Série1)

• Technology : AMS 0.8µm pure CMOS process in a 28 pin SOZ package• Half of the production has already been tested : yield is about 95%.• The power consumption is about [email protected].• The linearity is better than +/- 100ps per step. • The clock jitter is less than 15ps RMS for all channels.

http………http………


Fe PGAFe PGA

A D C d a ta 3

A D C d a ta 2

A D C d a ta 1

A D C d a ta 0

A ddC o u n te r/

L ate nc yo ffs e t /3 v

R d

A dd

L0 La te nc y R a mC irc u lar b u ffe r

F e_ P g a

T rig g er d a ta (1 6 b its @ 8 0 M hz )

L 0

W r

D ata

A dd

8 0

4 0 M hzC lock

I2 Cinte rfa c e C han 0 _ re g /3 v

C han 1 _ re g /3 v

V ersio n 17 /0 1 /2 00 5

D ata

R ea do u tS eq u en cer

C han 2 _ re g /3 v

C han 3 _ re g /3 v

S u b tra cto r

T riggerC a lib ra t ion

1 2 1 2

8

S u b tra cto r


1 2 1 2

8

S u b tra cto r


1 2 1 2

8

S u b tra cto r


1 2 1 2

8

2 0 L 0 D a ta

D e ra ndo m is e r1 6 de pth F ifo

T es tR AM

5 b lo c k s

1 21 2

1 21 2

T est seq u en ce

T es tC h an 3

S tatus

In terru p t

N T A

ad d

N eig hb ou rs d a ta (up to 3 2 b its@ 4 0 M hz )

L 0 F eR eset

W r R d

D a ta D a taFI FO /3 v

W r R d


W r R d


R d

W r R d


T es tC h an 2T es tC h an 1T es tC h an 0

T es tC h an 3

T es tC h an 2

T es tC h an 1

T es tC h an 0

I2 CP seud o P Msign a ls

sta rt

A ddC o u n te rtestm o de

testm o de

1 6 * 3

Spy F i fo


Actel Axcelerator Actel Axcelerator Match our needs in term of : Radiation tolerance & Latch up Match our needs in term of : Radiation tolerance & Latch up

Nb of IO pins, nb of cellsNb of IO pins, nb of cells Nb of Ram blocks for Latency and SpyNb of Ram blocks for Latency and Spy

……. And price : Ax 250 = 39,5 € . And price : Ax 250 = 39,5 € Ax 500 = 62,3 € + 2 € ( for programmation )Ax 500 = 62,3 € + 2 € ( for programmation )


ADC data processingADC data processing

G l o b a l C l o c k

V ersion 1 4 /0 6 /200 4

A D C d a ta

L0 D a ta

C k

D Q

C k

D Q

T r e sh

M u x

C k

D Q

+2 5 6

1 2

1 3firststa g e

a d d _ ech

+

M u xM i n

a d d er

1

0

1 2

C lk in v se l3 vreg

O ldsubm o de3 vreg

3 vreg

1

0

3

3 vreg

1 2 1 2

su b ra c to rsa t_ ech

S u b

S a t

C k

D Q

R

1 2

trig g er_ Ca lib

A

B

Sub_ z e r o

C a lib_ C t e3 vreg

A * B R o u n d& S a t

2 0 8

8 Trig g er D a ta

2 0

F E _ P g aL0 a n d tr ig g e r d a ta p ro ce s s in g p a r t : M o d u le S u b tra ct4 C lo ck cy cle s In p u t to O u tp u t

< 2 0 n s

C k

D Q

R

-2 5 6

3 vreg

1

0

T e st P a t t e r n

Test p a ttern d a ta

C k

D Q

R

C k

D Q

R

C k

D Q

R

1 2

C k

D Q

R

Clock adjustment study : see next talk Clock adjustment study : see next talk

Analysis of the 2 methods : see next talk Analysis of the 2 methods : see next talk


Front-end PGAs.Front-end PGAs.

R ea d ou tS eq u en cer

C irc ula rLa te nc yR a m

L0 d a taD e ra nd om ise rF ifo

p a ra m e te r_ re g

D a tap rocessin g

I2 Cin terfa ce

p a ra m e te r_ re g

L 0 d a ta

F e _ Pg a

2

F r on t E n d d a ta

T r ig g e r d a ta

R d

R ea d ou tseq u en cer &p a ri ty en cod er

D a tap roc e ss ing

E vt d a ta

T o C r oc

8 * 2 0

C ha n Bd ecod er

8Ev t I dco u n te r

B C idco u n te r

re s e t Ev t

re s e t B C

D e ra nd om ise rF ifo

R d

T e s t s e q ue nc e

I2 C

L 0 F e R e se t

L 0

T est pa ttern

L0

T e s t s e q ue nc e

L0 F e R e se t

I2 C

V ersio n 17 /01 /20 05

L 0Sequencer

L 0

PS S PD bitC i rcu l a rLa ten cyR a m

C pt A dd

Spy F i fo

Spy F i fo

C i rcu l a rLa ten cyR a m

I2 Cin terfa ce

2 1


Processing and formatProcessing and format

2 1

E vt & B c cou n terL 0 an d P s S p d d ata D e r a n d o m i s e r

FIFO

In 0In 1

In 9

M U X

w rfifo W r

rd fi fo

C k

D Q

C L

C k

D QFe P g a 0 20

P a r it y

C l o c k

EN

In p u t e n

C k

D Q

C L

C le a r o u tp u t re g

2 1

C k

D QFe P g a 7 20

P a r it y

C l o c k

EN

In p u t e n

T o C ro c

C l o c k

C l o c k

H o rizo n ta l P a rity

S e l m u x

078151617181920

BX - Id L0 - Id

Pari

ty

PRS/

SPD

Cal

ib.

Tes

t Se

q .

PRS/

SPD

Channel 8

Channel 4

Channel 0

Header

Separator

Separator

Trailer (Vertical Parity)

Channel 31

[É ]

0É0É

É 0É 0

011121920

Par

ity

Data ECAL/HCALTrigger ECAL/HCAL

Parity

Line i

Channel

4x ( ( i - 1 ) modulo 8 ) + int ( ( i Ğ 1 ) / 8 )

Line 1É


SeqPGA : sequencer partSeqPGA : sequencer part

C lo c k

L 0 e c h

R d C m d

L 0

n _ R d fifo

n _ W r fifo

fifo e m p ty

S e q d isa b le

n _ F e _ w re n a b le

se l M u x 0

se l M u x 1

c p t b o u c le

se l M u x 2

se l M u x 8

0

se l M u x 9

c le a r o u tp u t re giste r

3

Fe data Fe data Fe data Fe data

HeaderHeader

TrailorTrailor

2 words = to zero as separator2 words = to zero as separator


Triple voting FIFO Triple voting FIFO (derandomizer)(derandomizer)

R a m

W r A d ress

C lock

5 A d d 0

3 v c ounte rR d A d ress

5

C lock

R d f ifoS yn ch reset

C lock3 v c ounte r

W r f ifo E n a b l e

C lock

S yn ch reset

F ro n d E n d R eset

E n a b l e

A d d 1

A d d 3 1

C ounte rW r f ifo E n a b l e

C lock

S yn ch reset

F ro n d E n d R eset

C ounte rE n a b l e S yn ch reset

C ounte rE n a b l e S yn ch reset

3 V o tin g o u tp u t


Glue PGAGlue PGA

C tr l l ine

8 b D ata l ine

S LA V E _ R E C E IV E R

SP E C S C l o c k r e c e i ve rr e g i o n

I2 C _ 1

J TAG

I 2 C _ O UTPUT

SP E C S_ B U S

J TA G _ O UTPUT

S LA V E _R E G IS T E R

M U X J T A GE X P LO R E R

I2 C _ 2

S LA V E _ D A T A _ C T R L

SP E C S w o r d E m i t te r

SL AVE E m i tte r C TR L

SP E C S C l o c k e m i t te rr e g i o n

F IF O

JTA

G E

XP

LO

RE

R

JTA

G F

PG

A

L ED SC O NTR O L

R C _ L E D

L E D S

SP E C S_ B U S


L0 calorimeter triggerL0 calorimeter trigger

Detector + PM8x4 cells/FE card

10 m cables

80 m optical link

Selection Crate

Pla

tform

on

top

of ca

lorim

ete

r

LVDS links

14 ECAL crates 4 HCAL cartes 8 Prs/SPD crates 8 cards per half crate

FE

FE

FE

FE

FE

FE

FE

FE

Ba

rrack

LVDS links

L0 Decision Unit

80 inputs

TotalEnergy

FE

FE

FE

FE

FE

FE

FE

FE

HighestElectron

HighestPhoton

ECAL HCAL

HighestHadron

SecondHighest

Highestlocal

80 linksfrom 50 cards

8 inputs 4 inputs

28 inputs

4 outputs

One Validation card per half ECAL crateOne SPD sum perhalf PreShower crate

FE

PreShower / SPD

AddressFE

FE

FE

Validation Card

LUT

highestelectron

highestphoton

28 inputs

highest

local

28 inputs

LUT

Level 0 Decision Unit

8 inputs x 8 bits

Merge back to 50

address match

highest

Highest global

highest

global

28 inputs

E TOT

8 inputsSPD

multiplicity

Add

16 inputs

SPDmultiplicity

Add


TrigPGA : block diagramTrigPGA : block diagram

1 2 8

(1 6 x 8 ) @ 4 0 M h z1 2 8

(1 6 x 8 ) @ 4 0 M h z

1 2 8

(1 6 x 8 ) @ 8 0 M h z

3 2 CH A NE LSF E B

8 S ID ENE IG H B O U R S

4 U P S ID ENE IG H B O U R S

1 CO R NE R

6 4

(8 x 8 ) @ 4 0 M h z

3 2

(4 x 8 ) @ 4 0 M h z

8

(1 x 8 ) @ 4 0 M h z

3 V R e g _ 0

RAM _D e l ay_0

3 V R e g _ 1

3 V R e g _ 2

3 V R e g _ 3

H i g he s t s umand

To tal e ne r g yc o m pute

H ig hest sum

A dress h igh est sum

T o ta l en erg y8

8

5

SpyF IF O

I2 C

B X ID cp t reset

Ad ju s ta b le p ip elin e

RAM _D e l ay_1Ad ju s ta b le p ip elin e



I2C

I2C

I2C

I2C

V ersion 04 /02 /2005

R e -S y n c

R e -S y n c

R e -S y n c

T est Seq uence

(F R O M S eq_P G A )

BX IDCpt

R eg isters


TrigPGA : mappingTrigPGA : mapping

E c e lla d d e r

32 sum outputs

45 sum inputs

E [ 44 :0]

S[ 31 :0]

E t 0

E t 1

8

8

32 S a tu ra te d2* 2 S u ms

E t 2

E t 3

8

8

8

S at0

S at1

S at2


TrigPGA : internal latencyTrigPGA : internal latency

D a taco m p u tin g

h ig h est su m

a d ress h ig h est su m

to ta l en erg y

Su m 4

Su m 5

CLK

8

5

85

CLK

858

5

85

CLK

8

5A d d r_ H ig est_ S u mH ig est_ S u m

85

85

S u m 4

S u m 5

1 0 A d d er

F i rs t S tag e

8

C L K

8

5 A d d er

S eco n d S tag e

8

3A d d er

T h i rd S tag e 1 A d d er

F o rth S tag e1

A d d erF o rth

L as t S tag e

8

C L K

8

8

C L K

8 T o ta l en erg y8

1 C lo ck C ycle 1 C lo ck C ycle 1 C lo ck C ycle

Ad d er 8 b itsL es s th en 5 n s in AX 5 0 0 w ith

Ac te l M ac r o g en er a to r , S td s p eedA d d er sta g e w ith in 1 B C .

C o m p are+ M u xF i rs t S tag e

C o m p are+ M u xS eco n d S tag e C o m p are+ M u x

T h i rd S tag e C o m p are+ M u x

F o rth S tag e C o m p are+ M u xL as t S tag e

V ersio n 0 7 /0 2 /2 0 0 5


Clock distribution Clock distribution

D es erializ er2 1 /4

C om m onB ackp lan e

N eig h b o u r sto p & b o tto m

V ersion 9 /0 2 /200 5

An al ogIn pu tB l ock

D e lC h i p

D elayC h ip

9 0L V 0 4 7

9 0L V 0 4 7

9 0L V 0 4 7

Serializ er2 1 /4

8 F e pg a _ B lo c k s

F e pg a_ bl o c k

P m t e st P ulse

9 2L V 0 1 0

8 L V D S dif C lo ck s1 6

S e ria lCk 0

S e ria lCk 1

A d jCk 1

G lo b a lCk

T rig _P ga

9 0L V 0 4 8

1 L V D S dif C lo ck

C k

D Q2 1

C lock f ro m seria lizer

G lob a l clo ck

E cs R d R eg ister

S eria l D ata

A d ju sted C lock

C loc k from C roc

C o m m an d s

C k

D Q

C k

D Q

E cs

2 1 + C lo ck

2 1

L v 0 1 0

P L L

F e p g a

P L L

P L L

S eqpg a

P L L

G lu eI 2 C

Multi-drop analysisMulti-drop analysis

Unidirectionnal multi-load analysisUnidirectionnal multi-load analysis


+ 3 .3 V F u se

c te

F au lt

In

M ax 869

+ 3 .3 V _ F ep g a 3 to04 9 1 3

R e g ula tor

O n

Vc ore _ F e p g a 3 to0 (1 .5 v )

F au lt

In

M ax 869

+ 3 .3 V _ F ep g a 7 to44 9 1 3

R e g ula tor

O n

Vc ore _ F e p g a 7 to4 a nd T r ig g e r_ p g a (1 .5 V)

F au lt

In

M ax 869

+ 3 .3 V _ G lu e 8 S eq

O n

4 9 1 3R e g ula tor

Vc ore _ A p a ( 2 .5 v )

-5 V F u se7 9 1 3

R e g ula tor

F u se4 9 1 3

R e g ula tor

+ 5 V

In terru p t

In terru p t

C om m on sign a l to specs in terru p t

V a d c+ 3 .3 V _ g lu e com p on en ts ( seria l i zer , d ela y chip .. .)

A na log + 3 VA d 8 042 V 1 sh aper

A d 8 042 V 2 sh aper

A na log -4 V

C lerm on t

Power distributionPower distributionBoard Consumption : Board Consumption : +5 V = 4A+5 V = 4A+3.3V = 2 A+3.3V = 2 A-5V = 1 A-5V = 1 A


FE board : new version FE board : new version SeqPGA and Glue in ProAsic 300 and 150.

New version of ProAsic has been qualified by Actel and NASA and matches our requirements. Time schedule makes very difficult a complete change of all PGAs :

Only PGAs interfacing with the board’s outside are changed : Seq and Glue. But TrigPGA would thus have to be redesigned because of the lower performance of the ProAsic.

ProAsic 150 = 30 €ProAsic 150 = 30 €ProAsicProAsic 300 = 66 €300 = 66 €


FE board : new version FE board : new version

New design of the analog input part : Analog test signals will be routed carefully within the ground plane. F125 located closer to the shaper.

New version of the handshake FePGA-SeqPGA. Depending on future noise analysis results, the 8 FePGA may send

data one after the other instead of all together. Current peak may thus be avoided.

Evolution of the connectors. Use of another AB type connector on the 6U backplane (see Daniel’s

talk).


Programming-debugging : JTAG Programming-debugging : JTAG ChainChain

2 J ta g ch a in s : A x celera to r a n d P ro A sic

D ed ic a ted J tag p in s D ed ic a ted J tag p in sT C K T D I T D OT M S T C K T D I T D OT M S

G lu e p g aA P A 1 5 0

S eq p g a

A P A 1 5 0

IS P ( P roA sic p rogram m in g C on n ecto r )

A xcelera torjtag con n ecto r

F e p g aA x 2 5 0

D ed icat ed J t agp in s

T ckT m s

T d i

T d o

T C K

T M S

T D I

T D O

T D I

TD I<n >

T D O

TD O <n >

TD O <n -1 >T D I

T D O

Tr igA x 5 0 0

T ckT m sT d i

T d o

T C K

T M S

T D I

T D O

T D I

T D O

T C K

T M S

Lem o

D ed icat ed J t agp in s

Prob e s

' h om e-m ade 'P robes

Prob e s

P rogram m ab le

E C S


ProductionProduction Manufacturer will perform an aging of 16 boards in the same crate.

• Goal : Detection of bad soldered components. Boundary Scan:

• Ability to drive 2 chains independently.

• GluePGA has to be programmed first.

• Test of Actels’ interconnections. ‘ Takaya ‘ test :

• Impedance value and

interconnection.

• Bad soldered chips with ‘open

checker’.

• Needs a plug to test connectors.

• Footprints for probes have to

be foreseen.


Final layout Final layout

• Thickness : 2.4 mm.Thickness : 2.4 mm.• 12 layers12 layers• Minimum isolation : 0.11mmMinimum isolation : 0.11mm• Via : width = 0.35 mmVia : width = 0.35 mm• Plating : Ni-Au for BGAsPlating : Ni-Au for BGAs

• 2845 components2845 components• 3464 nets3464 nets• 15400 pins 15400 pins • ~10000 connections~10000 connections• 6072 vias6072 vias


Some layers … Some layers …


FE board production FE board production schedule.schedule.

Public call for tender February 15th ( Yes !!! ).

=> May 1st ( 51days + 4 weeks) : notification. June 10th : arrival of the two first boards ( 5 weeks ) => 7 weeks

for the thorough test. July 27th : decision based on the boards’ characterization

Not OK => two new prototypes ( 4 weeks + 3 weeks test + holidays) OK => 16 boards to equip a full crate : ( 3 weeks + holidays)

October 7th : beginning of production. Mid November : 40% of production. End of December : end of production. November to June : Reception test Installation : from December 2005 to July 2006 ( together with

CROC and Crate).

Documents

C. Beigbeder Final design Review ECAL/HCAL Frond End FE board : current prototype Test results Qualification Clock adjustment Noise analysis FE board