By: Vivek Ganti ([email protected]) Reg. No. 71368 UNITED ... · Petition for Inter Partes Review of U.S. Pat. No. 5,987,604 F. Ground 6: Collins, the Pentium Manual and the Intel Architecture

By: Vivek Ganti ([email protected]) Reg. No. 71368 Gregory Ourada ([email protected])

Reg. No. 55516

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

_________________

AMERICAN MEGATRENDS, INC., MICRO-STAR INTERNATIONAL CO., LTD,

MSI COMPUTER CORP., GIGA-BYTE TECHNOLOGY CO., LTD., AND

G.B.T., INC. Petitioners

v.

KINGLITE HOLDINGS, LLC

Patent Owner

_________________

Case IPR2015-TBA U.S. Patent No. 5,987,604

_________________

PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 5,987,604

Mail Stop PATENT BOARD Patent Trial and Appeal Board U.S. Patent & Trademark Office P.O. Box 1450 Alexandria, VA 22313-1450

mailto:[email protected]

mailto:[email protected]

Petition for Inter Partes Review of U.S. Pat. No. 5,987,604

TABLE OF CONTENTS Page

TABLE OF AUTHORITIES .................................................................................. iii

EXHIBIT LIST .......................................................................................................... v

I. Introduction ........................................................................................................ 1 II. Overview ............................................................................................................ 1 III. Mandatory Notices (42 C.F.R. 42.8(a)(1)) ...................................................... 11

A. Real party-in-interest (42 C.F.R. § 42.8(b)(1)) ........................................... 11 B. Notice of related matters (37 C.F.R. § 42.8(b)(2)) ................................... 12 C. Notice of Counsel and Service Information (37 C.F.R. § 42.8(b)(3-4)) ... 13

IV. Grounds for Standing ..................................................................................... 13 V. Statement of Relief Requested ....................................................................... 14 VI. Claim Construction ........................................................................................ 14

A. Applicable Principles of Claim Construction ........................................... 14 B. Level of Skill in the Art ............................................................................. 15 C. Terms to be Construed ............................................................................... 15

1. “Protected mode” .................................................................................. 15 2. “System management mode (SMM)” .................................................. 17 3. “Virtual mode” ..................................................................................... 17 4. “Paging” ............................................................................................... 19

VII. Identification of Challenge (37 C.F.R. § 42.104(b)) ...................................... 20 A. Ground 1: The combination of Collins and the Pentium Manual

renders obvious claims 1-4, 11-14, and 21-24 ...................................25 B. Ground 2: Collins, the Pentium Manual and the IBM 6x86 Manual

renders challenged claims 1-4, 11-14, and 21-24 obvious .................34 C. Ground 3: Challenged Claims 1, 11, and 21 are obvious under 35

U.S.C.§ 103(a) in light of the combination of Favor and the Am486 Manual. ...............................................................................................36

D. Ground 4: The Am486 Manual in combination with the IBM 6x86 Manual renders claims 1, 11 and 21 obvious .....................................43

E. Ground 5: Wooten 1 anticipates claims 1-2, 11-12 and 21. ..............45

i


F. Ground 6: Collins, the Pentium Manual and the Intel Architecture Software Developer’s Manual render claims 5-10, 15-20 and 25-30 obvious ...............................................................................................51

G. No Secondary Conditions Exist .........................................................58 Fees .........................................................................................................................58 Conclusion .............................................................................................................58

ii


TABLE OF AUTHORITIES Page

CASE LAW

United States Supreme Court Graham v. John Deere Co., 383 U.S. 1 (1966) ................................................ 25, 26 KSR v. Teleflex, 550 U.S. 398, 420 (2007) ........................................... 15, 27, 34, 36 Federal Circuit Court of Appeals CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002) ........... ........................................................................................................................ 14, 15 In re Kahn, 441 F.3d 977, 987-88 (Fed. Cir. 2006) .................................................26 Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d 1243, 1249 (Fed. Cir.

1998) .....................................................................................................................15 USPTO, Patent Trial and Appeal Board CBM2012-00003, Paper 7 .......................................................................................25 IPR2012-00001, Paper 59 ........................................................................................37 STATUTES 35 U.S.C. § 102 .................................................................................................. 1, 22 35 U.S.C. § 102(a) .............................................................................. 22, 23, 24, 36 35 U.S.C. § 102(b) ............................................................................... 22, 23, 24, 36 35 U.S.C. § 102(e) ...................................................................................... 23, 24, 36 35 U.S.C. § 103 ....................................................................................... 1, 25, 37, 43 35 U.S.C. § 103(a) ...................................................................................... 21, 22, 36 35 U.S.C. § 314(a) ..................................................................................................58 FEDERAL REGULATIONS 37 C.F.R. § 42.1(b) ........................................................................................... 24, 25 37 C.F.R. § 42.6(d) ..................................................................................................20 37 C.F.R. § 42.8(b)(2) ..............................................................................................12 37 C.F.R. § 42.8(b)(3-4) ..........................................................................................13 37 C.F.R. § 42.10(b) ................................................................................................13 37 C.F.R. § 42.15(a) .................................................................................................58

iii


37 C.F.R. § 42.100(b) ..............................................................................................14 37 C.F.R. § 42.103 ...................................................................................................58 37 C.F.R. § 42.104(b) ..............................................................................................20 37 C.F.R. § 42.104(b)(3) ..........................................................................................14 42 C.F.R. § 42.8(a)(1) ..............................................................................................11 42 C.F.R. § 42.8(b)(1) ..............................................................................................11

iv


EXHIBIT LIST

Ex. 1001 United States Patent No. 5,987,604 (“604 Patent”)

Ex. 1002 U.S. Pat. No. 5,644,755 (“Wooten 1”)

Ex. 1003 U.S. Patent No. 6,093,213 (“Favor”)

Ex. 1004 Enhanced Am486 Processor Manual (May 1995) (“Am486 Manual”)

Ex. 1005 Pentium Processor Family Developer’s Manual Vol. 3: Architecture and Programming Manual (1995) (“the Pentium Manual”)

Ex. 1006 “The Caveats of Pentium System Management Mode,” by R. Collins, Dr. Dobbs, May 1, 1997 (“Collins”)

Ex. 1007 U.S. Patent No. 5,544,344 (“Frame”)

Ex. 1008 U.S. Patent No. 5,832,299 (“Wooten 2” or “the 299 Patent”)

Ex. 1009 U.S. Patent No. 7,444,500 (“Jones”)

Ex. 1010 Excerpt from Prosecution History of U.S. Patent No. 7,444,500

Ex. 1011 Excerpts from Barron’s Dictionary of Computer Terms (3d ed. 1992)

Ex. 1012 IBM 6x86 MICROPROCESSOR Sixth-Generation Superscalar Superpipelined x86-Compatible CPU (February 1996) (“the IBM 6x86 Manual”)

Ex. 1013 Intel Architecture Software Developer’s Manual Volume 3: System Programming Guide (1996, 1997) (“ASDM”)

Ex. 1014 Declaration of Feliks Polyudov

Ex. 1015 Declaration of Vivek Ganti

v


I. Introduction

American Megatrends, Inc., Micro-Star International Co., Ltd, MSI

Computer Corp., Giga-Byte Technology Co., Ltd., and G.B.T., Inc. (“Petitioners”)

petition for inter partes review seeking cancellation of claims 1-30 of U.S. Pat. No.

5,987,604 (“the 604 Patent,” Ex. 1001), which is assigned to Kinglite Holdings,

LLC (“Kinglite”). Kinglite is referred to as “Patent Owner” in this Petition.

II. Overview

This Petition furthers the purpose of inter partes review – the cancellation of

unpatentable claims. The challenged claims of the 604 Patent never should have

issued. This Petition establishes a reasonable likelihood that Petitioner will prevail

regarding the claims challenged and that the challenged claims are unpatentable

under pre-AIA 35 U.S.C. § 102 and § 103. Thus, Petitioner respectfully requests

that the Board grant the Petition and institute trial on the challenged claims.

The 604 Patent issued on November 16, 1999, and claims priority to October

7, 1997. (Ex. 1001, p.1). It describes a system for executing instructions while in

system management mode (SMM). The apparatus has memory for storing

instruction sequences including a system management random access memory

(SMRAM). There is also a processor having a system address space, executing

stored instruction sequences. The stored instruction sequences cause the processor

1


to: (a) configure the processor to operate in a protected mode while in SMM, the

processor operating at an address greater than one megabyte; (b) invoke a paging

feature of the processor; (c) configure the processor to operate in a virtual mode;

and (d) process the instruction sequences, wherein these steps occur upon the

receipt of a system management request instruction. (Ex. 1001, p.1, Abstract).

The 604 Patent employs the familiar architecture of an x86 processor, which

was known in the prior art to include four modes: real mode, protected mode,

virtual mode, and SMM. Real mode is a standard user mode for running 16-bit

instruction programs, in which an 80286, 80386 or 80486 processor acts as an

older generation 8088 or 8086 processor. (Ex. 1011, p.4; Ex. 1014, p.8, ¶24).

SMM programs in the prior art were known to use real mode 16-bit code. (Ex.

1014, p.12, ¶34). As is known in the art, 16-bit programs are intrinsically limited

to using the first 1 MB of system memory, of which only 640k is available to user

programs. (Ex. 1011, p.4; Ex. 1014, p.8-9, ¶¶24-25). “An 8086 program may

generate linear addresses anywhere in the range 0 to 10_FFEFH (1 megabyte plus

approximately 64K bytes) of the linear address space.” (Ex. 1005, p.256).

With the advent of the x286 processor, protected mode was added to execute

32-bit instruction code (but not 16-bit code), expanding memory reach from 1 MB

to 4 GB. (Ex. 1011, p.3; Ex. 1014, p.9, ¶26). In the x286 processor, which

included real mode and protected mode, after configuring the processor to operate 2


in protected mode, it could not return to real mode unless the computer was reset.

(Ex. 1014, p.9, ¶27). The 386 processor added virtual mode, also called “virtual-

8086” or “v86” mode, to more support the operation of 16-bit programs within a

32-bit processing platform (protected mode). (Ex. 1011, p.5; Ex. 1014, p.9, ¶28).

Specifically, if a processor was running a 32-bit program in protected mode and a

16-bit program was selected, protected mode could enable paging to “virtualize

addresses” and emulate an 8086 processor running 16-bit code in real mode. (Ex.

1011, p.5; Ex. 1014, p.10, ¶30). This emulation process would effectively cause

the program to assume that it was being run on an 8086 or 8088 processor. Id.

The 604 Patent further explains that SMM is well-known in the art.

“Modern computers based on the personal computer architecture may perform

power management or other system management functions by employing an

operating mode of the Intel x86 family of microprocessors, known as the System

Management Mode (SMM).” (Exhibit 1001, p.13, 1:14-18). “SMM can be used

by the system firmware to control product-specific hardware features in a manner

which is transparent to the operating system and applications software.” Id. 1:18-

21. “SMM is used to implement intelligent power management and other

enhanced system functions in firmware in a manner which is completely

transparent to the operating system and applications software.” Id. p.14, 3:16-20.

3


In the prior art, the 604 Patent recites that the SMM is invoked through a

system management interrupt (SMI), which executes slowly, as compared to the

rate of normal code execution. Id. p.13, 1:26-28. This is because SMIs typically

operate below the 1 MB boundary in an uncached memory area, a characteristic of

16-bit programs operating in real mode. Id. at 1:28-29. The object of the invention

is to allow for faster operation of an SMM program by permitting code execution

in protected mode, above the 1 MB boundary. Id. at 1:31-52.

To accomplish its object, the 604 Patent creates a virtual monitor that runs

under the SMM with memory paging enabled (a standard feature in x86 processors

of the prior art) to execute SMI code in virtual mode. As noted, in real mode, the

support for 16-bit instructions does not permit execution of code above the 1MB

limit. (Ex. 1014, p.8-9, ¶¶24-25). Conversely, protected mode and virtual mode

each run applications on a 32-bit instruction platform, permitting execution of code

at up to 4 gigabytes (GB) of memory. Id., p.9, ¶26 and p.10, ¶30.

Because virtual mode supports programming in 32-bit code in the x486

processor, virtual mode allows SMM code which would otherwise run below 1 MB

to execute above the 1 MB boundary. In particular, an SMM program (often called

an SMI handler) is mapped above the 1 MB boundary and power management

code is executed as a page-enabled, protected mode virtual task within SMM. (Ex.

1001, p.13, 2:27-35). 4


Figure 7A describes the instruction process underlying the ‘604 Patent:

(Ex. 1001, p.11.)

In the foregoing diagram, the CPU, in response to an SMI, asserts the

SMIACT control signal, which accesses SMRAM. SMRAM is a memory space

dedicated to SMM, i.e., the operating system and applications software do not have

access to this space. (Ex. 1001, p.14, 3:21-27.) The then-current CPU state

5


(context) is stored in SMRAM after assertion of the SMIACT signal and the CPU

then jumps to a location in SMRAM to execute the SMI handler code for

performing system management activities. Id. at 3:27-31. Upon completion of

system management activities, the SMI handler executes a resume (RSM)

instruction which restores the CPU’s context from SMRAM, de-asserts the

SMIACT signal, and then returns control to the previously interrupted operating

system or application program execution. Id. at 3:31-36.

As discussed in greater detail below, processor manufacturers such as

Advanced Micro Devices (AMD), Intel and IBM published product literature in

the prior art which generally teaches transitioning between SMM and all three user

modes (real, protected and virtual) in an x86 processor architecture. Likewise,

these manuals teach moving from real mode to protected mode to virtual mode,

and vice-versa. Protected mode and virtual mode, unlike real mode, are associated

with accessing user program instructions above the conventional 1 MB memory

limit. The following is an excerpt from an AMD manual in 1995, two years before

the application leading to the 604 Patent was filed:

6


(Ex. 1004, p.44) (emphasis added).1 “PE=1” signifies that the processor has

enabled protected mode. (Ex. 1014, pp.10-11, ¶31). Next, the foregoing figure

shows enabling virtual mode (VM=1). Id., p.46-48, 51-52, 54 and 60-61, ¶¶ 137,

148, 152 and 169.

In addition to the foregoing figure, the prior art establishes that when an SMI

occurs, the handler program operating in SMM can configure processor to operate

in protected mode (PE=1) while the processor remains in SMM. An AMD-owned

patent having a priority date of Oct 6, 1995 for the flexible implementation of

SMM states that “While SMM 900 is active, all x86 architectural features and

1 See also Ex. 1005, p. 499-500 (identical figure in Pentium Manual). 7


instructions are available for use in addition to a set of SMM support instructions.”

(Ex. 1003, p.31, 33:23-42) (emphasis added).

In furtherance of this point, an IBM Manual from 1996 states that "Within

the SMI service routine, protected mode may be entered and exited as required,

and real or protected mode device drivers may be called." (Ex. 1012, p.95 at

§2.9.5) (emphasis added). Likewise, in “The Caveats of Pentium System

Management Mode,” by R. Collins, Dr. Dobbs, May 1, 1997 (“Collins”, Ex. 1006),

under the heading “Using Protected Mode within SMM,” it states that “SMM [is] a

completely separate x86 CPU state within a CPU. In that regard, it is orthogonal to

all other operating modes” and that the “processor is capable of entering protected

mode, v86 [virtual] mode…if the SMM handler was programmed to do such a

thing (although it probably wasn’t).” (Ex. 1006, p.4) (emphasis added). Collins

sets forth that it was known in the prior art to configure a processor for protected

mode and virtual mode while in SMM, the sine qua non of the 604 patent.

Another Intel software developer’s manual for Intel’s x86 and Pentium

processors gives a specific example in furtherance of the entry into protected mode

while in SMM. “In some instances (for example prior to powering down system

memory when entering a 0-volt suspend state), it is necessary to save the state of

the FPU while in SMM. Care should be taken when performing this operation to

insure that relevant FPU state information is not lost. The safest way to perform 8


this task is to place the processor in 32-bit protected mode before saving the FPU

state.” (Ex. 1013, p.347 (emphasis added)).

Understanding that the processor can be in SMM while PE=1 (protected

mode enabled), the import of the foregoing figure 27 at 7, supra, is that while in

SMM with PE=1, the processor is also configured to enter virtual mode (VM=1),

whereupon the processor can run 16-bit programs without the necessity of

reverting to real mode. The prior art shows that when SMM is invoked, the

processor transitions to an SMM mode of operation, which is similar to a real

mode. (Ex 1013, pp.337-338, 344-345 at §11.1 and 11.5); Ex. 1006, p.4). Since

CPU operation in SMM mode is very similar to CPU operation in real mode, all

mode transitions described in the Intel, AMD, and IBM references apply with

equal force to SMM mode and real mode. (See also Ex. 1003, p.31, 33:23-42:

“While SMM 900 is active, all x86 architectural features and instructions are

available for use in addition to a set of SMM support instructions.” (emphasis

added).)) Applying these precepts to the figure shown at 7 supra (see Ex. 1004,

p.44) leads to extending the figure as per the following diagram to reflect that the

same CPU mode transitions can be done inside and outside of SMM:

9


(Ex. 1014, pp.46-48 ¶137).

Likewise, the notion of running SMM code from SMRAM in protected

mode (i.e., above the 1 MB limit) was well-known in the art. “An SMM program

can execute all I/O and other system instructions and can address up to 4 Gbytes of

memory.” (Ex. 1005, p.500) (emphasis added). The same source teaches

“relocating SMRAM to a location above 1Megabyte.” Id., p.507 at §20.1.6.4; see

also Ex. 1013, p.350 at §11.11.1 (same). Another prior art reference likewise

teaches that “in DOS compatible systems, … SMRAM [can] be located beyond the

first megabyte of addressable memory space.” (Ex. 1007, p.6, 1:28-34) (emphasis

added).

This petition introduces references describing prior art AMD, Intel and IBM

processors to show that the invention of the 604 Patent is merely an obvious

deployment of x86 processor features. Other prior art will also be introduced to

show that the challenged claims of the 604 Patent were anticipated.

10


Feliks Polyudov, a technical expert in this field for almost twenty years,

explains how each of these prior art documents disclose, teach and otherwise

suggest every feature of the challenged claims, why the features described in the

challenged claims were obvious – memory, processor, mode-switching

capabilities, including operating an SMI handler in SMM and protected and virtual

modes -- to a person having ordinary skill in the art (“POSITA”) as of October 7,

1997. (Ex. 1014). As Mr. Polyudov explains, the 604 Patent merely takes

advantage of the known microprocessors, modes and memory conventions of the

time. Id., p.18, ¶57; see, e.g., Ex. 1004, describing the Enhanced AMD 486

microprocessor in 1995; Ex. 1005, showing the architecture of the Pentium

processor in 1995, and Ex. 1012, showing the architecture of the IBM 6x86

microprocessor. Moreover, the specific technique of the 604, entering protected

mode while in SMM and then transitioning to virtual mode to run SMI handler

code, is taught in prior art references such as Collins. (Ex. 1006, p.4). In view of

the evidence, the Board should cancel all of the challenged claims.

III. Mandatory Notices (42 C.F.R. 42.8(a)(1))

A. Real party-in-interest (42 C.F.R. § 42.8(b)(1))

The real parties in interest are:

11


• American Megatrends, Inc. (American corporation, principal place of

business in 5555 Oakbrook Parkway, Norcross, Georgia 30093)

• Micro-star International Co., Ltd (Taiwanese corporation with its

principal place of business at No. 69, Lide Street, Zhonghe District,

New Taipei City 235, Taiwan)

• MSI Computer Corp (American corporation with its principal place of

business at 901 Canada Court, City of Industry, California 91748)

• GIGA-BYTE Technology Co., Ltd. (Taiwanese corporation, principal

place of business at No.6, Bao Chiang Road, Hsin-Tien Dist., New

Taipei City 231, Taiwan)

• G.B.T, Inc. (American corporation, principal place of business in

17358 Railroad St, City Of Industry, CA 91748)

B. Notice of related matters (37 C.F.R. § 42.8(b)(2))

The 604 Patent is presently asserted against Micro-star International Co., Ltd

(“Micro-Star”) and MSI Computer Corp (collectively, “MSI”) in the District Court

for the Central District of California (CV 14-03009 JVS (PJWx)). The 604 Patent

is also presently asserted against GIGA-BYTE Technology Co., Ltd. (“GIGA-

BYTE”) and G.B.T, Inc. (collectively, “GBT”) in the District Court for the Central

District of California (CV 14-04989 JVS (PJWx)). MSI and GBT are both

customers of American Megatrends Inc. (“AMI”). AMI intervened in these two

12


district court cases and the district court consolidated the cases. The owner of the

604 Patent then asserted it directly against AMI.

C. Notice of Counsel and Service Information (37 C.F.R. § 42.8(b)(3-4))

Lead Counsel: Vivek Ganti (Reg. No. 71,368)

Address: HILL, KERTSCHER & WHARTON, LLP, 3350 Riverwood

Parkway, Suite 800, Atlanta, GA 30339. Tel. 678.384.7453. Fax. 770.953.1358.

Backup Counsel: Gregory Ourada (Reg. No. 55516)

Address: HILL, KERTSCHER & WHARTON, LLP, 3350 Riverwood

Parkway, Suite 800, Atlanta, GA 30339. Tel. 678.384.7443. Fax. 770.953.1358.

Please address all correspondence to the lead counsel at the address shown

above. Petitioner consents to electronic service by email at: [email protected].

Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney by Petitioner

appointing each of the above designated counsel is concurrently filed.

IV. Grounds for Standing

Petitioner certifies that the 604 Patent is eligible for inter partes review.

Petitioner is not estopped or barred from requesting inter partes review to

challenge the claims identified in the Petition. The required fee is paid via online

13


credit card payment. The Office is authorized to charge fee deficiencies and credit

overpayments to Deposit Account No. 506541 (Customer ID No. 87296).

V. Statement of Relief Requested

Petitioner requests inter partes review and cancellation of claims 1-30 of the

604 Patent based on the detailed statements presented in Sections VI and VII.

VI. Claim Construction

A. Applicable Principles of Claim Construction.

Unless otherwise noted, all claim terms employ their plain and ordinary

meanings. The Board should construe these claims using the broadest reasonable

interpretation (“BRI”). See 37 C.F.R. § 42.100(b). Petitioner proposes BRI-based

constructions of terms herein solely for purposes of the inter partes review (“IPR”)

proceeding as provided by 37 C.F.R. §§ 42.100(b) and 42.104(b)(3). The BRI-

based standard is not used in litigation or other proceedings, and on that basis

Petitioner notes that these constructions are not necessarily appropriate for use in

litigation or any other proceedings which employ a standard of claim construction

other than BRI.

There is a “heavy presumption” that a claim term is entitled to its ordinary

meaning as understood by a POSITA. CCS Fitness, Inc. v. Brunswick Corp., 288

14


F.3d 1359, 1366 (Fed. Cir. 2002). A POSITA is presumed to be aware of all

pertinent art, thinks in accordance with the conventional wisdom of the art, and is a

person of ordinary creativity. See KSR v. Teleflex, 550 U.S. 398, 420 (2007).

An inventor may act as his or her own lexicographer, but to do so, the

definition must be set forth in the specification with reasonable clarity,

deliberateness, and precision. See Renishaw PLC v. Marposs Societa’ per Azioni,

158 F.3d 1243, 1249 (Fed. Cir. 1998).

B. Level of Skill in the Art

With respect to the 604 Patent, a POSITA is a person holding a Bachelor of

Science degree or its equivalent in electrical engineering or a related technical field

such as computer engineering, having one or more years of experience in a

programming in an x86 processing environment. (Ex. 1014, p.7, ¶18).

C. Terms to be Construed

1. “Protected Mode”

“Protected mode” appears in independent claims 1, 11 and 21 of the 604

Patent. Protected mode refers to a mode of processor operation in which a

microprocessor can access the largest possible amount of memory. (Ex. 1011,

p.3). Protected mode was developed in order to avoid the 1 MB memory limitation

in the execution of instruction code by enabling 32-bit program instructions to be

15


run at up to 4GB of memory. (Ex. 1014, p.9, ¶26). It is well-known in the art that

protected mode is necessary to support virtual 8086 mode, which was released for

the first time in the 80386 microprocessor in order to emulate an 8086 processor

running a 16-bit program. Id., p.10, ¶29.

Protected mode is invoked in the context of the SMI handler, which is

mapped above the conventional 1 MB boundary imposed by real mode, wherein

power management code is executable as a page-enabled, protected mode virtual

task within SMM mode. (Ex. 1001, p.13, 2:31-35 and p. 11, Fig. 7A (S108)).

“During execution of the system management activities, the software occasionally

configures the processor to operate in the protected mode so as to facilitate the

execution of certain special tasks.” Id., p.16, 7:3-5.

The 604 Patent also states that the “x86 family of processors support the v86

mode of operation by the hardware setup provided in the protected mode of

operation.” (Ex. 1001, p.15, 5:45-47). Thus, applying BRI, “protected mode”

should be construed to be at least as broad as “a mode of processor operation in

which an 80286 or later generation microprocessor can access the largest possible

amount of memory for running a program, including memory above the first 1

Megabyte of memory.” (Ex. 1014, p.14, ¶41).

16


2. “System management mode (SMM)”

Independent claims 1, 11 and 21 of the 604 Patent also recite a “system

management mode (SMM).” Applying the BRI standard, a POSITA at the time of

invention would understand this language to be at least as broad as “an operating

mode of an 80386 and later generation microprocessor in which special separate

software for managing system interrupts is executed from memory.” (Ex. 1014,

p.14, ¶42).

The 604 Patent’s usage is consistent with the ordinary meaning of SMM

exemplified in the foregoing construction, and states that “it is understood by one

of ordinary skill in the technology that the present invention can be implemented in

any processor based system which employs any microprocessor that provides the

use of a System Management Mode (SMM), which is an operating mode that

employs a dedicated interrupt line (line 50 in FIG. 1) and memory space SMRAM

20. SMM is used to implement intelligent power management and other enhanced

system functions in firmware in a manner which is completely transparent to the

operating system and applications software.” (Ex. 1001, p.14, 3:10-20).

3. “Virtual mode”

“Virtual mode” is also used in independent claims 1, 11 and 21 of the 604

Patent. Applying BRI, the construction of this phrase is at least as broad as

17


“Virtual 8086 mode or V86 mode, wherein real mode programs on x386, x486 and

later generations of processors are run while in protected mode, with the program

assuming it is operating in 8086 real mode” (Ex. 1011, p.5; Ex. 1014, p.15, ¶44).

To enter real mode once the x286 processor was in protected mode was awkward,

requiring the resetting of the computer. (Ex. 1014, p.9, ¶27 and p.15, ¶46). The

1985 release of the 386 processor enhanced the 286 processor with virtual mode,

which permitted 8086-type (16-bit real mode) programs to run in protected mode,

with multitasking. (Ex. 1011, p.5; Ex. 1014,p.9, ¶28).

The present invention uses “virtual mode” in its conventional sense, which is

interchangeable with v86 mode and virtual 8086 mode. The 604 Patent states that

“[t]he x86 family of processors support the V86 mode of operation by the

hardware setup provided in the protected mode of operation. The processors are

able to execute a number of 8086 programs as virtual 8086 tasks. A virtual task is

set up to provide in software what appears to be an 8086 environment. A virtual

8086 task uses the x86 processor hardware and system software to execute a real

mode program.” (Ex. 1001, p.15, 5:45-52).

The 604 Patent “creates a virtual monitor that runs under the system

management mode (SMM). With memory paging enabled to execute SMI code in

virtual mode. The virtual mode operation allows the SMM code that was written

(for SMM mode that had to run below 1 Megabyte) to execute above the 1 18


Megabyte boundary.” (Ex. 1001, p.13, 2:27-35). “Once in virtual mode, the CPU

14 determines the logical address of the application the same way as in real mode.”

Id., p.15, at 6:66-67. “Thus, when running a virtual 8086 task, the processor forms

the v86 mode addresses as in real mode and runs the application program which is

the virtual task.” Id., p.15, at 6:1-4 (emphasis added).

Referring to Figure 7A, at step S114, the SMI handler program configures

the CPU to operate in virtual mode. The SMI handler then proceeds to process the

SMI and to perform system management activities, as shown in process step S116.

Id., p.11 and 16, at 7:45-49. “Upon completion of the system management

activities, the SMI handler configures the CPU 14 to exit the virtual mode, which

also configures the CPU 14 to operate in the protected mode again.” Id., p.16, at

7:15-18. All of the foregoing references are supportive of the BRI construction

advanced herein. (Ex. 1014, p.15, ¶44).

4. “Paging”

Applying BRI, “paging” is at least as broad as “in a memory-management

scheme, retrieving data from secondary storage in blocks called pages, allowing an

operating system to use secondary storage for data that does not fit into physical

random-access memory (RAM).” (Ex. 1014, p.17, ¶53). These pages are well-

19


known units of virtual storage in the prior art. (Ex. 1011, p.5 (definition of “virtual

storage”; Ex. 1014, p.17, ¶54).

In the prior art, it was well-known that, to enter virtual mode, the processor

would enable paging from protected mode. (Ex. 1014, pp.17-18, ¶55). Figure 7A

of the 604 Patent is consistent with this. There, at step S112, while in protected

mode, the SMI handler enables paging prior to entering into protected mode in step

S114. (Ex. 1001, p.11).

When operating in virtual mode, the processor combines the segment

registers with the standard pointer registers or offsets to form linear addresses in

the same manner as an 8086 processor running in real mode. “However, these

linear addresses go through a paging unit to map to 1 Megabyte of physical

memory, which can be anywhere in the system. Thus, when running a virtual 8086

task, the processor forms the V86 mode addresses as in real mode and runs the

application program which is the virtual task.” (Ex. 1001, p.15, 5:59-6:4). This is

supportive of the proffered BRI construction. (Ex. 1014, p.18, ¶56).

VII. Identification of Challenge (37 C.F.R. § 42.104(b))

Petitioner requests IPR on the Grounds of Unpatentability indexed below.

In accordance with 37 C.F.R. § 42.6(d), copies of the references listed in the index

below are filed with this Petition. As support for the Grounds of Unpatentability,

20


Petitioner submits the accompanying declaration of a technical expert, Feliks

Polyudov (Ex. 1014), to explain how a POSITA would understand the art.

Mr. Polyudov is highly qualified to analyze the pertinent prior art and how it

renders the challenged claims unpatentable. As set forth in his declaration, he has

a Masters degree from the National Technical University of Ukraine with a major

in computer engineering. For over twenty years he has worked as a computer

engineer, including substantial experience with systems architecture, firmware and

software. He is recognized as the inventor or co-inventor of sixteen different U.S.

Patents as a result of his work in the primary fields of system architecture and

firmware development. His significant education and work experiences includes

programming with the x86 processors in question. (Id., pp.2-6, ¶¶6-14).

The grounds upon which this petition is based are summarized as follows:

Ground 1: The combination of Collins and the Pentium Manual renders

obvious claims 1-4, 11-14, and 21-24 under 35 U.S.C. § 103(a).

Ground 2: The combination of Collins, the Pentium Manual and the IBM

6x86 Manual renders obvious claims 1-4, 11-14, 21-24 under 35 U.S.C. § 103(a).

Ground 3: The combination of Favor and the Am486 Manual renders

obvious claims 1, 11, and 21 under 35 U.S.C. § 103(a).

21


Ground 4: The combination of the Am486 Manual and the IBM 6x86

Manual renders obvious claims 1, 11, and 21 under 35 U.S.C. § 103(a).

Ground 5: Wooten 1 anticipates claims 1-2, 11-12 and 21-22 under 35

U.S.C. § 102.

Ground 6: Collins, the Pentium Manual and the Intel Architecture Software

Developer’s Manual render claims 5-10, 15-20 and 25-30 obvious.

Ground 1 applies Collins with the Pentium Manual. Collins refers to a May

1997 article entitled “The Caveats of Pentium System Management Mode,” (Ex.

1006), wherein Collins explores execution of SMM-related programs in protected

mode and virtual mode using the Pentium processor. Collins is prior art under 35

U.S.C. 102(a). Because Collins is specific to the Pentium processor, a POSITA

would naturally seek to combine Collins with the Pentium Manual. (Ex. 1014,

p.58-59, ¶165). The Pentium Manual (Ex. 1005) describes the architecture of a

Pentium processor. It is dated 1995, over two years prior to the priority date for

the 604 Patent. As such, it is prior art under at least 35 U.S.C. 102(a) and 102(b).

Ground 2 applies Collins, the Pentium Manual and the IBM 6x86 Manual

(Ex. 1012). It is dated 1996 and is prior art under 35 U.S.C. 102(a) and 102(b).

The IBM 6x86 Manual more explicitly teaches actively configuring an x86

processor into protected mode while in SMM. (Ex. 1014, p.63, ¶179). A POSITA

22


would combine Collins, the Pentium Manual and the IBM 6x86 Manual to

maximize the utility of the x86 processor, design optimal SMI handler code, and

take full advantage of the architectural capabilities of the Pentium processor. Id.,

pp.58-59, 64-67, ¶¶165, 183-186, and 188.

Ground 3 applies the combination of Favor (Ex. 1003), an Advanced Micro

Devices (AMD) patent applied for in May 1996 relating to the flexible

implementation of SMM in a processor, more than a year in advance of the 604

Patent. Favor is combined with the 1995 Am486 Manual (Ex. 1004) for the

enhanced family of 486 AMD microprocessors. Favor is prior art under at least 35

U.S.C. §102(a) and 102(e). The Am486 Manual is prior art under 35 U.S.C.

§102(a) and 102(b). It would have been obvious to apply the Favor patent for

implementing SMM with an AMD enhanced 486 processor utilizing SMM, as is

taught in the Am486 Manual. (Ex. 1014, p.41, ¶¶122-124).

Ground 4 applies the Am486 Manual and IBM 6x86 Manual. The 6x86

Manual expressly teaches configuring an x86 processor to protected mode while in

SMM than the Am486 Manual. (Ex. 1014, p.63, ¶179). A POSITA would

combine these references to maximize the utility and capabilities of the x86

processor, and to design optimal SMI handler code. Id., pp.64-66, ¶¶ 183-187.

23


Ground 5 applies Wooten 1 (Ex. 1002), a reference published in 1995, more

than two and a half years prior to the priority date for the 604 Patent, for a virtual

system management mode (VSM). Wooten 1 is prior art under at least 35 U.S.C.

102(a), 102(b) and 102(e). VSM is entered upon a virtual system mode interrupt,

or VMI. VSM is introduced as a new mode for system management, which is

compatible with real mode, protected mode and virtual mode.

Ground 6 applies the combination of Collins, the Pentium Manual and the

related Intel Architecture Software Developer’s Manual Volume 3: System

Programming Guide (1996, 1997) (the “ASDM”), a reference originally published

in 1996. The ASDM is prior art under at least 35 U.S.C. 102(a). This combination

shows that claims 5-10, 15-20 and 25-30 were obvious at the time of invention.

Recognizing that the Board is to secure “the just, speedy, and inexpensive

resolution of every proceeding” (37 C.F.R. § 42.1(b)), Petitioner has tailored the

discussion to seven references among numerous others which are of doubtless

relevance, in order to avoid straining these resources, while giving adequate

attention to all thirty of the challenged claims. As shown, the interests of justice

militate in favor of the institution of IPR on each of the grounds presented herein.

Petitioner respectfully submits that denial of any of the asserted grounds of

unpatentability in this Petition on the basis of redundancy, without reaching its

24


merits, would upset the statutory mandate of just, speedy and inexpensive

resolution set forth in 37 C.F.R. § 42.1(b). See CBM2012-00003, Paper 7 at 2. As

a practical matter, the page limitations applicable to this Petition constrain the

Petitioner. These limitations inherently balance the need for both justice and

speed. Petitioner respectfully submits that the Board should not adopt an overly

restrictive view of how many grounds of patentability to consider, for the failure to

consider potentially meritorious grounds presented in these limited pages would

threaten the balance of the foregoing factors of justice and speed. When the Board

further considers the estoppel provisions in the event of an unsuccessful trial on the

merits, Petitioner is confident that the Board will conclude that the interests of

justice and speed are best served by taking up IPR on all grounds presented herein.

Petitioner now presents each ground of unpatentability in detail:

A. Ground 1: The combination of Collins and the Pentium Manual

renders obvious claims 1-4, 11-14, and 21-24.

In Graham v. John Deere Co., 383 U.S. 1 (1966), the United States Supreme

Court clarified the nonobviousness requirement in United States patent law, set

forth in 35 U.S.C. § 103. The Court held that §103 required a determination of the

scope and content of the prior art, the differences between the claimed invention

and the prior art, and the level of ordinary skill in the prior art. Id. at 17-18. In

25


addition, “secondary considerations” may in appropriate cases serve as evidence of

nonobviousness. Id. A basis to combine teachings from the references need not be

stated expressly in any prior art reference. In re Kahn, 441 F.3d 977, 987-88 (Fed.

Cir. 2006). There need only be an articulated reasoning with rational

underpinnings to support a motivation to combine teachings. Id. at 988.

“The Caveats of Pentium System Management Mode,” by R. Collins, as

published in Dr. Dobbs Journal on May 1, 1997 (“Collins,” Ex. 1006) is especially

important, for it teaches various possibilities while working with the Pentium

processor in SMM. For example, Collins has a section entitled “Using Protected

Mode within SMM.” There, it states that the “processor is capable of entering

protected mode, v86 [virtual] mode…if the SMM handler was programmed to do

such a thing (although it probably wasn’t).” (Ex. 1006, p.4) (emphasis added).

This is a crucial teaching of being in protected mode and virtual mode while in

SMM, which is the critical thrust of the 604 patent. “SMM [is] a completely

separate x86 CPU state within a CPU. In that regard, it is orthogonal to all other

operating modes.” Id.

The Pentium Manual (Ex. 1005) describes in even greater detail than Collins

the architecture of the Intel Pentium processor at issue in Collins, including the

memory management features such as paging. (Ex. 1014, pp.49, ¶141). The

Pentium Manual describes a Pentium processor with two primary operating modes 26


– protected mode and real mode -- and a system management mode. (Ex. 1005,

p.40). Protected mode features the ability to directly execute "real-address mode"

8086 software in a protected, multi-tasking environment. This feature is identified

as Virtual-8086 "mode" (or "V86 mode"). Id. This “v86” mode is virtual mode.

(Ex. 1014, p.49, ¶143).

A POSITA is presumed to be aware of all pertinent art, thinks in accordance

with the conventional wisdom of the art, and is a person of ordinary creativity,

KSR, 550 U.S. at 420. “The combination of familiar elements according to known

methods is likely to be obvious when it does no more than yield predictable

results.” KSR, 550 U.S. at 416. Here, a POSITA would be motivated to combine

Collins and the Pentium Manual because Collins identifies the use of the same

Pentium processor described in the Pentium Manual, and these complimentary

references describe the features and capabilities of the Pentium processor having

SMM, protected mode and virtual mode. (Ex. 1014, pp.58-59, ¶165).

Claim Chart I demonstrates that Collins and the Pentium Manual provide

grounds for cancellation of the challenged claims. Unless otherwise noted, all

underlining and bolding of text in the chart are emphasis added.

604 Patent Claim Chart I –Collins and the Pentium Manual [1P] 1. An apparatus for

The preamble is not a limitation. Pentium Manual: “SMM handler: System Management

27


executing instructions in a system management mode in a processor-based system, comprising:

Mode handler. This is the code that will be executed when the processor is in SMM. An example application that this code might implement is a power management control or a system control function.” Id. at 20-2 (emphasis added). “After saving its state the CPU will jump to the address location SMBASE + 8000H to begin executing the SMI handler.” (Ex. 1005, p.495 (emphasis added)). See also Ex. 1014, pp.49-50, ¶144.

[1.1] a memory for storing instruction sequences by which the processor-based system is processed;

Pentium Manual: “SMRAM: This is the physical memory dedicated to SMM. The SMM handler code and related data reside in this memory. This memory is also used by the processor to store its context before executing the SMM handler.” (Ex. 1005, p.494 (emphasis added)). See also Ex. 1014, p.50, ¶145.

[1.2] a processor having a system address space, the processor for executing the stored instruction sequences; and

Pentium Manual: The Pentium processor has “[a] dedicated and secure memory space (SMRAM) for SMI handler code and CPU state (context) data with a status signal for the system to decode access to that memory space, SMIACT#.” (Ex. 1005, p.493 (emphasis added)). See also Ex. 1014, pp.50-51, ¶146.

[1.3] wherein the stored instruction sequences cause the processor to:

See [1.4]-[1.7] below.

[1.4] (a) configure the processor to operate in a protected mode while in system management mode, the processor operating at an address greater

Collins (operate in a protected mode while in system management mode): In a section entitled “Using Protected Mode within SMM,” it states that the “processor is capable of entering protected mode…if the SMM handler was programmed to do such a thing ….” (Ex. 1006, p.4).

See also Ex. 1014, p.60, ¶167. Pentium Manual (processor operating at an address greater than one megabyte): See Ex. 1014, p.51-52, ¶148.

28


than one megabyte;

“In SMM, the CPU can access or jump anywhere within the 4Gbyte logical address space. The CPU can also indirectly access or perform a near jump anywhere within the 4-Gbyte logical address space.” (Ex. 1005, p.502 (emphasis added)). SMRAM can be relocated above 1 MB. (Id., p.507). A POSITA would recognize that one feature of protected

mode is that is permits instructions located between 1MB and

4GB of memory to be accessed by the processor. (Ex. 1014,

p.52-53, ¶149).

[1.5] (b) invoke a paging feature of the processor;

Collins: Section entitled “Using SMM to Create a CPL-0 v86 Task,” indicates that paging is enabled. (Ex. 1006, pp.4-5). (Ex. 1014, p.61, ¶ 170). Pentium Manual: “16.5. SOFTWARE INITIALIZATION IN PROTECTED MODE ... Paging can be enabled for allowing access to large data structures which are partly in memory and partly on disk.” (Ex. 1005, p.402 (emphasis added)). “If the PG bit is set, paging is enabled.” (Ex. 1005, p.403). See also Ex. 1014, p.53, ¶150. “22.2.1. Paging for Virtual-8086 Tasks Paging is not necessary for a single virtual-8086 task, but paging is useful or necessary for any of the following reasons: Creating multiple virtual-8086 tasks. Each task must map the lower megabyte of linear addresses to different physical locations.” (Ex. 1005, p.532). See also Ex. 1014, p.53, ¶151.

29


[1.6] (c) configure the processor to operate in a virtual mode; and

Collins: The Section entitled “Using SMM to Create a CPL-0

v86 Task,” shows enabling virtual mode while employing

SMM in protected mode by placing the VM bit in the

EFLAGS register, i.e., configuring the processor into virtual

mode. (Ex. 1006, pp.4-5; Ex. 1014, pp.60-61, ¶¶168-169).

Section heading: “Using Protected Mode within SMM” “[P]rocessor is capable of entering protected mode, v86 mode…if the SMM handler was programmed to do such a thing (although it probably wasn’t).” (Ex. 1006, p.4) (emphasis added). v86 mode is synonymous with virtual mode. (Ex. 1014, p.49,

¶143).

Pentium Manual: Figure 20-2 shows moving from protected

mode (PE=1) to virtual mode (VM=1). (Ex. 1005, p.499-500;

Ex. 1014, p.54; ¶152). See also Figure 22-2 regarding

transitioning from protected mode into virtual mode. (Ex.

1005, p.534).

“The processor runs in virtual-8086 mode when the VM (virtual machine) bit in the EFLAGS register is set.” (Ex. 1005, p.529). See also Ex. 1014, p.54, ¶152.

[1.7] (d) process the instruction sequences stored,

Pentium Manual: “SMM is entered through activation of an external interrupt pin (SMI#), which switches the CPU to a separate address space while saving the entire context of the CPU. SMM-specific code may then be executed

30


transparently. The operation is reversed upon returning.” (Ex. 1005, p.41 (emphasis added)). See also Ex. 1014, p.54-55, ¶153. As indicated above, once SMM in invoked, SMI handler executes to perform system management activities in response to the SMI. (Ex. 1005, p.495).

[1.8] wherein the process steps occur upon the receipt of an instruction to process a system management request.

Pentium Manual: “The Pentium microprocessor also provides support for System Management Mode (SMM). SMM … to implement system power management and OEM differentiation features. SMM is entered through activation of an external interrupt pin (SMI#), which switches the CPU to a separate address space while saving the entire context of the CPU. SMM-specific code may then be executed transparently.” (Ex. 1005, p.41 (emphasis added)). “The SMI# interrupt causes the processor to switch to SMM.” (Ex. 1005, p.500). A POSITA would understand that an SMI interrupt signifies

the emergent SMI handler code, comprising instructions

which trigger the processing of system management requests.

See also Ex. 1014, p.55-56, ¶154.

[2.1] The apparatus of claim 1, wherein (b) comprises: See [1.5] [2.2] (b.1) creating at least one page table; and

Pentium Manual: When paging is used, the CR3 register

has the 20 most-significant bits of the address of the page

directory (the first-level page table). (Ex. 1005, p.266

(emphasis added)).

See also Ex. 1014, p.56, ¶156.

[2.3] (b.2) invoking a paging feature of the processor. See [1.5] [3] The Pentium Manual: “If the PG bit is set, paging is enabled.”

31


apparatus of claim 1, wherein the instruction sequences further cause the processor to create at least one page table prior to (a).

(Ex. 1005, p.403). Before setting the PG (paging enabled) bit, at least two page

tables must be created: the page directory (CR3) and at least

one second-level page table. (Id.) The PG and PE (protected

mode enabled) bits can be set at the same time. (Id.) It is

known in the art that CR3 can be loaded with a page table

before the PE (protected mode enabled or PE=1, see Ex.

1005, p.308) bit is enabled in control register 0 (CR0),

signifying entry into protected mode. (Ex. 1014, pp.10-11,

¶31).

[4.1] The apparatus of claim 1, wherein (a) comprises: (a.1) performing a near jump to a second location; and

Pentium Manual: “In SMM, the CPU can access or jump anywhere within the 4Gbyte logical address space. The CPU can also indirectly access or perform a near jump anywhere within the 4-Gbyte logical address space.” (Ex. 1005, p.502 (emphasis added)). See also Ex. 1014, p.57, ¶158.

[4.2] (a.2) configuring the processor to operate in a protected mode.

See [1.4]

[11.P] A method for executing instructions in a system management mode in a processor-based system, comprising the acts of:

See [1.P]

[11.1] (a) configuring a processor to operate in a protected mode, while in system management mode, the processor operating at an address greater than one megabyte;

See [1.4]

[11.2] (b) invoking a paging feature of the processor;

See [1.5]

[11.3] (c) configuring the processor to operate in a virtual See [1.6] 32


mode; [11.4] (d) processing instruction sequences stored in a first location; and

See [1.7]

[11.5] wherein the acts occur upon the receipt of an instruction to process a system management request.

See [1.8]

[12] The method of claim 11, wherein (b) comprises: (b.1) creating at least one page table; and (b.2) invoking a paging feature of the processor.

See [2] and [11.P]-[11.5]

[13] The method of claim 11, further comprising creating at least one page table prior to (a).

See [3] and [11.P]-[11.5]

[14.1] The method of claim 11, wherein (a) comprises:

See [1.4] and [11.P]-[11.5]

[14.2] (a.1) performing a near jump to a second location; and

See [4.1]

[14.3] (a.2) configuring the processor to operate in a protected mode.

See [1.4] and [11.2]

[21.P] Computer-executable process for executing instructions in a system management mode in a processor-based system, comprising:

See [1.P]

[21.1] configuring the processor to operate in a protected mode while in system management mode, the processor operating at an address greater than one megabyte;

See [1.4]

[21.2] invoking a paging feature of the processor; See [1.5] [21.3] configuring the processor to operate in a virtual mode; See [1.6] [21.4] processing instruction sequences stored in a first location; and

See [1.7]

[21.5] wherein the process occurs upon the receipt of an instruction to process a system management request.

See [1.8]

[22.1] 22. Computer-executable process of claim 21, wherein (b) comprises:

See [21.P] – [21.5]

[22.2] (b.1) creating at least one page table; and See [2.2] [22.3] (b.2) invoking a paging feature of the processor. See [1.5] [23] Computer-executable process of claim 21, further comprising creating at least one page table prior to step (a).

See [21.P] – [21.5] and [3]

33


[24.1] Computer-executable process of claim 21, wherein (a) comprises:

See [21.P]-[21.5]

[24.2] (a.1) performing a near jump to a second location; and See [4.2] [24.3] (a.2) configuring the processor to operate in a protected mode.

See [1.4] and [21.1]

Claim Chart I shows that Collins and the Pentium Manual render challenged

claims 1-4, 11-14 and 21-24 obvious. Ground 1 shows that the challenged claims

withdrew what was known in the field; these claims, if allowed to stand, merely

diminish the resources available to skillful men. See KSR, 550 U.S. at 415-16.

For this reason, the challenged claims should be determined unpatentable.

B. Ground 2: Collins, the Pentium Manual and the IBM 6x86 Manual

renders challenged claims 1-4, 11-14, and 21-24 obvious.

Claim Chart I above shows that the elements of the challenged claims are

present in the combination of the Pentium Manual and Collins. In Collins, it states

that the “processor is capable of entering protected mode…if the SMM handler

was programmed to do such a thing (although it probably wasn’t).” (Ex. 1006,

p.4) (emphasis added). Thus, Petitioners anticipate that the Patent Owner will

seize on the highlighted language to argue that elements [1.4], [11.1] and [21.1]

(configuring the processor to protected mode while in SMM) are insufficiently

taught in the combination presented in Ground 1. Although Petitioners contend

that such an argument conflates non-standard programming with programming

34


unknown to a POSITA, adding the IBM 6x86 Manual to the combination leaves no

doubt about obviousness. The 6x86 Manual unequivocally teaches configuring the

processor to protected mode while in SMM. Specifically, the Manual states that

"[w]ithin the SMI service routine, protected mode may be entered and exited as

required, and real or protected mode device drivers may be called." (Ex. 1012,

p.95 at §2.9.5) (emphasis added).

Like the Pentium Manual, the 6x86 Manual teaches the technical concepts at

issue. It is consistent with the x86 instruction set. (Ex. 1012, p.1). It teaches

SMM. (Ex. 1012, p.11). SMM memory space can be up to 4 Gigabytes. (Ex.

1012, p.92).

The 6x86 Manual teaches real mode applications running in virtual mode

and paging. (Ex. 1012, p.100). “V86 [virtual] mode allows the execution of 8086-

type [real mode] applications, yet still permits use of the IBM 6x86 CPU paging

mechanism.” (Id.). The 6x86 Manual also teaches enabling paging as per

elements [1.5], [11.2] and [21.2], so that, from protected mode, the transition can

be made to virtual mode (elements [1.6], [11.3] and [21.3]) for the purpose of

running real mode code above the 1 megabyte limit ([1.4], [11.1] and [21.1]). (Ex.

1014, p.64, ¶181, citing Ex. 1012, p.100).

A POSITA would be motivated to combine the teachings of Collins and the

Pentium Manual with the teachings of the 6x86 Manual to maximize the utility of 35


the x86 processor, design optimal SMI handler code, and take full advantage of the

architectural capabilities of the Pentium processor. (Ex. 1014, pp.64-66, ¶¶ 183-

186). For these reasons, the combination of the Pentium Manual, Collins and the

6x86 Manual presents a compelling obviousness challenge to claims 1-4, 11-14,

21-24. (Id., p.66, ¶188).

C. Ground 3: Challenged Claims 1, 11 and 21 are obvious under 35

U.S.C. § 103(a) in light of the combination of Favor and the Am486 Manual.

U.S. Patent No. 6,093,213 (“Favor”), has a priority date of May 16, 1996,

such that it is prior art under at least 35 U.S.C. § 102(a), 102(b) and 102(e). (Ex.

1003). It represents an exemplary embodiment of a flexible application of SMM

on a processor in the prior art. Favor, an AMD-owned patent, is combined with a

1995 manual for an AMD family of microprocessors (the Am486 Manual).

Because a POSITA is presumed to be aware of all pertinent art, thinks in

accordance with the conventional wisdom of the art, and is a person of ordinary

creativity, KSR, 550 U.S. at 420, Favor represents an obvious way to combine an

approach to SMM on an Am486 processor. See IPR2012-00001, Paper 59 at 39-47

(combining four references to determine that three patent claims were unpatentable

under Section 103).

36


A POSITA would be motivated to use the Am486 as the processor of Favor

in order to obtain the enhanced feature set described in Am486 Manual. (Ex. 1014,

p.41, ¶¶122-124). Am486 teaches memory architecture, and features and

limitations of an AMD processor. Favor and Am486 each teach SMM, protected

mode and virtual mode explicitly, as shown in Claim Chart II below.

Chart II shows that combining Favor and Am486 reveals the obviousness of

the challenged claims. Unless otherwise noted, all underlining and bolding of text

in the chart are emphasis added.

604 Patent Claim Chart II –Favor and Am486 Manual

[1P] 1. An apparatus for executing instructions in a system management mode in a processor-based system, comprising:

This is preamble language, not a limitation.

Favor: “A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "soft" and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.” (Ex. 1003, p.1, Abstract) (emphasis added).

“Several advantages are achieved by the described invention. One advantage is that the system management mode (SMM) operation is transparent to the operation of all other software so that other software operates identically whether SMM is active or inactive. Similarly, SMM operation is transparent to the

37


operation of all normal CPU operating modes.” (Ex. 1003, p.16, 3:45-52) (emphasis added).

See also Ex. 1014, p.34-35, ¶106.

Am486 Manual: “Enhanced Am486 microprocessors use a 32-bit architecture with on-chip memory management and cache memory units. The instruction set includes the complete 486 microprocessor instruction set along with extensions to serve the new extended applications.” (Ex. 1004, p.18) (emphasis added).

“The Enhanced Am486 microprocessor has four modes of operation: Real Address Mode (Real Mode), Virtual 8086 Address Mode (Virtual Mode), Protected Address Mode (Protected Mode), and System Management Mode (SMM).” (Id.) (emphasis added).

See also Ex. 1014, p.42, ¶126.

[1.1] a memory for storing instruction sequences by which the processor-based system is processed;

Favor: “FIG. 8 is a memory map which illustrates processor memory assignments including assignment of a separate system management RAM (SMRAM) area.” (Ex. 1003, p.16, 4:17-19).

See also Ex. 1014, p.35, ¶107.

Am 486 Manual: “Memory is organized into one or more variable length segments, each up to 4 Gbytes (232 bytes). A segment can have attributes associated with it, including its location, size, type (i.e., stack, code, or data), and protection characteristics. Each task on a microprocessor can have a maximum of 16,381 segments, each up to 4 Gbytes.” (Ex. 1004, p.18)

See also Ex. 1014, p.42, ¶127.

[1.2] a processor having a system address space, the

Favor: “A memory map shown in FIG. 8 illustrates processor 120 memory assignments, including assignment of a separate system management RAM (SMRAM) area.”

38


processor for executing the stored instruction sequences; and

(Ex. 1003, p.30-31, 32:59-33:10)

See also Ex. 1014, pp.35-36, ¶108.

Am486 Manual: “The processor begins executing SMM code from a separate address space, referred to earlier as system management RAM (SMRAM).” (Ex. 1004, p.43).


See [1.4]-[1.7] below.

[1.4] (a) configure the processor to operate in a protected mode while in system management mode, the processor operating at an address greater than one megabyte;

Favor: “Referring to FIG. 9, a flowchart which illustrates SMM functionality is shown. SMM 900 is a processor operating mode that is distinct and substantially different from other modes including real, V86 and protected modes. … While SMM 900 is active, all x86 architectural features and instructions are available for use in addition to a set of SMM support instructions. ... However, the SMM environment definition is a soft definition which is completely adaptable and designated by the information set up or initialized by a RISC SMM entry sequence which begins in step 912.” (Ex. 1003, p.31, 33:23-42) (emphasis added).

See also Ex. 1014, p.36-37, ¶110-112.

“The SMM initialization routine 920 is activated upon an SMI signal, a SMM software instruction call or an I/O access trap. Upon recognition of an activating signal, … the processor 120 may save the current x86 state and/or a suitable extended instruction pointer (EIP) if desired, set up or initialize a new x86 operating state including specifying the SMM operating mode, setting a SMM micro-architecture control register bit (see SMM control register 1038 shown in FIG. 10), and jump to an x86 SMM handler code which is located at a specified location in the A0000H to BFFFFH address area. Essentially any type of SMM entry functionality is allowed and implemented.” (Ex. 1003, p.31, 33:46-59) (emphasis added).

39


A POSITA would understand that “a new x86 operating state”

includes protected mode, and that in protected mode, the CPU

can operate at an address greater than one megabyte while

operating in protected mode. See Ex. 1014, pp.37-38, ¶113-114.

Am486 Manual: “Protected Mode provides access to the sophisticated memory management paging and privilege capabilities of the processor.” (Ex. 1004, p.18).

“(If the SMM was entered from Protected mode, the Real mode interrupt and exception support is not available.)” (Ex. 1004, p.45) (emphasis added).

AMD Manual, p. 45: “In SMM, the CPU can access or jump anywhere within the 4-Gbyte logical address space. The CPU can also indirectly access or perform a near jump anywhere within the 4-Gbyte logical address space.” (Ex. 1004, p.45) (emphasis added). “If SMRAM has been relocated to address space above 1 Mbyte, and A20M is active upon entering SMM,…” (Ex 1004, p.49). See Ex. 1014, p.43-44, ¶ 130-131.


Favor: “While SMM 900 is active, all x86 architectural features and instructions are available for use in addition to a set of SMM support instructions.” (Ex. 1003, p.31, 33:34-36).

See also Ex. 1014, pp.38-39, ¶115.

Am486 Manual: “Protected Mode provides access to the sophisticated memory management paging and privilege capabilities of the processor.” (Ex. 1004, p.18) (emphasis added).

40


(Ex. 1004, p.2) (emphasis added).

See also Ex. 1014, p.44-45, ¶132-133.


Favor: “While SMM 900 is active, all x86 architectural features and instructions are available for use in addition to a set of SMM support instructions.” (Ex. 1003, p.31, 33:34-36) (emphasis added).

“[T]he SMM environment definition is a soft definition which is completely adaptable” (Id., 33:38-40).

See also Ex. 1014, p.39, ¶116.

Am486 Manual: “In Virtual Mode, the processor appears to be in Real Mode, but can use the extended memory accessing of Protected Mode.” (Ex. 1004, p.18) (emphasis added).

See also Ex. 1014, p.45, ¶134.

[1.7] (d) process the instruction

Favor: “SMM software 810, including SMM instructions and SMM data, resides at a predefined location within the A0000H to BFFFFH area of address space and physically resides in main memory mapped to this region. During normal system operation,

41


sequences stored,

a main memory controller is configured to respond only to SMM accesses within the portion of the A0000H to BFFFFH memory locations that specifically holds SMM software. These locations are called an SMRAM memory locations 812.” (Ex. 1003, p.31, 33:2-10) (emphasis added).

See also Ex. 1014, p.39, ¶117.

Am486 Manual: “The processor begins executing SMM code from a separate address space, referred to earlier as system management RAM (SMRAM).” (Ex. 1004, p.43).

See also Ex. 1014, p.46, ¶135.


Favor: “Referring to FIG. 9, a flowchart which illustrates SMM functionality is shown. SMM 900 is a processor operating mode that is distinct and substantially different from other modes including real, V86 and protected modes. Entry 910 into system management mode (SMM) is attained by one three methods, including assertion of a signal on a system management interrupt (SMI) interrupt pin, a call by a special SMM software instruction and the occurrence of an I/O access trap.” (Ex. 1003, p.19, 9:23-31) (emphasis added).

See also Ex. 1014, p.40, ¶118.

Am486 Manual: “The external signal SMI causes the processor to switch to SMM.” (Ex. 1004, p.43) (emphasis added).

(Ex. 1004, p.44)

See also Ex. 1014, pp.46-48, ¶¶136-137.

Claim Chart II demonstrates that Favor and the Am486 Manual render

challenged claim 1 unpatentable under 35 U.S.C. § 103 (obviousness). As Claim

42


Chart I illustrates, there is considerable overlap in the elements of the independent

claims 1, 11 and 21. Claim preambles [11.P] and [21.P] are each taught for the

same reasons discussed regarding Favor and the Am486 Manual and claim [1.P].

Claim elements [11.1] and [21.1] are each taught in the foregoing analysis of [1.4].

[11.2] and [21.2] are each taught for the same reasons as discussed in [1.5]. [11.3]

and [21.3] are each taught in the analysis of [1.6]. [11.4] and [21.4] are each

addressed in relation to [1.7]. [11.5] and [21.5] are each addressed in relation to

[11.8]. For these reasons, claims 11 and 21 are invalid for the same reasons shown

in relation to claim 1 in Chart II above. (Ex. 1014, pp.48-49, ¶¶138-140).

D. Ground 4: The Am486 Manual in combination with the IBM 6x86

Manual renders claims 1, 11 and 21 obvious.

The analysis of Ground 3 above shows that the Am486 Manual teaches the

elements of claims 1, 11 and 21. Petitioners anticipate that the Patent Owner may

assert that elements [1.4], [11.1] and [21.1] (configuring the processor to protected

mode while in SMM) are insufficiently demonstrated in the Am486 Manual.

Although Petitioners disagree with that argument, the IBM 6x86 Manual sets forth

an incontrovertible teaching of configuring the processor to protected mode. (Ex.

1012, p.95 at §2.9.5) (emphasis added).

Like the Am486 Manual, the 6x86 Manual teaches the fundamental

technical concepts at issue here. It is consistent with the x86 instruction set. Id., 43


p.1. It teaches SMM. (Ex. 1012, p.11). SMM memory space can be up to 4

Gigabytes. Id., p.92. The 6x86 Manual teaches paging, so real mode applications

can run in virtual mode. Id., p.100. The 6x86 Manual further teaches enabling

paging as per elements [1.5], [11.2] and [21.2], so that, from protected mode, the

transition can be made to virtual mode (elements [1.6], [11.3] and [21.3]) for the

purpose of running real mode code above the 1 megabyte limit ([1.4], [11.1] and

[21.1]). (Ex. 1014, p.64, ¶181, citing Ex. 1012, p.100).

As one of ordinary creativity, a POSITA would be motivated to combine the

Am486 Manual in view of with the 6x86 Manual to maximize the usefulness of the

x86 processor, design ideal SMI handler code, and take advantage of the

architectural capabilities of the AMD 486 processor. (Ex. 1014, pp.64-66, ¶¶ 183-

187). For these reasons, the combination of the Am486 and the 6x86 Manual

demonstrates the obviousness of challenged claims 1,11 and 21. Id., p.66, ¶187.

E. Ground 5: Wooten 1 anticipates claims 1-2, 11-12 and 21-22.

Wooten 1 refers to U.S. Patent No. 5,644,755, a patent which was applied

for on February 24, 1995. (Ex. 1002, p.1). Wooten describes, among other things,

“[a] processor having the prior three user addressing modes and a new virtual

system mode (VSM).” Id., p.11, 3:1-9.

44


Wooten 1 teaches the virtual system management mode as an improvement

on more traditional forms of SMM. (Ex. 1014, p.22, ¶69). Wooten’s VSM is also

the subject of U.S. Patent No. 5,832,299 (Ex. 1008, or “Wooten 2”), which is a

continuation patent of Wooten 1. During prosecution of an unrelated application

involving replacement of registers while transitioning in and out of SMM (which

ultimately issued as U.S. Patent 7,444,500 (Ex. 1009)), Wooten 2 was identified as

the basis of a rejection to the claims. The Examiner, applying the BRI standard to

system management mode, determined that Wooten’s VSM exemplified a form of

SMM, as used in the claims. “Wooten ‘299’s Virtual System Mode is best

reasonably and broadly interpreted as the claimed System Management Mode.”

(Ex. 1010, p.5). For this and other reasons presented in the chart below, Mr.

Polyudov concludes that the VSM of Wooten 1 meets the BRI construction of

system management mode. (Ex. 1014, pp.23-26, ¶¶73-80). The support for his

conclusion is identified in Claim Chart III below in section [1P], showing that

VSM is not a user mode, but a system mode reliant upon system interrupts which

are managed by special VSM code. Id.

Claim Chart III indicates that Wooten 1 teaches all of the limitations, and

therefore renders anticipated claims 1-2, 11-12 and 21. These teachings are

explicit or, in very few cases, inherent. Unless otherwise noted, all underlining and

bolding of text in the chart are emphasis added.

45


604 Patent Claim Chart III –Wooten 1 (Ex. 1002) [1P] 1. An apparatus for executing instructions in a system management mode in a processor-based system, comprising:

This is preamble language, not a limitation.

“A processor embodying the principles of the present invention includes a processor having the prior three user addressing modes and a new virtual system mode (VSM). The processor is preferably compatible with Intel 486 or higher processors, and therefore in this context, the user modes refer to normal operational modes of the processor, including real mode, protected mode and virtual 8086 mode.” (Ex. 1002, p.11, 3:1-9)

“The processor P has four modes of operation, namely, real mode, protected mode, virtual 8086 mode and virtual system mode. In this context, real mode, protected mode and virtual 8086 mode are referred to as user modes.” (Id., p.12, 5:18-21)

(See also id., p.17, 15:24-55)

“If the Hardware Interrupt Enable (HIE) bit in the VSM enable register 238 is set, all external hardware interrupts (INTR and NMI) will cause virtual system mode to be entered through vector 3. This vector allows conventional hardware to be transparently emulated with non-conventional hardware and a VSM handler.” (Id., p.18, 17:34-39) (emphasis added).

“Virtual system mode (VSM) provides an additional mode of operation from which a VSM emulation task can be performed transparently to the conventional software executing on the computer system.” (Id., p.12, 5:42-45) (emphasis added). “Virtual System Mode is best reasonably and broadly interpreted as the claimed System Management Mode.” (Ex. 1010, p.5). See also Ex. 1014, pp.23-24, ¶¶73.

[1.1] a memory for storing instruction

“Memory unit 102 provides conventional memory storage for programs and data of the computer system C.” (Ex. 1002, p.11, 4:40-42).

46


sequences by which the processor-based system is processed;

See also Ex. 1014, p.27, ¶81.

[1.2] a processor having a system address space, the processor for executing the stored instruction sequences; and

“The processor has three distinct address spaces known as logical, linear, and physical.” (Ex. 1002, p.14, 9:18-19) (emphasis added). “The upper 16MB of the virtual system mode memory space (0×ff000000 through 0×ffffffff) is designated as non-mapped virtual system mode memory. Virtual system mode logical addresses in this range are directly converted to an addressable range of the processor. Virtual system mode logical addresses below 0×ff000000 will be translated to physical addresses by the current page table if paging is enabled (protected mode). Otherwise, these addresses become physical addresses without modification (real mode).” (Id., p.11, 3:37-47) (emphasis added). See also Ex. 1014, pp.27, ¶82.


See [1.4]-[1.7] below.

[1.4] (a) configure the processor to operate in a protected mode while in system management mode, the processor operating at an address greater than one megabyte;

“Additionally, real mode is the default mode of the processor and is required to setup the processor for protected mode operation.” (Ex. 1002, p.12, 5:28-30) (emphasis added). Referring to Table 1, “Setting this bit enables Virtual System Mode. This bit may only be set when the processor is executing in real mode or protected mode level 0.” (Id., p.13, 7:24-30). A POSITA would understand that the foregoing reference to

executing VSM in protected mode inherently teaches

configuration of the processor to operate in a protected mode

while in SMM. (Ex. 1014, p.28, ¶85).

47


“Protected mode provides access to the memory management capabilities of paging and protection, discussed below, and operates in a 32-bit environment with 4GByte physical memory limit and therefore, in conjunction with virtual system mode, is the preferred mode of operation of the processor.” (Id., p.12, 5:33-38) (emphasis added). “Protected mode removes most of the memory management limitations of the earlier processors.” (Id., p.10, 2:8-10) A POSITA would understand that the “memory management

limitations” of the earlier processors is referring to addresses in

the first megabyte in real mode, and that in protected mode the

processor operates at an address greater than 1 MB and up to 4

GB. (Ex. 1014, pp.29-30, ¶¶88-89). A POSITA would

therefore understand that all aspects of this element are taught in

Wooten. (Ex. 1014, p.30, ¶90).


“Virtual system mode logical addresses below 0×ff000000 will be translated to physical addresses by the current page table if paging is enabled (protected mode).” (Ex. 1002, p.11, 3:42-45) See Ex. 1014, p.30, ¶91.


“Once the processor is in protected mode, an additional real mode environment, called virtual 8086 mode, can be created for backward compatibility with real mode applications.” (Ex. 1002, p.10, 2:11-14) (emphasis added). “Within protected mode, software can perform a task switch to enter into tasks known as virtual 8086 mode tasks thus emulating real mode as a task from within the protected mode of operation.” (Id., p.12, 5:38-41) (emphasis added).

48


See also Ex. 1014, pp.30-31, ¶¶ 92-93.

[1.7] (d) process the instruction sequences stored,

“The processor of claim 2, further comprising: a code segment register for receiving a code segment selector for addressing a code segment containing instruction sequences” (Ex. 1002, p.22, 26:5) (emphasis added). “Interrupts have externally supplied vectors, while exceptions have internally supplied vectors. The processor then determines from the user vector which of the eight VSM vectors is applicable. The VSM vector table contains the starting address of the VSM interrupt service routine. Then the VSM interrupt service routine is executed. VSM code can then determine the source of the interrupt and respond appropriately, thus handling conventional interrupts conventionally or handling non-conventional interrupts with VSM emulation code.” (Id., p.17, 15:34-46) (emphasis added). See also Ex. 1014, pp.31-32, ¶94.


“Transitions from the user modes to virtual system mode can be made by indirect calls through a call gate, such as by a jump or call instruction, or through vectored entries, such as a hardware interrupt or I/O fault.” (Ex. 1002, p.11, 3:15). See also Ex. 1014, p.32, ¶95.

[2.1] The apparatus of claim 1, wherein (b) comprises:

See Claim 1 above.

[2.2] creating at least one page table; and

“Virtual system mode logical addresses below 0×ff000000 will be translated to physical addresses by the current page table if paging is enabled (protected mode).” (Ex. 1002, p.11, 3:42-45) (emphasis added). See also Ex. 1014, p.32-33, ¶97.

[2.3] invoking a paging feature of the processor.

In addition, “[Claim] 8. The processor of claim 7, wherein said memory management unit further includes a selectably enabled paging unit and wherein if paging is enabled said memory operand is translated into a physical address and if paging is not enabled said memory operand is translated into a linear address.” (Ex. 1002, p.20, 22:11-15) (emphasis added).

49


“The memory management unit 124 contains the logic necessary for address generation and protection checking and includes a segmentation unit and a paging unit. These functions will be described in more detail below.” (Ex. 1002, p.11, 4:63-67) (emphasis added). See also Ex. 1014, p.33, ¶98-99.

In light of the foregoing, Wooten 1 teaches all elements of the challenged

claims 1 and 2, rendering each of them anticipated. Moreover, as Claim Chart I

illustrates, there is considerable overlap in the elements of the independent claims

1, 11 and 21, as well as dependent claims 2, 12 and 22. In an effort to avoid

redundancy, Petitioner shows that the preambles [11.P] and [21.P] are each taught

for the same reasons discussed regarding Wooten 1 and claim [1.P]. Claim

elements [11.1] and [21.1] are each taught in the foregoing analysis of [1.4]. [11.2]

and [21.2] are each taught for the same reasons as discussed in [1.5]. [11.3] and

[21.3] are each taught in the analysis of [1.6]. [11.4] and [21.4] are each addressed

in relation to [1.7]. [11.5] and [21.5] are each addressed in relation to [11.8].

[12.1] and [22.1] are each addressed in the foregoing analysis of Claim 11. [12.2]

and [22.2] are each addressed in the analysis of [2.1]. [12.3] and [22.3] are each is

shown in the analysis of [2.2]. For these reasons, claims 11, 12, 21 and 22 are

anticipated for the same reasons shown in relation to claims 1 and 2 in Chart III

above. (Ex. 1014, p.33-34, ¶¶100-103).

50


F. Ground 6: Collins, the Pentium Manual and the Intel

Architecture Software Developer’s Manual render claims 5-10, 15-20 and 25-

30 obvious.

Ground 6 adds the Intel Architecture Software Developer’s Manual Volume

3: System Programming Guide (the “ASDM”) to Ground 1 in order to demonstrate

the obviousness of additional claims 5-10, 15-20 and 25-30. (Ex. 1013). The

ASDM “describes the architecture and programming environment of all Intel

Architecture processors.” (Id. p.25). The ASDM “pertain[s] primarily to the 32-

bit Intel Architecture processors, which include the Intel386™, Intel486™, and

Pentium® processors[.]” Id. As such, it would be obvious to combine the

teachings of the ASDM relating to SMM, protected mode, virtual mode and related

memory conventions with Collins and the Pentium Manual, two other references

illustrating similar architectural features and capabilities of the Pentium processor.

(Ex. 1014, pp.58-59, ¶165 and p.68, ¶190).

The ASDM teaches instances of SMM where the processor should be

configured to protected mode, per element s [1.4], [11.1] and [21.1]. “In some

instances (for example prior to powering down system memory when entering a 0-

volt suspend state), it is necessary to save the state of the FPU while in SMM. Care

should be taken when performing this operation to insure that relevant FPU state

information is not lost. The safest way to perform this task is to place the processor 51


in 32-bit protected mode before saving the FPU state.” (Ex. 1013, p.347)

(emphasis added). In terms of elements [1.4], [11.1] and [21.1], the ASDM also

describes relocating SMRAM to an address above 1 MB, and running SMM code

above 1MB. (Id., p.350 at §11.11.1). ASDM also teaches the elements of

numerous dependent claims, as shown more fully below.

Claims 3, 13 and 23: To claims 1, 11 and 21, respectively, Claims 3, 13 and

23 each add the step of instructions for creating a page table prior to entry into

protected mode. (Ex. 1001, p.16, 8:51-53, p. 17, 9:57-58 and p. 17, 10:54-55)).

The ASDM teaches the creation of a page directory and at least one other page

table before the processor can be switched to protected mode. (Ex. 1013, p.266).

Thus, these claims are obvious. (Ex. 1014, p.69, ¶192).

Claims 4, 14 and 24: Claims 4, 14 and 24, which depend from claims 1, 11

and 21, respectively, each add the step of performing a near jump to a second

location and configuring the processor to operate in a protected mode. (Ex. 1001,

pp.17-18, 9:53-57, 10:58-61 and 11:57-61). Of course, elements [1.4], [11.1] and

[21.1] already teach configuring the processor to operate in protected mode. To

this, the ASDM teaches performing a near jump to a second location upon enabling

paging. (Ex. 1013, p.506 at §17.22.3). Thus, these claims are obvious. (Ex. 1014,

p.69, ¶193).

52


Claims 5, 15 and 25: Claims 5, 15 and 25 depend from claims 1, 11 and 21,

respectively. Claims 5, 15 and 25 each add the same three additional limitations,

each of which is taught by the ASDM.

First, claims 5, 15 and 25 “determine if control should be transferred to

instruction sequences for executing a task that requires the processor to be

configured to operate in protected mode.” (Ex. 1001, p.17-18, 9:59-67, 10:62-67

and 11:62-67). The ASDM teaches this when it states “In some instances (for

example prior to powering down system memory when entering a 0-volt suspend

state)[.]” (Ex. 1013, p.347) (emphasis added). This is a deterministic approach to

identifying which tasks are safely performed in protected mode. The reference to

“some instances” suggests other instances where it is unnecessary to switch to

protected mode before task execution. However, where the task in question is

saving the state of the floating point unit (FPU) before a power down of system

memory, it would be obvious based on the teachings of the ASDM to require entry

into protected mode before saving the state of the FPU.2 (Ex. 1014, p.70, ¶¶195-

196).

2 A POSITA would recognize that “real or protected mode device drivers” in the

6x86 Manual (Ex. 1012, p.94-95 at §2.9.5), are examples of SMM tasks suitable

for execution by an SMI handler while in protected mode. (Ex. 1014, p.70, ¶197).

53


Secondly, claims 5, 15 and 25 state that if it is necessary to enter protected

mode to execute a task, then the next step is “configuring the processor to operate

in the protected mode, and executing the instruction sequences for executing the

task[.]” (Ex. 1001, p.17-18, 9:59-67, 10:62-67 and 11:62-67). In Ground 1,

configuring the processor to protected mode is shown in element [1.4]. The

ASDM adds that saving the FPU state (the execution of instruction sequences) will

“place the processor in 32-bit protected mode as described in Section 8.8.1.,

[‘]Switching to Protected Mode[‘].” (Ex.1013, p.348). (Ex. 1014, p.71, ¶198).

Finally, claims 5, 15 and 25 state “otherwise to continue to process the

instruction sequences stored.” (Ex. 1001, p.17-18, 9:59-67, 10:62-67 and 11:62-

67). Here, the reference to “some instances” in the ASDM signifies that there will

be instances where it is not necessary to enter protected mode, in which case the

SMI handler continues to operate uninterrupted. (Ex. 1014, p.70, ¶196).

Therefore, these claims are obvious. (Id., p.71, ¶199).


respectively. Each of these claims adds common limitations. (Ex. 1001, pp.17-18,

9:3-13, 10:6-16 and 11:6-17). First, these claims add a step to “determine if

execution of instruction sequences pertaining to system management activities

have been completed[.]” Id. In computer science, each sub-routine executes until

54


it is determined that execution of instructions pertaining to sub-routine's area of

processing have been completed. (Ex. 1014, p.72, ¶201).

The claims further state that if system management activities have been

completed, “configuring the processor to disable operation in the virtual mode,

configuring the processor to operate in the protected mode, and configuring the

processor to disable paging; otherwise continuing to execute instruction sequences

pertaining to system management activities.” (Ex. 1001, pp.17-18, 9:3-13, 10:6-16

and 11:6-17). The Intel Pentium Manual’s state transition diagram shows how to

disable operation in virtual mode by setting VM bit to 0. (Ex. 1005, pp.499-500;

see also Ex. 1014, p.72, ¶202). The ASDM section “15.2.6. Leaving Virtual-8086

Mode” describes leaving virtual mode in greater detail. (Ex. 1013, pp.446-447).

Figure 15-3 illustrates returning from virtual mode to protected mode. Id., p.445).

The ASDM teaches disabling paging. "Paging (bit 31 of CR0). Enables paging

when set; disables paging when clear. When paging is disabled, all linear addresses

are treated as physical addresses." (Id., p.49) (emphasis added). A POSITA would

recognize that once a v86 task is completed, paging can be disabled by clearing

paging bit in CR0. (Ex. 1014, p.72-73, ¶202). The analysis above in relation to

claims 5, 15 and 25 shows the teaching of otherwise continuing to execute

instruction sequences pertaining to system management activities. (Id., p.71,

¶199). Thus, claims 6, 16 and 26 are also obvious. (Ex. 1014, p.73, ¶203).

55


Claims 7, 17 and 27: Claims 7, 17 and 27 depend from claims 5, 15 and 25

respectively. Each claim adds two steps: to “restore the processor's context in

memory; and return to a calling function.” (Ex. 1001, p.17-18, 9:14-17, 10:17-19

and 11:18-21). The ASDM teaches these elements. “The RSM instruction restores

the processor’s context by loading the state save image from SMRAM back into

the processor’s registers. It then returns program control back to the interrupted

program.” (Ex. 1013, p.339 (emphasis added); Ex. 1014, p.73-74, ¶205).

Therefore these claims are obvious. (Ex. 1014, p.73-74, ¶205).


respectively. Each claim adds these steps: “delete at least one page table; [ ]

restore the processor's context in memory; and [ ]return to a calling function.” (Ex.

1001, pp.17-18, 9:18-23; 10:19-23 and 11:23-12:3). In the ASDM, when paging is

disabled, all linear addresses are treated as physical addresses. Ex. 1013, p.49). A

POSITA would recognize that disabling paging necessitates deletion of paging

data structures (including page tables), to wit, releasing (deallocating) memory

used by the data structure into a pool of available memory. (Ex. 1014, p.74, ¶207).

Deallocation of memory consumed by a data structure (such as page tables) once it

is no longer needed was a common practice in the art at the time of invention. Id.

The remaining features of these claims are addressed above in relation to claims 7,

17 and 27. Therefore, these claims are also obvious. Id.

56


Claims 9, 19 and 29: Claims 9, 19 and 29 depend from independent claims

1, 11 and 21, respectively. These independent claims are addressed in Ground 1.

Claims 9, 19 and 29 each add the following steps to the independent claims:

“determine if execution of instruction sequences pertaining to system management

activities have been completed; and if so, configuring the processor to disable

operation in the virtual mode, configuring the processor to operate in the protected

mode, and configuring the processor to disable paging; otherwise continuing to

execute instruction sequences pertaining to system management activities.” (Ex.

1001, pp.17-18, 9:24-35, 10:24-33 and 12:4-16). The ADSM teaches these

additional elements, as discussed above in relation to claims 6, 16 and 26. For this

reason, these claims are also obvious. (Ex. 1014, p.75, ¶209).

Claims 10, 20 and 30: Claims 10, 20 and 30 depend from claims 9, 19 and

29, respectively. Claims 10, 20 and 30 each add the following steps: to “restore

the processor's context in memory; and return to a calling function.” (Ex. 1001,

pp.17-18, 9:36-39, 10:34-36 and 12:17-20). The ADSM teaches these additional

elements, as discussed above in relation to claims 7, 17 and 27. For this reason,

these claims are also obvious. (Ex. 1014, p.75, ¶211).

G. No Secondary Conditions Exist

As explained in Grounds 1-6 above, the prior art renders obvious the claims

of the 604 Patent. No secondary indicia of non-obviousness having a nexus to the

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putative invention of the 604 Patent exists that is contrary to that conclusion.

Petitioners reserve their right to respond to any assertion of secondary indicia.

FEES (37 C.F.R. § 42.103)

Pursuant to 37 C.F.R. § 42.15(a), the undersigned provides an online credit

card payment of the petition fees ($9,000 request fee; any excess claim fee; and

$14,000 post-institution fee). The undersigned further authorizes payment for any

additional fees (or fee deficiency) that might be due in connection with this

Petition to be charged to the Deposit Account 506541 (Customer ID No. 87296).

CONCLUSION

This Petition demonstrates “a reasonable likelihood that the petitioner would

prevail with respect to at least one of the claims challenged in the petition.” 35

U.S.C. § 314(a). Because all elements of the challenged claims 1-30 of the 604

Patent are taught in the prior art as explained in the detailed proposed Grounds for

Unpatentability, Petitioner requests inter partes review of these claims, and the

ultimate cancellation of the challenged claims.

Respectfully submitted,

HILL, KERTSCHER & WHARTON, LLP,

/Vivek Ganti/

Vivek Ganti (Registration No. 71368)

Lead Attorney for Petitioner

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-and-

/Gregory Ourada/

Gregory Ourada (Registration No. 55516)

Backup Attorney for Petitioner

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CERTIFICATION OF SERVICE

The undersigned hereby certifies that the foregoing Petition and supporting

materials (Exhibits 1001-1015 and Powers of Attorney) was served via Federal

Express on April 21, 2015, in its entirety on the following:

Patent Owner’s correspondence address for U.S. Pat. No. 5,987,604 Kinglite Holdings, Inc. 7 Temasek Boulevard #15-01A Suntec Tower One Singapore 038987 Omikron IP Law Group 16325 Boones Ferry Rd. Suite 204 Lake Oswego, OR 97035 Counsel of record for U.S. Pat. No. 5,987,604

Loren H. McRoss Phoenix Technologies, Ltd. 915 Murphy Ranch Rd Milpitas, CA 95035 -and to counsel for Patent Owner in the concurrent litigation matter involving U.S. Pat. No. 5,987,604: Rolf O. Stadheim, George C. Summerfield, Kyle L. Harvey, Robert M. Spalding and Christopher H. St. Peter STADHEIM & GREAR LTD. 400 N. Michigan Avenue Suite 2200 Chicago, Illinois 60611

60


HILL, KERTSCHER & WHARTON, LLP

/Vivek Ganti/ Date: April 21, 2015 Vivek Ganti (Registration No. 71368)

Attorney for Petitioner 3350 Riverwood Pkwy, Suite 800 Atlanta, GA 30339 (770) 953-0995

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Documents

By: Vivek Ganti ([email protected]) Reg. No. 71368 UNITED ... · Petition for Inter Partes Review of U.S. Pat. No. 5,987,604 F. Ground 6: Collins, the Pentium Manual and the Intel Architecture