Business & Technical News from Unaxis Semiconductors

Business & Technical News from Unaxis Semiconductors

August 2003 | Issue

Introducing the New VERSALINE™

The Photomask Future has Arrived with MASK ETCHER IV®

10 BEST Award Fourth Year Running

cont

ents

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Unaxis Insights

Unaxis on the Path to Business Excellence 2

Customer Complaint Management at Unaxis Semiconductors 3

Feature

Let There be Light!An overview of one of the chip industry’s fastestgrowing markets – high brightness LEDs. 5

Advanced Silicon

65 nm Dry Etch: the Photomask Future has ArrivedThe Unaxis Semiconductors Photomask business unit has developed new etch technology focused on the 90 nm and 65 nmtechnology nodes. 10

Advanced Packaging

3D IntegrationThe packaging technology for tomorrow’sperformance needs. 14

Compound Semi&Microtechnology

AIN Films for Bulk Acoustic Wave Devices 18

Introducing the VERSALINE™Low cost of ownership for high volume etching&depsition 22

RF MEMS Analysis, Forecasts and Technology Review 26

VCSELs to Revolutionize Fibre OpticCommunications 30

Index 33

14

22The new VERSALINE™operator interface

Unaxis Sputter ToolCLUSTERLINE®

5High performanceLED headlights fromOsram OptoSemiconductors

www.semiconductors.unaxis.com

Unaxis Insights

Front CoverClose-up view of self-aligningbuffer interfacestation on theMASK ETCHER IV®

Editor in ChiefJuerg Steinmann, Global Communications Manager Unaxis Semiconductors

Executive EditorMarion Turner, U.S. Marketing Communications Manager Unaxis Semiconductors

Managing EditorVeronika Schreyer, is design

Design /LayoutCactus AG

PhotographyMichael Reinhardand Unaxis, unless stated otherwise

Published byUnaxis Semiconductors P.O. Box 1000FL-9496 Balzers Liechtenstein

Printed bySüdostschweiz Print AG

If you have any questions or comments, please contact us at [email protected] or fax back the reply card provided in this magazine.

Chip, the Business & Technical News from Unaxis Semiconductors,is also available online at:www.semiconductors.unaxis.com

Kenneth T. BarryPresident, Unaxis Semiconductors

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Unaxis Chip

Welcome to Chip 9!

Since joining Unaxis Semiconductors in April, we have been analyzing and evaluating

the current market conditions, and how we need to reposition ourselves to become

even more competitive. We have developed a comprehensive strategy to ensure our

readiness with the right products and services for you, our customers.

I am pleased to announce the VERSALINETM, a new, leading edge deposition and

etching tool dedicated to volume production for compound semiconductors, MEMS

and thin film head applications (pages 22–25). Our new MASK ETCHER IV® system

gained strong acceptance at Semicon West in July. Please be sure to read about our

ground-breaking concept in ICP dry etch technology enabling 65 nm photomask

production (pages 10–13).

Reinforcing our commitment to improve the quality of our products and services,

our St.Petersburg technology center received ISO 9001 and ISO 14001 certifica-

tions in June of this year (page 2). I would like to extend my sincere appreciation to

you for your positive feedback, which enabled our winning of the VLSI "10 Best”

award in the category of semiconductor equipment suppliers for the fourth

consecutive year ("Unaxis Semiconductors around the Globe” insert before page 5).

At Unaxis Semiconductors, we continue to seek emerging and leading edge

technology opportunities – one being the solid state lighting market. This market

shows great potential in the coming years and is featured on pages 5–9. Another new

and promising development is 3D integration, the packaging technology for

tomorrows’ performance needs (pages 14–17).

I look forward to meeting you at future semiconductor shows and events.

Meanwhile, if you have any specific requests, or would like more information on

our technologies or Unaxis Semiconductors in general, please email me at

[email protected] or use the reader reply fax inserted after page 20. I hope you enjoy

reading this new edition of Chip!

Sincerely,

Kenneth T. Barry

2 | Chip Unaxis

Unaxis InsightsUnaxis InsightsUnaxis Insights

implemented a powerful managementsystem as the backbone for futuresuccess and innovation.

The wide span of business processesfrom R&D, sales, engineering, supplychain, assembly, and customer service is well defined and also well supportedwith the relevant and necessary tools andinstruments. One remarkable aspect in thetotal added value chain, from the basicdevelopment to the servicing of theproduct installation at the customer site, is the very high qualification level of allemployees involved.

To maintain or even enhance thisstrategic success factor, the present effort

of skill management will be kept at alllevels of the company.

By unanimous decision of all partiesinvolved, a routine inspection by the SQSauditor will be carried out again in April2004. We are looking forward to the daywhen we will be able to present all thevaluable improvements achieved by“Creating outstanding customer value”(Unaxis USA, Inc. mission statement).

For more information please contact:[email protected]

Unaxis USA, Inc., St.Petersburg has nowreceived high honors from the SwissAssociation for Quality and ManagementSystems SQS (Swiss Association forQuality and Management Systems), therecognized qualification body for ISOstandards worldwide.

Unaxis USA is the headquarters of theglobal Unaxis Semiconductor Division.Besides the production site located inTruebbach, Switzerland, where there hasbeen an SQS-certified ISO 9001:2000management system since March 2002,Unaxis USA is also a major production site employing a total of 199 employees.Both the Corporate Environment Manager,Martin Hollenstein and the DivisionBusiness Excellence Coach, MarkusBaerlocher were instrumental in thesuccessful definition, setup and implementation of the integrated ISO9001:2000 and ISO 14001:1966management system. Unaxis USA, Inc. is the first legal entity in the division to apply and maintain an environmentalmanagement system according to the ISO 14001:1996 standard.

This outstanding step on the stairway to excellence was possible due to the factthat all personnel at Unaxis USA, Inc.participated as a team. Supported activelyby their Operation Manager, Wayne Pasco,and lead through the specifics of standardsby James Coughlin, Quality Manager, andBill Strand, Environment, Health and SafetyManager, the organization has now

Customer Value – Unaxis on the path to Business Excellence

Markus BaerlocherUnaxis Semiconductors

Unaxis Insights

Unaxis Chip | 3

Customer loyalty develops throughsustained satisfaction with the product or service of a company. This can includeeverything from sales commitments,technical support, product reliability to the delivery of spare parts. Should anypart of the business process break down,the customer’s loyalty is put to the test.Customer support experts tell us that,despite an occasional failure, customerswill remain loyal – if their problems aredealt with quickly and effectively.

Our customer’s opinion countsIn 2002, an independent survey measuredthe level of satisfaction among Unaxis’customers. The Customer Opinion Surveylooked at performance areas such asspare parts, sales representation,customer relationship, service engineeringand complaint management. The resultsshow customers’ overall satisfaction levelas satisfied, however, as always, there is room for improvement. The analysis of our weak points showed customerswere concerned with the way UnaxisSemiconductors handles complaints. The whole process of complaintmanagement needed to be reviewed –from finding a competent person tosubmit the complaint to, the processing of a complaint, to the way in which thecomplaint is settled.

Improving the processTo improve the existing complaintmanagement process and take correctiveactions regarding the comments from the customer survey, we analyzed theprocess to address the handling ofcomplaints. The effort to develop andimprove this process involved theinteraction of many departments withinUnaxis Semiconductors and input frommany colleagues around the globe. Driven by the ISO 9001: 2000 system, we looked for the right process with aclosed loop for continuous improvement.To be effective in handling complaints weneeded a way to categorize them toensure the complaint resided with theproper owner. Customer complaints arenow part of the overall ComplaintManagement Process (Figures 1 and 2).

The Customer Complaint Managementprocess is a 10-step process starting with

Unaxis Insights

Customer Complaint Managementat Unaxis Semiconductors

Complaints

Cus

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er

Cus

tom

erCustomerComplaintsC1

ServiceNotificationS1

InternalComplaintsQ3

Complaintsto SuppliersQ2

PeriodicalFailure AnalysisImprovements




Complaint Mangement Process Complaint

Improvement

Immediate/corrective/preventive actions

Periodical problem analysis and improvement

Evaluation ofdatabase

Semiconductors

“One key area, where customers are testing yourcommitment towards customer satisfaction andloyalty, is the management of customer complaints.It is not so much the fact that a complaint can arise,but rather the professionalism in how the complaintis handled that makes the difference.” Robert van der PuttenVice President, Customer Support, Semiconductor Division

Dave AbremskiUnaxis Semiconductors

Figure 1: Complaint Management overview

4 | Chip Unaxis

Unaxis Insights

an easy access template located on theUnaxis Intranet (Figure 3). All Unaxisemployees who interact with customersare trained on how to access and use this template. On completion of the template, a confirmation number for the complaint is generated. This confirmation number automaticallytriggers a notification to the appropriatecustomer complaint manager who is

responsible for contacting and assigning a complaint owner. Once the complaint is entered into SAP, it can be processed,tracked, measured and managed tocompletion. Getting there wasn’t easy.Coordinating many departments withinUnaxis and input from colleagues aroundthe globe made it happen.

To keep a focus on any open complaints,scheduled review and status update

meetings have been scheduled withsenior management. During these reviewscomplaints can be escalated to providethe necessary resources in order to bringcomplaints to completion.

The Customer Complaint process isalready in place and utilized in the UnitedStates and Europe. The remainder of the Semiconductor Division is currentlybeing trained, with a complete globalrollout by the end of 2003. Measurementscollected in SAP are used as key data for further improvements and areconstantly being implemented. Ifcustomer satisfaction creates customerloyalty, then the Unaxis CustomerComplaint process is a means to achieve that satisfaction.

For more information please [email protected]

CustomerComplaint

Customer satisfied withresolution to complaint

Key AccountManagement

Logged intoSAP

LocalComplaint Manager

Sourcing CenterComplaint Manager

Assign to ComplaintOwner

Verify effectiveness of the process (KPI-B/W)

Engineering CustomerSupport

Supply ChainManagement others

2nd level

Customer complaint: Any verbal or writtenexpression of dissatisfaction by a customer –whether justified or not – caused by Unaxis notmeeting his/her expectations, specifications,needs, or requirements is defined as acustomer complaint.

Goals and principles of customer complaint management Any Unaxis employee can generate a

customer complaint. Single point of contact by division, subsidiary,

and sourcing center. Every complaint has an assigned problem

owner. The customer is involved in defining an

agreeable solution. Constant status overview is available. The process allows for escalation to apply

the required resources. Response and resolution time are measured

and recorded. The complaint data is analyzed and used

for continuous improvement.

Figure 2: CustomerComplaint process

Figure 3: Customer Complaint input template

Unaxis Chip | 5

High brightness (HB) LEDs show up in themost unexpected places these days –sewn into ballet dancers’ costumes, spapools and hotel lobbies. The burgeoningof applications and new uses for bright, cool light sources is an echo of the boomwhich occurred when transistors replacedvacuum tubes.

Manufacturers have improved illumination power to the point that evenmachine vision equipment suppliers have adopted HB-LEDs as part of thesystems used to inspect plastic cards, cell phones, semiconductors and surfaces for defects.

Volpi AG, a global leader in themanufacture of “cold light” sources formachine vision, microscopy, and otherspecialized applications has been usingexpensive fiber optics for the illuminators it sells to Siemens, Nokia, Solistic, andMartin Marietta.

By adopting HB-LED technology, it was able to introduce a new line of highmargin products. “Some of our new

products are only possible thanks to HB-LEDs,” says Michael Friedrich, marketingmanager.

It is easy to see why the 50 year old firm is an early adopter of the technology.“We’ve been able to develop newproducts and new applications. Theirreliability gives our customers atremendous advantage, with 35,000 to 70,000 hours of lifetime before the need for replacement,” says Friedrich.

A compelling market opportunityLongevity and low power consumption are just some of the drivers of the multi-colour LED market, now worth about $2 billion a year.

Machine vision and architectural lightingare the niche markets at the moment,representing about 5% of the market,according to market researchers. By far,

the handheld device sector is the largestwith 40% market share. It also has thegreatest growth potential in the short run,according to the latest data from IntertechCorporation, a high tech consulting firmbased in Portland, Maine.

LEDs as backlights in LCD monitors areanother large potential market. It grew by105% to 32.2 million units in 2002.

Sales growth rates are about 50% peryear. Typical applications are traffic lightsand signage, as well as the handheldelectronic market, consisting of mobilephones (a market that grew from 400million units shipped in 2001, to 420 millionunits in 2002), PDAs and cell phone/camera combinations, as well as portableentertainment devices.

Earlier market forecasts of a $3 billionmarket by 2006 may have been “toocautious”, according to Intertech.

Feature

Behind the surprisingly low-profile headlights on a futuristic sports car are high-performance LEDs from Osram Opto Semiconductors. The study by top Italiandesigner Pininfarina was presented at the 73rd International Geneva Car Show.

An overview of one of the chip industry’s fastest growing markets –high brightness LEDs.

Valerie Thomson, Technical Journalist, Zurich

“By 2005, LEDs will begin to make significant inroads into markets for indoor/outdoor lighting, automotive interior/exteriorlighting, shipboard lighting, gaming machines, and toys,” Dr. Robert Steele, Strategies Unlimited

Feature

6 | Chip Unaxis

Many are hoping the LED demand will get a big boost by the Kyoto agreement,which the European Union is expected to translate into a law requiring all lightsto change from magnetic to electronicconverters. US energy research has alsodemonstrated the HB-LED’s environmentefficiency.

A short history of LEDsGeneral Electric developed the first practicallight-emitting diode. Steady evolutionbased on optimizing efficiency ensued.

Over time, Hewlett-Packard developedthe market for using HB-LEDs in red trafficlights and automobile brake lights.

A breakthrough came in the early ninetieswhen Nichia and the Japanese researcher,Shuji Nakamura, pioneered processes forreliable multi-coloured LEDs, eventuallydeveloping a low power, blue spectrum LEDand laser diode which enabled the rapidreplacement of traditional green, blue,violet, ultraviolet and white light sources.

Blue LEDs proved remarkably popular in electronic devices around the world, as well as in automotive applications, led primarily by Osram Optical Semiconductor’s efforts.

The energy saving features of HB-LEDshas become a big attraction. Aixtron wasnamed to the Dow Jones SustainabilityIndex and is now held in a number ofprofessionally managed investment fundportfolios because of its environmentallyfriendly stance – its equipment can be used to make solar cells and supportsmanufacturing energy saving lights, lasersand screens.

The technology leading lightsWhen it comes to materials, compoundsemiconductor processes such as GaN

dominate, particularly for blue, green, and white LEDs. Since 1999, the market for GaN devices has grown by 221% to$1.35 billion.

The main players today are Nichia,Toyoda Gosei, Cree, Lumileds and Osram.

The industry is expanding as host ofnewcomers from Taiwan enter the market,adding Steele, including UEC, Epistar,Formosa Epitaxy, South Epitaxy andHighlink. “There is a growing interest fromTaiwan,” agrees Notker Kling, UnaxisSemiconductor’s VP of Compound Semiand Microsystems business unit.

The manufacturing process that turnsGaN-based materials into blue spectrumlight is called MOCVD (metalorganicchemical vapor deposition). “There are two main suppliers of these platforms,Emcore and Aixtron”, says Ann McDonald,a veteran chip industry editor and founder of CompoundSemi News.

Fierce competition between the twohelped to accelerate the manufacturing ofhigh brightness LEDs and blue laser diodes.

Orange and red toned devices are madein InGaAlP. Lumileds and Toshiba, as wellas Osram are leading the way, she says.

Feature

Mobile phone camerascan be equipped withLED flash to replaceconventional dischargelamps. With an LED the light flash isimmediate, no need to wait for the bulb to charge up again.

Unaxis Chip | 7

Feature

The art of making lightThe fabrication of HB-LEDs requires the understanding of optical properties ofthe materials used, how to manipulate thinfilms, substrates, as well as packaging, inorder to achieve high efficiencies.

“It is still quite an art to manufacture the devices. It’s a complex process,” says Dr. Steele from Strategies Unlimited.“In addition, the substrate size is still small.It is still all 2 inch wafers.” Many have tried and failed. “There’s a lot of know-how required, plus there are a lot ofpatents, which can prove to be a minefieldfor innovators,” adds Steele.

While companies such as Aixtron and Emcorehave become industry standards for the epitaxial material growth required to make GaNLED structures, Unaxis’ SHUTTLELINE system has become important for device productioninvolving dry etching and PECVD processes.

Obtaining brighter LEDs at acceptable costsrequires high performance fabrication processes. Although device geometries are notcritical for the new HB-LEDs, the materials being dry etched do present significant challenges. As an emerging technology, there is a wide range of materials being included in devices which must be addressed.

These materials range from variouscombinations of III-V compounds, to dielectrics, to indium oxide. All layers must be either etched or deposited with high quality, stable processes to obtain high brightness devices.

The wrong systems or processes will affectperformance and costs. To avoid the low yields in the manufacturing process it is important thatprocesses be optimized. For example, the wrong etching process for GaN materials can

result in surface morphologies which include pits and pillars or profiles with an undesired shape.

The relatively small wafer size used in GaNproduction, 2" predominately and currently transitioning to 3", requires that dry etchingsystems support high throughput. Unaxis hasdeveloped an Inductively Coupled Plasma (ICP)technology which can handle sapphire and siliconcarbide substrates used for GaN devices.

The ICP technology is particularly adept atproviding the process flexibility for the manymaterials requiring dry etching while maintainingthe needed etching rates. Similarly, a PECVD batch system is available to support the throughput requirements necessary for deposition of high quality dielectrics such as SiNx and SiO2.

Unaxis has developed a tool which can provideeffective etching and deposition processes, while maintaining high yield and satisfying capacity requirements. Fitting into the batchproduction environment with a small footprint and low demands on facilities was also an essential requirement.

The Unaxis Semiconductors SHUTTLELINETM

has become important for GaN LED structures

Notker Kling, Unaxis Semiconductor’s VP ofCompound Semi and Microsystems businessunit, St.Petersburg, Florida

Concept vehicles‚ from the likes of Ford andVolkswagen, use white HB-LEDs in theheadlamps. They consist of a cluster of dozensof LEDs controlled by software to producevarious beam patterns. (Image courtesy of Barco)

8 | Chip Unaxis

The future is brightThe LED industry has its collective eye onthe $15 billion general illumination market.Eventually, solid-state lighting will replaceincandescent bulbs in most applications.

So far an effective white light at the right price is still elusive. An LED can now exceed the luminous efficiencies of incandescent light bulbs, greater than 30 lumens per watt, according toIntertech, but the total light output and cost per lumen has to improve to be competitive with existing lightingtechnologies.

Feature

Surprising low profileheadlights on a futureFORD truck

Valerie ThompsonMSc., has been a freelance business and high-tech writer for more than 10 years. A Canadian based in Zurich, she tracks the trends and developments of Europe’s purveyors of advancedtechnology.

Advantages of LEDs over conventional lighting

The best LEDs today are twice as efficient as incandescent bulbs, converting about 10 – 20% of the electrical energy to light.

LEDs have no moving parts, no fragile glassencapsulation, no mercury, no toxic gasses,and no filament. Hence, there is nothing tobreak, rupture, shatter, leak, or contaminate.

Unlike conventional light sources, LEDs arenot subject to sudden failure or burnout.

The top LED applications

Mobile appliances 40%

Signs 23%

Automotive 18%

Illumination 5%

Signals 2%

Other 12%

10 | Chip Unaxis

Current wafer scanners are able to print90 nm technology node features with new193 nm wavelength light sources. In fact,recent trends clearly show 65 nmtechnology node features will be possible,and some in our industry believe thatnovel optical adjustments to waferscanners (i.e., water immersion lenses) will allow this technology to extend to 45 nm feature sizes!

The photomask is expected to remainthe primary transfer medium for massproducing integrated circuit patterns. Wafer lithography now requires the use of newer photomask techniques, such as phase shift masks, in order to achievethe very small features demanded by the current International TechnologyRoadmap for Semiconductors (ITRS).

Now, more than ever before etchingbinary chromium (Cr) masks is theresolution-limiting step within themanufacturing process of advancedmasks sets. Unaxis Semiconductors hasbrought the 65 nm technology node within reach more than one year earlierthan predicted. We expect 90 nm nodetechnology masks to be prototypedbefore the end of 2003 and 65 nm masksto be prototyped by the third quarter of2004 – 12 months earlier than the mostrecent roadmap!

Developing a solutionFor more than 2 years, the UnaxisSemiconductors Photomask business unit has been developing new etchtechnology focused on the 90 nm and 65 nm technology nodes. This fourthgeneration (Gen 4) ICP system is quiteunique and will again allow our customersto push the limits of optical lithography.Gen 4 etch equipment will be mandatoryfor the photomask industry for a numberof reasons discussed in the followingpages.

Mask error budgetThree major manufacturing technologiesare utilized in the production ofphotomasks: Pattern generation (writingor exposure of the circuit patterninformation into a photo-sensitive resist on the mask blank), resist develop (wetchemical removal of resist in the exposedpattern areas on the mask blank) andabsorber etch (wet chemical or ICP dryetch of the photo-absorber material – Cr, MoSi, etc. – using the developed resist as an etch mask).

Each of these manufacturing processescontributes a portion of error to theformation of the actual vs. ideal patterninformation. Any pattern deviation istypically known as the mean-to-targeterror, where “target” describes the various

feature sizes and placement of the circuitpattern, as originally designed on thecomputer. The “mean” aspect describeshow the manufacturing process(es)altered those features and their placementon the final mask. Obviously, as featuressizes have continued to shrink, theallowable “mean-to-target” error budgethas had to shrink proportionately. This has posed a significant problem in generalfor all mask manufacturing processes, but has posed a particularly difficultproblem for the mask etch process asdescribed in the following paragraphs.

Pattern generationThe accuracy of exposure tools hasimproved significantly over the past 5 to10 years with smaller grid and beam sizes,enabling these tools to produce eversmaller features in the resist and placethose features in more closely controlledproximity. However, resist systems havenot evolved together with the beamplacement accuracy of the patterngenerators. In recent years, importantadvances in resist chemistry have been in the form of “fast” resists which can beexposed with low beam energy (e.g.chemically amplified resists). But, almostno advancement has occurred in resistmaterials as it pertains to final imageformation, resist thickness, feature

65 nm Dry Etch: the PhotomaskFuture has Arrived

Wafer dimensions continue to accelerate downward towards ever smaller features and the legendary Moore’s Law is still validfor current silicon devices. As wafer IC dimensions approach thephysical limitations of silicon physics, the lithography techniquesused to print these patterns on silicon become very difficult toperform.

Advanced Silicon

Michael D. Archuletta, Dr. Chris Constantine, Dr. Dave Johnson, Unaxis Semiconductors

Advanced Silicon

Unaxis Chip | 11

Advanced Silicon

Unaxis Chip | 11

sidewall angle, residue, and materialstability. The net result is pattern generatoraccuracy has improved substantially withregard to placement and overlay accuracy,but for overall feature fidelity (CDuniformity, feature resolution, feature sizelinearity, etc.), the pattern generatorscannot fully absorb their fair share of thesmaller error margin needed for the 90 nmtechnology node. With no new resistsystems foreseen, they cannot beexpected to absorb any further errormargin as we move into 65 nm technologynode mask making.

Resist develop The minimal evolution of resist systemsequates literally to zero advancement inthe method and accuracy of the resistdevelop. This process step has not andwill not be able to absorb any additionalreduction in error margin.

Cr etchIt should now be painfully clear that theonly manufacturing step left to absorb theever smaller error margin needed to meetthe 90 nm and 65 nm mask makingchallenge is the etch process. One of the foremost advances in absorber etch technology came from UnaxisSemiconductors in 1995 with ICP dry etchtechnology. Since that time, Unaxis hasintroduced three successive generationsof improved dry etch systems. Now, thecollapsing ITRS roadmap has forced us

once again to reduce the error tolerancesin our equipment technology.

Figure 1 illustrates the evolution of dryetch error margins required for keyperformance parameters at the varioustechnology nodes over the past eight years (Gen1– 3) and the error marginrequirement today and in the near future(Gen 4).

Dramatic performance improvements in dry etch system technology wererequired – and achieved by UnaxisSemiconductors during the past eightyears – to keep the mask industry in stepwith the lithography demands of thedevice designers. So far, we are on trackto continue this dry etch performanceimprovement trend.

Feature size resolutionWafer IC dimensions are becoming sominute, they are literally smaller than thewavelength of the stepper light used toexpose them on the wafer. As discussedearlier, one method of overcoming thisproblem is the use of special maskmaterials which provide half-waveattenuation or “phase shifting” of thestepper light. This produces exposures onthe wafer even smaller than the exposurelight wavelength. Another, more commonmethod of resolving features on the waferis to employ what are called “opticalproximity correction” (OPC) features onthe photomask. These are printed featureson the mask which are too small to resolveat the wafer level, but they do add light tothe edges and corners of very smallfeatures on the wafer. This “light assist”technique has been used effectively bypattern designers for many years.

What has become problematic for mask makers is as average feature sizedimensions decrease, OPC feature sizeson the mask are becoming too small toresolve. Figure 2 illustrates typical OPCfeatures on an advanced photomask for a 0.13 µm technology node device. Some of the OPC features shown are less than 200 nm wide. As we move to the 65 nm technology node, OPC featureswill shrink to less than 100 nm. Very high resolution dry etch is the only answer.

Advanced Silicon

Year Unaxis model no. CD uniformity CD linearity Etch bias (technology node) (3 sigma) (range) (average)

1995 MASK ETCHER I® (0.18 µm) 35 nm - N/A - - N/A -

1998 MASK ETCHER II® (0.15 µm) 25 nm - N/A - 80 nm

2001 MASK ETCHER III® (0.13 µm) 15 nm 20 nm 45 nm

2003 MASK ETCHER IV® (90 nm) 8 nm 15 nm 30 nm

2004 MASK ETCHER IV® (65 nm) 6 nm 8 nm 20 nm

Mask dry etch – key performance specifications

Figure 1: The evolution of dry etch error margins required for key performance parametersat the various technology nodes over the past eight years.

Advanced device patterning requires very high resolution imaging: e.g. optical proximity correction (OPC)

Figure 2: OPC serifson the photomaskadd light at theedges and cornersof a feature whenprinted on the wafer.

1322 UnaxisFinal Cr – initial resist

Iso clear 500 nm featuredeviation from average

30.00

15.00

7.50

–15.00

–30.00

Average: 26.223 Sigma: 23.14Max: 44.70Min: 17.00Range: 27.70

Figure 3: A highlyuneven pattern with > 99% Cr load in the window and < 1% Cr load on theremaining area

Figure 4: Gen 3 dryetch process showsvery large brightfield/dark field etchsignature disparity in the clear (window)vs. the dark (outer)area

12 | Chip Unaxis

Feature size linearityAnother challenge facing the photomaskindustry as geometries diminish is thevariety of small to large features on thesame pattern level that must be preciselysized. For technology nodes ≥ 0.15 µm, theaverage mask level would typically haveonly one primary feature that needed to besized as closely as possible to the originalcircuit design parameter. All other featureson that mask level, smaller or larger thanthe primary feature, could be slightly underor over-sized because their dimensionswere relatively inconsequential to the finaldevice performance. This is no longer thecase at 90 nm. For example, on a 90 nmmask, the primary design feature togetherwith its various OPC features must all becarefully sized to their original designcriteria because the margin for error on thewafer is so small. Figure 1 corroboratesthis new challenge. Note that in 1998, atthe 0.15 µm technology node, CD linearitywas not even a specified performanceparameter. However, by 2001, CD linearityappears as a mask etcher performancerequirement at less than half the total etchbias. This requirement continues to dropdramatically with each new technologynode.

Bright field/dark field linearityThe MASK ETCHER III® was an enormousbreakthrough for the mask industry. ThisGen 3 system was able to optimize theplasma etch of chromium films on glass sothat the uniformity for high load Crpatterns and low load Cr patterns are thesame. This was a major step forward forthe industry providing a large yieldimprovement for most mask shops. Thiswas during a time when most devicepattern layers were fairly uniform acrosseach mask, creating evenly distributedhigh or low chrome loads on differentmasks. However, as device geometrieshave grown smaller, device designs havegrown more sophisticated. Logic devicesnow have large imbedded memory cellsand memory devices have on-board logiccircuits. The net result of this circuitintegration are patterns with large opencells on the same layer, creating maskswith large areas of unevenly loadedchrome. In other words, mask makers arenow faced with high and low chromeloads on the same mask.

Figure 3 is a picture of the “Ybor” UnaxisSemiconductors dry etch test mask usedto emulate the high/low chrome loadconditions of an advanced mask layer.The test features are written in FEP171chemically amplified (E-Beam) resist.

There are 64 measurement sites coveringa 135 mm x 135 mm patterned area. Each site contains a variety of Iso/Denseand clear/dark features. This kind ofpattern layer is aptly named a “nightmare”mask level by the industry in general. Asdevice designs evolve, mask makers areseeing more and more of these advancedmask levels.

The desired etch for this type of masklayer is to achieve a very low total etchbias in both the clear field (window) andthe dark field (low Cr load area), while atthe same time producing a very low criticaldimension (CD) uniformity for the full rangeof feature sizes (feature size linearity). The Cr profile must be kept as close to90° as possible.

Why Gen 4?Until now, the required dry etch processimprovement has not been forthcoming tosupport the performance level needed for90 nm lithography. Over the past twoyears, the Unaxis Semiconductors Gen 3ICP source has proven itself to be themost advanced dry etch reactortechnology in the market; superior in allperformance categories to any othercompetitive tool. However, as good as itis, even to our Gen 3 ICP reactor thisasymmetrically loaded etch is a challenge.

Advanced Silicon

Ybor (1 window) test mask – Gen 3 etch signature

Unaxis Chip | 13

Advanced Silicon

Figure 4 is a box plot that gives apictorial representation of the dry etchcontribution across an Ybor (1 window)test mask (#1322) using a Unaxis Gen 3ICP source. The various box sizesillustrate the relative CD uniformity (of 0.5 µm features) across the maskbased on the amount of under or overetch of each feature from the average etch bias. The average etch bias appearsquite good, (26.22 nm) but the global CDuniformity is quite high (23.14 nm, 3 σ).After more than two years of processdevelopment, the dramatic chrome loaddistribution on this type of mask levelcontinues to pose a severe CD uniformityproblem for Gen 3.

Unaxis MASK ETCHER IV®

is the answerMore than eighteen months ago, weunderstood some very fundamentalconcepts need to be realized and a newetcher, Gen 4, needed to be developed in order to achieve the necessaryperformance improvements for 65 nmmask making. Utilizing a unique and veryadvanced plasma ICP concept (patentpending), even early Gen 4 resultsdemonstrated resist selectivity 2–3 timesnormal process conditions. Furthermore,Gen 4 incorporates a vastly improved

vacuum system and utilizes a radically newRF generator configuration which allows usto explore process areas which were notpossible with Gen 3. The proof of course, isin the process performance results.

Figure 5 is a box plot of the dry etchcontribution across an Ybor (1 window)test mask (# 1396) using a Gen 4 ICPsource. There is a notable absence of the etch disparity signature in the windowarea. The average etch bias is still quitegood (31.78 nm) but the global CDuniformity is now almost half (12.19 nm,3 σ), what was typical for Gen 3.

Figure 6 is a more complete summarycomparison of results for the two Ybortest masks #1322 and #1396. The

1396 UnaxisFinal Cr – initial resist

Iso clear 500 nm featuredeviation from average

30.00

15.00

7.50

–15.00

–30.00

Average: 31.783 Sigma: 12.19Max: 47.00Min: 24.60Range: 22.40

Figure 5: Initial Gen 4dry etch processshows almost nobright field/dark fieldetch signaturedisparity in the clear(window) vs. the dark (outer) area.

Ybor (1 window test mask – Gen 3 vs. Gen 4 dry etch data comparison summary

Measurement Gen 3 Gen 4feature size Etch results Etch results

Ybor (1 window) Ybor (1 window)test mask # 1322 test mask # 1396

300 nm – Iso ClearCD uniformity (3 σ) 23.1 nm 11.1 nm

CD bias (average) 22.4 nm 29.6 nm





Figure 6: feature size linearity: Gen 3 = 12 nm Gen 4 = 3 nm

summary includes measurement data for300 nm, 500 nm and 1500 nm featuresacross each mask. In each case, the C Duniformity from Gen 4 etch is vastlysuperior to the Gen 3 results. The totalfeature size linearity is in the 3 nm rangeacross the various feature sizes for the Gen 4 etch results; this is a 4ximprovement over the Gen 3 etch results.The high quality achieved with the MASKETCHER IV® (as depicted in Figure 5)represents a true breakthrough andliterally marks a new era in dry etchtechnology for mask making.


Ybor (1 window) test mask – Gen 4 etch signature

14 | Chip Unaxis

3D integration represents a system levelintegration scheme wherein specificcomponents (e.g. logic, memory, sensors,A/D converters, etc.) are fabricated onindividual, separate wafer platforms, andthen integrated onto a single chip-scaledpackage. This concept allows theintegration of otherwise incompatibletechnologies, and offers significantadvantages in performance, functionality,and form factor. That’s why, from atechnological perspective, this can beconsidered the merging of microsystemstechnology (MEMS), conventionalpackaging and wafer level packaging.

A continuing demand exists for lowercost electronic products offering eversmaller size, higher performance andincreased functionality. A significantportion of these improvements stem fromthe packaging and system-level integrationof logic, memory, and other functionaldevice ICs. Historically, advancements inelectronic packaging have concentratedon reducing the package size. Given thehigh cost of board real estate and theprogressive drive to system miniaturizationand cost reduction, the demand to furtherreduce the effective area used in chippackaging requires novel approaches. 3Dintegration, also known as chip stackingand system-in-a-package (SiP), eliminatesthe need for extraneous package areawhile offering significant performanceenhancements. The initial forays into 3Dpackaging were dominated by stacking ofchips while inter-chip interconnects were

established by extra-chip wire bonding.Other methods of stacking were performedby using bumped wafers – takingadvantage of higher performance shortlead interconnects – to connect from chipto chip. This required that wafers bethinned to allow efficient through-wafer viaprocessing to accommodate contact padson both sides of the chip. Yet anothermethod was used where connections were established over the edge of the die.

The latest approach to 3D stackingtechnology involves processing of fullwafers – employing either wafer-to-waferor die-to-wafer processing. Thesetechniques involve the transfer offunctional circuits from one wafer toanother and connecting multiple layers to form the 3D package, as shown inFigure 1. The technique for building 3Dpackages or 3D IC‘s is based on wafer (ordie) bonding and interconnect technology,while the interconnect is typically a verticalthrough wafer via interconnect. Waferthinning is a prerequisite which facilitatesthrough-wafer electrical connections andallows for sufficient heat dissipation; andalso ensures that multi stack devices willyield thin packages.

Companies ranging from IBM, Intel,Samsung, Micron, Infineon to startups likeZiptronix, Xanoptix and Tezzaron haverecently presented detailed products andprocesses that involve interconnection of heterogeneous devices by stacking dieon wafers or wafers to wafers. While duallevel stacking will fulfill the majority of theshort term needs, systems with up to fourstacked functional levels have beendemonstrated.

The primary advantages of a stackedpackage approach involve reduced size,weight, and power consumption; as well

3D IntegrationThe packaging technology for tomorrow’s performance needs

Advanced Packaging

Eric T. Eisenbraun, Ph.D., Albany NanotechDavid Lishan, Ed Ostan, Hans Auer, Unaxis Semiconductors

Figure 1: Three-dimensionalintegration concept

Passivation

Bond

Bond

Thinned substrate

Thinned substrate

Base substrate

Device Layer 3

Device Layer 2

Device Layer 1

Interconnect layer 3



Throughwafer

“Face-to-face”bond

“Face-to-back”bond

Advanced Packaging

Unaxis Chip | 15

as improved performance enabled by thereduction of inter-chip power, ground, and signal distribution line lengths. This significantly reduces signal propagationdelays associated with chip-to-chipelectrical signals.

Three-dimensional integration involvesfive key technologies: Wafer-to-Wafer Alignment Wafer Thinning Wafer Bonding Etching Metallization and Passivation

In particular, etching and metallization as well as passivation of three-dimensionalstructures involve significant challengesrelated to the large features (compared tofront end wafer processing), as well as theplurality of materials typically encounteredin the stack during via formation.

Etching for three-dimensionalstructuresWith respect to via etching, threedimensional integration structurestypically present a combination of materialsystems, often including silicon, siliconoxide, nitride, and polymeric bondinglayers. Moreover, these structures typicallyland on embedded metal structures. Thepresence of such a wide variety of materialsystems dictates the use of a flexibleetching platform with dedicated clusteredprocessing modules.

In order to preserve lateral chip realestate, the etching must exhibit nearvertical sidewalls with a minimum of taperthrough the bulk silicon layer(s), whichrepresents the thickest portion of thestack in non-SOI (Silicon-on-Insulator)approaches. Bosch etching employs a cyclical process of etching and

passivation of polymeric material, hasbeen successfully utilized in etching deepvertical vias through silicon, as shown inFigure 2. In addition, these applicationsdemand excellent etch selectivity involvingall layers in the stack in order to maintainetch depth control. This avoids significantoveretch and the associated potential forlateral etching of structures.

New deep silicon etching processeshave been released which extended theoriginal Bosch technology providing Sietch rates in excess of 18 µm/min for large vias of 100 µm, yet maintaining ratesin excess of 7 µm/min for small, highaspect ratio features. Typical processresults are shown in Table 1 and Figure 2.

Advanced Packaging

Figure 3: (a) SEM image of sidewall scallopsusing the conventional Bosch etchingprocess. (b) Smoother sidewalls, using theUnaxis DSE fast gas switching techniquewith an etching rate twice that of (a).

Figure 2: SEM image of a feature 30 µm wide and40 µm deep, etched at12 µm/min.

a

b

Table 1: Typicaletching rates forfeatures of variousdimensions

Feature dimension Depth etched Etching rate

2.5 µm trench 15 µm 8 µm/min

30 µm trench 40 µm 12 µm/min

100 µm trench 100 µm 18 µm/min

Additional development in the processgas switching technology from the etchcycle to the passivation cycle havedemonstrated the capability to producesidewalls with virtually no scalloping. Anexample of the smooth sidewalls possibleis shown in Figure 3.

New processes are also available forhighly productive etching of thick (>0.5 µm) SiNx and SiO2 layers as well as multi-layer oxide/nitride stacks. Etch rates of >0.5 µm/min have beendemonstrated. Non-photosensitive BCB(benzocyclobutene) resins are etched in standard fluorine-oxygen chemistriesand with processing capability to achieveanisotropic straight sidewalls. Fluorine isused in the etching chemistry to cleanly

16 | Chip Unaxis

remove the silicon present in the BCBstructure. Figure 5 shows etching of athick SiO2 layer.

These etching processes are achievedusing an ICP configuration with an RF biaselectrode. A photograph of the chamber is provided in Figure 4.

Metallization of three-dimensionalstructuresSputtering is the deposition method ofchoice for liner and seeding base layer as well as barrier layer metallization.Sputtered films are either formed ascomplete metal systems for redistributionpurposes or as plating bases, providing anadhesion/barrier layer plus a conductinglayer. The conducting layer is then used as the conducting base during the electrochemical deposition while theplating process also provides the filling of the via holes. However, the ability of sputtering to provide a continuous, robust layer is strongly dependent on the aspect ratio of the structure. While today’s interconnects used in wafer level packaging typically representaspect ratios of up to 3:1, higher packingdensity designs will likely require higheraspect ratios in the future. These needscan potentially be met by metal chemicalvapor deposition (CVD)-based

approaches, including atomic layerdeposition (ALD) processes such as are currently used in the front end waferlevel interconnect processes. Manymetallization steps, especially thoseinvolving less challenging aspect ratios,are expected to continue to employsputtering as the metal deposition methodof choice. This is due to its maturity andcompatibility to the majority of employedmaterials as well as the low cost ofownership. Typical parameters ofsputtering include: High deposition rate,good physical and resistivity uniformityand tight control over temperature and film stress (see also the CLUSTERLINE®

specifications).In particular, the use of polymeric

bonding/glue layers such as BCB presentan effective thermal constraint for all post-bond processing. In such cases the use oflow temperature (i.e., < 300°C) depositionprocesses is dictated. Sometimes CVDand ALD processes cannot be carried out

at such temperatures, and if they can, oftenyield films with less than optimal materialproperties. Accordingly, for theseapplications plasma-based CVD and ALDprocesses are under consideration, owingto their capacity to allow lower temperatureprocessing. Plasma processes also offerthe possibility of reaction pathways notaccessible via thermal processing, andinterruption of thermodynamically preferredgrowth routes.

One example of this concept involvesmetalorganic ALD processing of ultra-thintantalum-based films for copper barrierapplications. While “conventional”thermally activated processing using, for example, tert-butylimido tris-diethylamidotantalum (TBTDET) and NH3 as reactants yields highlyconformal films at low processing temperatures (~250°C), the resistivity

Advanced Packaging

LLS EVO specificationBatch sputtering system

Wafer Size: 2" to 200mmProcesses: Degas, Clean Etch and upto 5 PVD sources (DC, DC pulsed, RF)Typical film uniformities: <+/– 5%Typical clean etch uniformity: <+/– 15%Typical throughput: 4" – 40 wph /150mm – 14 wph / 200mm – 10 wph

Figure 5: Smoothsidewall SiO2 etchingwith hardmask orphotoresist processes

VERSALINE™process moduleshown with anelectrostatic waferchuck, providesetching capability for materials used in 3D integration.

Figure 4: Openchamber onVERSALINE™system

Unaxis Chip | 17

of these films is prohibitively high (i.e. >1000 µΩ/cm). By comparison, use ofthe same tantalum chemistry with a purehydrogen plasma counter cycle, instead ofNH3, yields films with much lower resistivity(~250 µΩ/cm), improved thermal stability,and more robust barrier performance.

Isolation/PassivationIn most applications of inter-waferintegration, electrical vias need to befabricated through silicon layers. Thispresents integration difficulties in that thesilicon layer is electrically active, leading to lateral wiring shorts. To prevent this, an insulating layer must be fabricated thatseparates the metal interconnect structurefrom the silicon layer. This is one of themost challenging passivation layers in thedesign, since it requires highly conformalfilms not just on the surface but also insidethe vias. Accordingly, PECVD and ALDtechniques are preferred for these c riticalapplications. SiO2 is the material of choice

for this insulating layer; although siliconnitride, alternate metal oxides (such asAl2O3), and spun-on dielectrics (polymericand inorganic) may also be considered.This decision is driven as much byintegration-specific considerations, aswell as the dielectric properties of theinsulator. As with the interconnectformation, ensuring the integrity of thebonding process demands stringentcontrol over the temperature of theisolation and passivation processing. This process also presents relatedchallenges, for example the selectiveremoval/cleaning of the dielectric from the via “floor” contacting to the underlying metal level.

In addition, dielectric passivation layers are required on the functional layersurface to accommodate for the variousrequired interconnect levels. For these

Advanced Packaging

CLUSTERLINE® specificationsSingle wafer sputter tool

Wafer Size: 150 to 300 mmProcess modules: Degas, ICP Etch and up to 5 PVD modules (total of 6 modules)Typical film uniformities: <+/– 5%Typical clean etch uniformity: <+/– 10%Typical throughput: 40 wph

Unaxis Sputter ToolCLUSTERLINE®

Dr. Eric T. Eisenbraunis currently an AssistantProfessor in theUniversity at Albany(UAlbany) School ofNanoSciences andNanoEngineering, and a Senior ResearchScientist at AlbanyNanoTech (ANT). Sincejoining UAlbany in 1998,Dr. Eisenbraun has been involved in various areas of thin film research formicroelectronic and hardcoatings applications.Prior to his currentposition, he was ChiefScientist for Metal CVD at Tokyo Electron (TEL)Massachusetts, andprior to this, he wasinvolved in thedevelopment of metalCVD processes at LamResearch Corporation. Dr. Eisenbraun receivedhis Ph.D. in Physics from the University atAlbany, and his B.S. inPhysics at RensselaerPolytechnic Institute. Dr. Eisenbraun has overthirteen years experiencein thin film processingand integration. He hasover 40 publications andone patent issued.

applications, sputtering as well as PECVDare considered to form these layers.

Summary Three-dimensional integration is a rapidly emerging technology thatpromises to provide substantial benefits in IC functionality and cost in a smaller,more efficient package. A wide variety of heterogeneous technologies can beintegrated with this technique, includinglogic, memory, analog circuits, andsensor/detector technologies. Thisapproach applies aspects of conventionalpackaging, on-chip interconnect, andMEMS technologies, and is expected to be applicable to a wide variety ofcommercial and military applications.


18 | Chip Unaxis


The key to the emerging FBAR (Film Bulk Acoustic Resonators) and SMR(Solidly Mounted Resonators)technologies is piezoelectric thin film,such as AlN (Aluminum Nitride). Devicesbased on the thin film BAW technologypromise very small sizes and better powerhandling capability than SAWs.

This article presents some importantprocess details regarding the AlNpiezoelectric films – especially results of film orientation, stress, roughness and uniformity.

AlN deposition technology Unaxis Semiconductors addresses theBAW market with the development of a specific system enabling both excellentfilm uniformity and quality. The capability of the CLUSTERLINE® 200 system, which already meets the high standards of the semiconductor industry regardingquality and impurity level, has beenextended to include the deposition of AlN and other piezoelectric layers. TheCLUSTERLINE® 200 system is equippedwith highly efficient gas conductionbackside heating capabilities for precisetemperature control up to 550° C. Otherspecification options are pulsed sputtering,RF sputtering and RF substrate bias.

For the last few years UnaxisSemiconductors has been developingreactive magnetron sputtering of variouspiezoelectric layers, coming up with anultra-high uniformity sputter source (Flexi-Cath) which enables a dynamicadjustment of the film thickness uniformity over the entire target lifetime.Excellent uniformity below 0.3% (1 σ)can be achieved (Figure1).

This technology is also easilyreproducible, as has been shown in a Unaxis application note [2].

AlN Films for Bulk Acoustic Wave Devices

Stanislav Kadlec and Eduard Kügler, Unaxis Balzers Ltd., Christian Lambert, Unaxis SPTec Ltd.

BAW (Bulk Acoustic Wave) devices, based on thin-film piezoelectric materials, represent a promising new technology for telecom applications and MEMS in the GHz range [1].

100908070605040302010

0–10–20–30–40–50–60–70–80–90

–100

X [mm]

0.3% – 0.5%

0.1% – 0.3%

–0.1% – 0.1%

–0.3% – –0.1%

–0.5% – –0.3%

–0.7% – –0.5%

–0.9% – –0.7%

–1.1% – –0.9%

–1.3% – –1.1%

AlN thickness [nm]Average 464.6Min 458.6Max 466.8St. Dev 1.15 3 sigma distribution 0.75%Min-Max range 0.88%

–100 –80 –60

–40 –20 0 20 40 60 80

100

Y [

mm

]

Figure 1: Example of AlN thickness distribution mapping on a 8-inch waferdeposited using FlexiCath. Thickness of the AlN film on a Si wafer is 0.46 µm. It was measured with a spectral Ellipsometer M200F from Woolam. The edge exclusion is 10 mm.

Compound Semi & Microtechnology

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.5 3.0 3.5 4.0 4.5 5.0

FWH

M A

IN (0

02) [

°]

Process 1

Process 2, wafer center

Process 2, r = 40 mm

Process 2, r = 60 mm

FWHM Pt (111) bottom electrode [°]

Unaxis Chip | 19


Crystalline orientationIt is well known for AlN as a hexagonalpiezoelectric material, that the c-axisorientation perpendicular to the wafersurface is crucial. Highly oriented films are necessary for devices with the best electromechanical coupling. In BAWapplications the process parameters as well as the quality of the bottomelectrode are critical for obtaining theadequate orientation of AlN film asillustrated in Figure 2. It shows the“rocking curve” width of the AlN (002)peak in XRD as a function of theorientation of the bottom electrode (Pt),expressed also as width of the rockingcurve. The platinum bottom electrode has been deposited on UnaxisSemiconductors equipment under various process conditions. The figurealso shows the orientation remains almost constant across the wafer radius.

AFM roughnessAlN surface roughness is an additionalimportant contributor to the device’sfunctionality. Figure 3 shows an example of an AFM scan (1 x 1 µm) of a 2.3 µm thick film. In this case, the RMS roughnessis just about 3.1 nm. With increasingtemperature the Pt film gets smoother, thus improving the roughness of the upper AlN layer.

Test resonator fabricationThe BAW technology needs are of course much broader than the AlNdeposition only. An example of a simpletest resonator is shown in Figure 4. Theacoustic mirror, all electrodes and the AIN layer itself have been deposited on the CLUSTERLINE® 200 system, using 8-inch wafers.

Figure 2: AlN orientationvs. Pt orientation,expressed as FWHM(full width at halfmaximum) of the XRDrocking curve measuredwith a Philips HRXRDinstrument. Two AlNdeposition processesare compared, “process 1” for 1 µmand “process 2” for 2.3 µm film thickness.

Figure 3: An exampleof an AFM scanshowing the AlNroughness, measuredin tapping mode with a Digital InstrumentsNanoscope.

Top Electrode

AIN

Resonator

Bottom ElectrodeAcoustic Mirror

300µm

~1.6µm @ 2GHz

Si wafer

AIAIN

Ti/Pt1.6µm

100µm

A A

Figure 4: A testresonator built as asolidly mountedresonator

20 | Chip Unaxis


Real (Y11) meas

Real (Y11) sim

Imag (Y11 meas

Imag (Y11) sim

Abs (Y11) meas

Abs (Y11) sim

0.2

0.3

0.4

keff 2 5.31%Q 434

– 0.2

– 0.1

Frequency [MHz]

– 50

– 45

– 40

– 35 20*l

og

(ad

mit

tanc

e) [

S]

0.1

Ad

mit

tanc

e [S

]

– 30

– 25

– 20

– 15

– 10

– 5

0

0.0

2,00

0

2,05

0

2,10

0

2,15

0

2,20

0

2,25

0

Figure 5: A typicaladmittance curve of test resonators in the 2-GHz range

–96

–78

–60

–42

–24 –6 12 30 48 66 84

9684

7260

48

36

24

12

0

–12

–24

–36

–48

–60

–72

–84

–96

Y [

mm

]

0.80% – 1.00%

0.60% – 0.80%

0.40% – 0.60%

0.20% – 0.40%

0.00% – 0.20%

–0.20% – 0.00%

–0.40% – –0.20%

–0.60% – –0.40%

Frequency [MHz]Average 2,106Min 2,097Max 2,126St. Dev 6 3 sigma distribution 0.85%Min-Max range 0.68%

X [mm]

Figure 6: Frequency uniformityof the resonators over an 8-inch wafer area

Figure 5 presents typical measuredadmittance curves of the resonators in the2-GHz range. The effective coupling factorkeff

2 is 5.3 in this case, the quality factor isQ=434.

Due to the highly uniform thickness ofthe AlN films on the wafer, the resonatorfrequency uniformity is excellent (Figure 6).Coupling and resonator quality factorsalso reach high values of 5.66% ±0.33%and 790 ±110, respectively.

SummaryUnaxis Semiconductors has developed an optimized AlN process, taking intoconsideration the Pt metal electrode andoxide sublayers seeding effects.Therefore, the CLUSTERLINE 200 systemcan be used for the deposition ofextremely uniform, smooth piezoelectricAlN films, exhibiting a high degree ofcrystalline orientation and thus meetingthe film specification requirements of BAWdevices. The coupling factor of 5.66%±0.33% and resonator quality of 790±110 have been achieved on testresonators. The reported thicknessuniformity of AlN and frequency uniformityare both better than 0.3% 1σ on 6-inch as well as 8-inch wafers.

References1 P. Jacot, C. Lambert, P. Krebs, S. Kadlec and

S.Krassnitzer, “Bulk Acoustic Wave Devices: A Promising Technology for Future WirelessCommunications”, Chip 7, 2002

2 P. Jacot, S. Kadlec, E. Kuegler and C.Lambert,Unaxis Application Note “Aluminum NitridePiezoelectric Thin Films for Bulk AcousticWave Applications” Unaxis, September 2002

3 The “MARTINA” project IST-2001-37362,http://www.isen.fr/martina/


22 | Chip Unaxis


Introducing the VERSALINE™Versatility combined with low cost of ownership

The VERSALINE™ was conceived toaddress a frequently encounteredproduction scenario needed in today’scompound semiconductor and micro-system fabrication facilities – a singleproduction oriented module. With a single-step process module, customers are notburdened with the complexity and cost ofcluster systems. A platform with a singlemodule which performs a “discreet”process step, such as the VERSALINE™,is a preferred solution when sequential ormultiple process steps are nonessential.Unaxis uses this opportunity to present theadvantages of providing etching andPECVD deposition processes on this newcost effective platform.

Unified Platform Unifying platforms – for automobiles,audio systems, as well as chip manufac-turing systems – reduces the number ofparts, simplifies development, and most

importantly, helps to lower costs overall.For this reason, two years ago UnaxisSemiconductors began reviewing itsspectrum of systems designed for diversemarkets and the corresponding widerange of deposition and etch processtechnologies, as well as wafer sizerequirements varying from 2“ to 300-mmin diameter.

The Unified Platform project plays a key role in substantially improvingperformance in the following three areas:

Cost of ownership Time to market Benchmark setting processes

For Unaxis, the Unified Platform is key toaccelerating the development and launchof new solutions and thus speeding upinnovation. It allows us to react faster toincreased demand, shortens lead timesand facilitates adaptation to the cyclicalswings of the market.

Customers benefit from this approach,making it much faster and easier to con-figure and ramp-up systems. Only a single,standardized training program is neededfor operators, rather than training on manydifferent platforms. Delivery times will bereduced considerably and finally, thebenefits for service and maintenance areobvious.

The Unaxis Unified Platform project nowprovides a clear path to upgrade with thefollowing three systems, built around astandardized software and hardware set:

Michael D. Archuletta, Vice President, Etch Business Unit,Unaxis Semiconductors

The VERSALINE™ is the newest deposition and etching system for volumeproduction from Unaxis Semiconductors. The tool is optimized to offer the lowest costof ownership for single process module applications, including cassette-to-cassetteloading. New benchmark setting processes are designed for etching and depositionon compound and silicon materials including MEMS and thin film head applications.


Figure 1: Unified Platformbasic systems

CLUSTERLINE® - high volume cluster toolVERSALINETM - volume production forsingle Process Module applications

SHUTTLELINETM - Multi-processplatform for R&D and pilot production

Unaxis Chip | 23


The SHUTTLELINE™Low volume and R&D multi-processplatform

The VERSALINE™High volume cassette-to-cassette singleprocess module system

The CLUSTERLINE®

High volume cluster system(CLUSTERLINE® 200 for wafer sizes150 to 200 mm and the CLUSTERLINE®

300 for wafer sizes 200 to 300 mm)

Within the Unified Platform projectcompatible and standardized components,modules, handling platforms, software andgraphical user interface (GUI) are utilized. The control system used in theVERSALINE™ is a flexible service-basedprogram using Control Works™-based

software, with common core softwaremodules. As a standardized systeminterface it controls the recipe manage-ment, scheduling, data collection/logging,etc., enabling functions such as e-diagnostics, data analysis and real-timefault detection.

The VERSALINE™ system has a simpleand reliable wafer-handling and userinterface, yielding improved reliability andcost effectiveness not possible with largercluster-type configurations.

Process Module Options andApplicationsThe process modules, covering a widerange of unique deposition and etchprocesses, are designed and builtaccording to a standardized architecture

to assure compatibility with the centralhandling unit where applicable, andsimplifying system configuration. Theprocess modules are engineered based onthe experience of hundreds of systemsoperating in fabs worldwide.

Figure 2: Graphical UserInterface

Figure 3: VERSALINE™communicationschematic withfactory interface

Etching ProcessesUnaxis boasts of a large library of starting-point etching processes for avariety of materials including:

Dielectrics – SiO2, Si3N4, Al2O3, Photo Resist, Polyimide,

Metals – Al, Cr, Mo, Ti, W, Ta, Semiconductors – Si, SiC, TaSi, Compound Semiconductors – GaAs,

InP, AlGaAs, InGaP, InSb, GaN

The following are examples ofguaranteed, state-of-the-art processspecifications for applications which havebecome standard in our served markets:

24 | Chip Unaxis

Etching Process Modules Inductively Coupled Plasma (ICP)

Etching– Standard Temperature (0°C – 80°C)

applications include GaAs via etch and MESA formation (Figure 4)

– High Temperature (100°C – 180°C)applications include InP featureetching and any others where effluentcontrol is important for low CoO(Figure 5)

– DSE™ III (Deep Silicon Etching) forMEMS production and wafer-scalepackaging applications

Pulsed High Frequency (PHF) RIEFor etching very thin, damage-sensitivelayers

High Performance Oxide Etching(HiPOE)For deep oxide etch applications inAWGs, MEMS and Damascenestructures

Deposition Process Module Large Area Plasma Enhanced Chemical

Vapor Deposition (PECVD)– The large area PECVD process

module is used for device encapsula-tion and many ILD (inter-layerdielectric) applications (Figure 6)

– Available processes for PECVDdielectric thin films include: SiO2,Si3N4, SiOxNy.

Process TechnologiesImproved benchmark setting processesfor applications on compound and siliconmaterials including MEMS and thin filmhead applications have been developedfor the VERSALINE™. The etching anddeposition processes are designed tosupport a broad variety of volumemanufacturing applications.


GaAs Etch Rate 8.3 µm/min – 40 µm via10.1 µm/min – 100 µm via

GaAs:PR Selectivity 15:1

Via Profile Sloped *

GaAs Rate Uniformity < 5%

Morphology Pillar Free

* using sloped PR mask

Figure 7: Optical crosssection of 40 µmdiameter via

GaAs Via III – 3rd generation GaAs viaetching for HBT (heterobipolar transistor)manufacturing (Figure 7)

Figure 6:Large area PECVD process module

Figure 4: Standard Temperature ICP PM

Figure 5: High Temperature ICP PM

Unaxis Chip | 25


Table 2:DSE performancespecifications (Table 2) & examplesof typical micro-structures created in Si using DSEprocesses (Figure 8)

Mask Etch Mask Selectivity Profile Etch Rate Sidewall Undercut Rate Resist SiO2 Uniformity Scalloping

Rate Optimized 0.3 µm 20+ µm/min > 150:1 > 250:1 90° ± 2° 3.5% length = 0.5 µm100 µm feature AR 2:1 depth = 0.1 µm

Rate Optimized 0.3 µm 7.0 µm/min > 100:1 > 200:1 90° ± 2° 3.5% length = 0.5 µm5 µm feature AR 20:1 depth = 0.1 µm

Sidewall Optimized 0.1 µm 6.0 µm/min > 75:1 > 150:1 90° ± 1° 3.0% length = 03 µm 100 µm feature AR 2:1 depth = 0.05 µm

Sidewall Optimized 0.1 µm 5.0 µm/min > 60:1 > 150:1 90° ± 1° 2.0% length = 0.3 µm5 µm feature AR 20:1 depth = 0.05 µm

The VERSALINE™ is introduced toprovide fabrication facilities with a platformwhich accommodates the most advancedtechnologies for etching and deposition.The platform consists of a reliable cassette-to-cassette handling system with easy tolearn, field-proven control software whilethe modules utilize application specificfeatures. Purposefully designing modulesfor processes and using easy maintenancehardware leads to undeniably reducedoperational costs with increased uptime.These same concepts are applied to allUnaxis systems, resulting in a completeportfolio of leading-edge productionsolutions.

For more information please [email protected].

DSE™ III – Third generation deep silicon etching for volume manufacturing of MEMS devices (Figure 8)

Figure 8a:High load etching

Figure 8b:Comb structure

Figure 8c: High aspect-ratioetching with excellentprofile control

Deposition ProcessesUnaxis offers guaranteed PECVD solutionsfor dielectric films including SiO2, Si3N4

and SiOxNy. Features of Unaxis PECVDprocesses include controllable film stress,controllable refractive index and lowhydrogen content.

SiO2 Si3N4 SiOxNy

Film stress 0 – –300 MPa –300 MPa to +300 MPa –300 MPa to +300 MPa

H2 content NA < 12% @ 300°C NA

Nf 1.46 to 1.48 1.95 to 2.05 1.6 to 1.9

Film uniformity ± 2% ± 2% ± 2%

Deposition rate 400 to 2500 Å/min. 80 to 500 Å/min. 100 to 500 Å/min.

Eb up to 5 MV/cm up to 5 MV/cm up to 5 MV/cm

BOE (ref. TOX) 10:1 to 3:1 1:1 to 0.1:1 composition dependent

Deposition temp. 100°C to 350°C 100°C to 350°C 100°C to 350°C

Table 3:Controllable ranges of film characteristics using theVERSALINE Large-Area PECVD system.

Specifications shown are selection guidelines. Actual filmperformance will be optimized for user-specific applications.

26 | Chip Unaxis


National and International BodiesDARPA (USA), 5th and 6th European FP, MST 2000+ (D)

RF MEMS manufacturersAcademic R&D

Michigan Uni (USA)HRL (USA)

Pennsylv. Uni (USA)IMEC (B)

CEA-LETI (F)FhG ISIT (D)

Tokyo Uni. (J)KAIST (Kr)

GPSC (SGP)

RF-MEMS Start-upsDiscera (USA)Xcom (USA)

Magfusion (USA)MEMS Solution (Kr)

Radant MEMS (USA)Teravicta (USA)

MEMS Start-upsMemscap (F)

PHS MEMS (F)

Large IC and MEMSmanufacturersMotorola (USA)

Intel (USA)Agilent (USA)

JDS-Uniphase (USA)STMicroelectronics (F)

Infineon (D)Philips (NI)

Samsung (Kr)NEC (J)

RF devices manuf.Epcos (D)Murata (J)

Integrators& users

Wireless telecomterminals andinfrastructure

Automotive

Space & Defence

ServicesMEMS CAD & IPCoventor (USA)

CorningIntellisense (USA)Memscap (F)

MEMS FoundriesDALSA (CA)Tronic's (F)

MEMS PackagingShellcase (IL)

RF CAD & EDAModelithicss (USA)

Sonnet. (USA)Agilent (USA)

Integrators with ownMEMS developmentDefense & aerospace

Raytheon (USA)Thales (F)

DaimlerChrysler (D)Automotive

Robert Bosch (D)

26 | Chip Unaxis

What are RF MEMS?RF MEMS are micro systems for radiofrequency and millimeter waveapplications. Examples of devices aremicro-switches, tunable capacitors,micro-machined inductors, micro-machined antennas, micro-transmissionlines and resonators including micro-mechanical resonators, BAW (BulkAcoustic Wave) resonators and cavityresonators. RF MEMS are manufactured

using conventional 3D structuringtechnologies, such as bulk micromachining, surface micro machining, fusionbonding or LIGA (X-ray Lithography). Thematerials used include Si, GaAs, SiC or SOI substrates.

In addition to their potential forintegration and miniaturization, RF MEMSoffer lower power consumption, lowerlosses, higher linearity and higher Q factorsthan conventional communicationscomponents. RF MEMS also enable newarchitectures for the next generations oftelecommunication systems, easily andrapidly reconfigurable and operating over a wide frequency range.

The serial products commerciallyavailable now include inductors atMemscap (F), Bulk Acoustic Waveresonators already manufactured in millionsof units at Agilent (USA) and Infineon (D).Furthermore, the first MEMS switches –amongst the most challenging RF MEMSproducts to manufacture – are available inevaluation kits at Teravicta (US) andMagfusion (USA).

RF MEMS market participantsThe RF MEMS industrial chain is shown inFigure 1. More than 120 industrial andresearch organizations work on RF MEMS

RF MEMS Analysis, Forecasts and Technology Review

Jérémie Bouchaud, Dr. Henning Wicht, WTC – Wicht TechnologieConsulting

Microsystems for Radio Frequency applications, known as RF MEMS, are expected to be the next breakthrough in micro-machined devicesafter accelerometers. Recognizing the significance of this exciting andimportant market, WTC carried out an in-depth investigation ofapplications, technical challenges and opportunities for RF MEMS.

Figure 1: RF MEMSindustrial chain mainbodies, companiesand services


Unaxis Chip | 27


Unaxis Chip | 27

foundry services, packaging and RFCAD and EDA (Electronic DesignAutomation)

Integrators and users who cooperatewith academic research organizations,RF MEMS manufacturers and serviceproviders developing device specifi-cations and integrating RF MEMS intheir future products

National and international authoritieswho are involved in promoting andfinancing research and developmentprograms on RF MEMS

An immense market potentialThe market potential is tremendous.Significant applications are identified as: Micro-switches to build impedance

networks in front of power amplifiers anddecrease the number of components inmulti-standard mobile phones

BAW resonators to replace bulkyceramic duplexers in 3G mobile phones

MEMS inductors and tunable capacitorsfor integrated VCOs in GPS

Switches, tunable capacitors andtunable inductors to build multi-standardand base stations which can bereconfigured

Dense networks of micro-antennas formilitary radars

We estimate the total market for RF MEMSto exceed US$ 1 billion in 2007, asfeatured in Figure 2. From 2002 to 2004,the market for RF MEMS will begin togrow, with activities focusing on prototypesand qualification processes. Full scaleproduction is anticipated to start in 2005.

In order to identify the most interestingmarket segments, we compared allpotential applications with user benefits,

Figure 2: RF MEMSmarket forecast 1200.00

1000.00

800.00

600.00

400.00

200.00

0.00

2002 2003 2004 2005 2006 2007

Turn

over

(US

$ m

illio

n)

worldwide. The RF MEMS market participants can be divided in five groups: Academic research institutions: more

than 60 universities and institutesworldwide are involved in RF MEMSresearch.

RF MEMS manufacturers including:– RF MEMS start-ups that focus on

developing RF MEMS– MEMS start-up companies that

specialize in MEMS development andRF MEMS

– Large IC and MEMS manufacturers and integrators who develop RFMEMS for their own specific needs

– Manufacturers of RF devices who arenot traditionally involved in MEMSdevelopment

Companies that offer a diverse range ofservices to the RF MEMS industrialchain including MEMS CAD and IP,

28 | Chip Unaxis


expressed by technical advantages andprice acceptance as shown in Figure 3. As a result, we distinguished three typesof market segments: High End Applications: military, space

and instrumentation applications areready to use RF MEMS. The maindrivers are the significantly bettertechnical performances and reliabilitycompared to existing techniques.Market volumes are small in comparisonwith mobile telephony, however,companies are prepared to pay higherprices for components if technicalperformances are proven.

Volume Drivers: The second groupincludes industrial and consumerapplications, interested in performanceand functionality. Mobile telephony, GPSand WLAN plan to use RF MEMS.However, price targets have to bereached, as MEMS are in competitionwith existing techniques. Theseapplications provide the large volumemarkets needed for efficient MEMSproduction.

Out of reach: In some cases MEMScould be used from a technical point of view. However, the use of MEMS is out of reach, as prices are very lowand there is no need for increasedperformance. This is the case forpersonal area networks, such asBluetooth, where RF MEMS do not offer any particular advantages.

Challenges and key factors for successRF MEMS devices offer a number ofadvantages over conventionalcomponents, however, certain issuesmust be resolved prior to their acceptanceas viable alternatives to the traditionalcomponents currently in use. Challengeswhich need to be resolved include thefollowing: Proven reliability: this is a major issue.

Some MEMS switches stand 20 billioncycles, however, very little is known on ageing of materials in the micronrange. Thus, it is difficult to carry outaccelerated aging test. Unresolved

technical problems include stiction ofmovable parts in tunable capacitors andswitches.

Packaging: a key issue, as it impactslong time reliability, performance and price of RF MEMS. For massproduction, wafer level packagingemerges as the most promising solution, as compared to discretepackaging indicating the price of RF MEMS can be halved. Increasedactivity in organizations such as APiAand its members, including UnaxisSemiconductors, will help to drivecompletion.

Pricing: producing RF MEMS at anacceptable price is the most significantchallenge for manufacturers. First, themarket prices have to be known. Whileswitches for mobile phones may bepriced between 30 and 40 cents, and between US$ 15 to 30 for instrumentation. Second, futuremanufacturing costs have to becalculated. It may happen that targetprices cannot be met. WTC hasinvestigated the price acceptance byapplication and future retail prices.

Business opportunities in RF MEMSThe market potential of RF MEMS isextensive. Subsequently to micro-machined accelerometers for airbags, it is the first time components which offerimproved performance, miniaturization and integration are required in hundreds of millions of units. We anticipate, by 2007, communications applications,including mobile telephony, GPS andWLAN will hold the major part of themarket. These markets will mainly be served by large IC and MEMSmanufacturers.

Base station

Anti collision radars

GPS

WLAN

Mobile phonesVolume drivers

RFID

Technical advantages through RF MEMS Decisiveadvantages

No advantages

Bluetooth

Out of reach

Low

Pric

e ac

cep

tanc

eH

igh Satellites

Military radarsMissile systems

Test equipment

High end applications

Figure 3: Implementationpotential for RF MEMS byapplication

Unaxis Chip | 29


However, medium-volume, higher-priced applications, such as automotiveradars, base stations and instrumentationare very promising for smaller sizecompanies and start-ups. Again,development and procurement programsfor space and military applications provideinteresting niches for small and mediumsize companies.

Two approaches are being

developed for the integration of

RF MEMS components with

ICs into RF functional modules:

hybrid integration and monolithic

integration. Which one

will dominate the market?

Indeed, the market for RF MEMS is notonly one of the most significant emergingMEMS markets in terms of size, it is alsoopen to all MEMS players from the smallstart-up to the international ICmanufacturer.


Jérémie Bouchaud is a senior analyst atWTC for microsystemsproducts and markets.He graduated from the Technical Universityof Applied Sciences inMunich and received adiploma as MarketingEngineer at theBusiness School ofGrenoble. He hasanalyzed markets forhigh technologyproducts since 1997 atthe German Office ofCEA-Leti and joinedWTC as foundingmember in 2000.

Dr. Henning Wicht is founder and presidentof WTC-WichtTechnology Consulting. Henning has beenworking in marketing of microsystemtechnology since 1993.He started working atLeti Grenoble and in1996 he set up the CEA German Office. In 2000, WTC-WichtTechnologie Consultingwas created,specializing in servicesfor companies with high tech products in microsystems andelectronics. He is co-author of the NEXUSMarket report and coordinator of theNEXUS User-SupplierClub MEMS packaging.Within SEMI he ismember of the SEMIInternational MEMSIndustry Forum andguides the technicalprogram. HenningWicht received aDiploma in IndustrialEngineering at THDarmstadt in 1993. Thesubject of his PhD workwas the evolution of themicrosystems industry.It was published as abook in 1999.

Hybrid integration is rather straightforward. It uses wirebonding or flip-chip and is well suited to small to mediumvolumes. Hybrid integration makes it possible to optimizethe design and manufacturing of the MEMS independentlyof the IC. This is important because even if MEMS and ICsare similar with regards to batch fabrication or use of silicon,the processes are very different. For example: IC manufacturers are not familiar with sacrificial layers and thechemicals used to remove them in MEMS processes; while12" wafers are coming for ICs, most MEMS are stillmanufactured on 4" or 6" wafers; some poly-silicon RFMEMS switches are manufactured at 1100°C whereasCMOS processes usually do not exceed 350°C.

Monolithic integration reduces the number of interconnects. This results in smaller losses, increasedreliability, and – last but not least – lower chip prices. Asmonolithic integration is much more complex than hybridintegration, it only makes sense for mass-producedproducts, where price pressure and high volumes justify the development of more complex processes. Above-ICintegration of inductors and BAW resonators is a first steptowards monolithic integration. However, the objective andthe real challenge is the “In-IC” manufacturing, i.e., themanufacturing of MEMS in 100% CMOS-compatible lines.While BAW resonators are already manufactured in 90%CMOS-compatible lines, RF MEMS with a higher number of mask-like switches or tunable capacitors still needdedicated lines. The full manufacturing compatibility ofMEMS and ICs is a tough challenge for MEMS manufac-turers as well as for equipment and materials suppliers, but it is key to meeting the extremely low price requirementsfrom the RF MEMS killer application – mobile phones. MajorRF MEMS players such as STMicroelectronics, the IMECand several Taiwanese foundries are actively working atfinding a solution.

Hybrid versus monolithic integration

30 | Chip Unaxis


30 | Chip Unaxis

IntroductionA VCSEL is a specialized laser diode thatpromises to revolutionize fiber opticcommunications by improving deviceefficiency and increasing data speed.Representing some of the latesttechnology in laser design, VCSELs havegained much attention in the photonicdevices field due to their high powerconversion efficiency at low operatingcurrents [1]. While similar in operatingprinciple to conventional diode lasers,where the light emerges from the edges ofthe device through mechanically cleavedsurfaces, VCSELs are unique in that the

reflecting mirror surfaces (called DBR –Distributed Bragg Reflectors) are stackedvertically, with the light emerging normal to the substrate surface. The light emissionis in the shape of a circular beam, muchmore efficient for coupling to fiber opticsthan the elliptically shaped beam of the edge emitting lasers. A simplifiedschematic of a VCSEL is illustrated inFigure 1. Typically, the mirror stacksconsist of alternating layers of doped III-Vcompound semiconductor materials suchas GaAs and AlxGa1–xAs. VCSEL devicefabrication requires a process which non-selectively etches through these epitaxiallayers with smooth feature walls stoppingon the specific layer in the active region.Controllable etch rates near 1 µm/min andvertical feature profiles are necessary tomeet these requirements.

GaAs/AlxGa1–xAs non-selective etchingusing RIE, ICP and ECR reactors has beenstudied in the past; SiCl4, BCl3, SiCl4/Cl2and BCl3/Cl2/Ar plasmas have historicallybeen the choices for achieving equal-rateor near equal-rate etch for GaAs/AlxGa1–xAslayers [2]. However, very few papers havereported the utilization of high densityplasma for VCSEL applications. Inaddition, implementation of an etchprocess monitoring technique isbecoming increasingly important in themanufacturing environment [3]. In thefollowing pages, we describe an ICP-based non-selective GaAs/AlxGa1–xAs etchprocess for the fabrication of VCSELmicro-laser devices. The process space ischaracterized using designed experiments(DOE). Endpoint detection techniquesincluding laser reflectance and Optical

Emission Spectroscopy (OES) were alsoevaluated in this work.

ExperimentalAll experimental work was performed withUnaxis Semiconductors’ inductivelycoupled high-density plasma technologyon a platform equipped with electrostaticclamping and He backside cooling. On thissystem, a high-density plasma isgenerated by a 2 MHz coil while the ionenergy is controlled by a 13.56 MHz RFbiased cathode. Gas flow rates arecontrolled by mass flow controllers. Thesubstrate was set at room temperatureand controlled by backside He cooling.The Unaxis ICP system was also equippedwith two endpoint systems including laserreflectance and Unaxis Spectraworksoptical emission spectrometer. The (SOFIEInstruments S.A. Inc.) laser reflectancesystem consists of a polarized 670.4 nmHe-Ne laser head, CCD detector andvideo camera for laser spot positioning.The Unaxis Spectraworks OES system hasa spectral range of 200 –800 nm with aresolution of 1 nm. The plasma emission is coupled to the spectrometer through a sapphire reactor viewport and a silicaoptical fiber.

Results and discussionPrior to the DOE, a number of preliminaryexperiments were conducted toindependently examine the GaAs andAlGaAs etch rates. Figure 2 shows similar etch rates for GaAs and AlGaAsover a 0 – 50% Cl2 in a BCl3/Cl2 mixture.Later experiments confirmed the etchrates of the alternating layers in the

VCSELs to Revolutionize Fibre Optic CommunicationsCharacterization of GaAs/AlGaAs non-selective ICP etch process for VCSEL (Vertical Cavity Surface Emitting Laser) applications

M. W. DeVre, Y. S. Lee, B. H. Reelfs, R. J. Westerman, Unaxis Semiconductors

Figure 1:Simplified VCSELcross section

Surface-emitted beam ina circular narrow cone

Isolation

P-type multilayer DBR(Distributed Bragg Reflector)

Active region

N-type multilayer DBR


Unaxis Chip | 31


Unaxis Chip | 31

VCSEL devices were in good agreementwith the etch rates of the individual films.Based on these results a series ofdesigned experiments were performed on VCSEL device structures.

DOE resultsThe analyzed DOE response for thecomposite GaAs/AlGaAs stack etch rateis illustrated in Figure 3. Consistent with a chemically driven etch mechanism, the GaAs/AlGaAs composite etch rateincreases with increased chamberpressure and Cl2 percentage. Thissuggests that the generation of Cl radicalsis the key factor determining the etch rate of GaAs/AlGaAs. Furthermore, sincethe GaAs/AlGaAs etch rate is independentof both the RF bias and ICP powers overthe range of parameters tested, thissuggests the process is reactant-limited.

Based on the DOE analysis, the mask(silicon nitride) etch rates were mainlycontrolled by Cl2% and weakly affected by RF bias power. High Cl2% and RF biaspowers tended to increase SiNx etchrates. The GaAs/AlGaAs:SiNx etchselectivity was found to be a function ofboth Cl2% and pressure with high Cl2percentages significantly improving the etch selectivity due to a stronglyenhanced GaAs/AlGaAs etch rate. TheDOE analysis also showed that Cl2% is the only parameter having a significanteffect on the profile. High Cl2% tends toresult in re-entrant (undercut) featureprofiles, while high BCl3% lead topositively tapered (sloped) profiles. The DOE results did not show a significant parameter dependence on the non-uniformity over the range ofparameters tested. All cells within the

designed experiment showed etch rate uniformities well below ± 3% (Range /(2 Mean method)).

Mask effectThe initial mask properties such as profileand edge roughness had a profoundeffect on the etched feature profiles andsidewall morphology. The magnitude ofthe effect depends primarily on the etchselectivity, which in turn is a function of theprocess conditions. A positively slopedetched profile can be achieved throughthe use of a sloped mask profile andlowering selectivity of the stack material to the mask (driving the mask profile intothe etched feature through mask erosion).For applications requiring vertical featureprofiles, it is preferable to utilize a hardmask such as silicon nitride or silicondioxide. Selectivities to these materials

Figure 2: The etch rates of GaAs and AIGaAs as the function of the %CI2 in BCI3/CI2

GaAs

AIGaAs

2.5

2.0

1.5

1.0

0.5

0.0

Etc

h ra

te[µ

m/m

in]

% CI2

0 10 20 30 40 50 60

Etch Rate[µm/min]

1.0

0.5

0.0

-0.5

-1.0-1.0 -0.5 0.0 0.5 1.0

Pressure[relative]

0.50

0.90

1.30

1.70

2.10

% C

I 2[r

elat

ive]

Figure 3: Contour plot of theGaAs/AIGaAs etch rate responsesurface as a function of pressureand CI2%

32 | Chip Unaxis


32 | Chip Unaxis

can be up to 4 times higher compared to photoresist mask materials. Figure 4demonstrates the etched results ofapplying the optimized process on anitride masked AlGaAs based VCSELstack structure. As is apparent from Figure 4, a highly anisotropic profile wasobtained through the use of nearly verticalmask combined with highly selectiveprocess conditions.

Endpoint detectionIn this work, two primary types of endpointsystems were employed to examine thefeasibility of monitoring the process: laserreflectance and optical emissionspectroscopy (OES). Figure 5 shows an

example of a laser reflectance trace of aVCSEL etch process. The etch depth ismonitored by counting the reflectancepeaks. Each peak represents etchingthrough a GaAs/AlGaAs mirror pair. TheOES was used to monitor the progress ofthe etch in the stack by looking at the Gaemission line from the plasma. An OESsignature for the VCSEL etch process isshown in Figure 6. The emission signalalternates between maxima and minima,with the maximum corresponding toetching a GaAs layer and the minimumcorresponding to etching the AlGaAslayer. The peaks in the OES signaturematch the peaks observed using the laserCCD system. Once the base region isreached, no more variation in the signal isseen, and end-point is easily detected.

ConclusionsA systematic investigation of a dry etchprocess for GaAs/AlxGa1–xAs using aBCl3/Cl2 chemistry in a high densityplasma has been performed.GaAs/AlGaAs etch rates ranged fromapproximately 0.25 to 2.5 µm/min. The DOE results show the compositeGaAs/AlGaAs etch rate is a strongfunction of Cl2/BCl3 ratio and pressure.The etch rates of GaAs and AlGaAsobtained with Cl2% varying from 20% to

50% were nearly identical. The mask (SiNx)etch rate was mainly controlled by Cl2%and weakly affected by RF bias power.Cl2/BCl3 percentage and pressure werefactors which influenced the stack:masketch selectivity. Etch rate uniformity wellunder ± 3% (Range / (2 Mean)) wasobtained over all etch conditions. HighCl2% tended to result in re-entrant etchedprofiles; while high BCl3% lead to positivelytapered profiles. We are able to etch thestack GaAs/AlGaAs with equal etch rateand excellent uniformity. Laser reflectancehas been demonstrated as a powerful tool to determine the etch depth duringprocessing, while the success of utilizingOES as an endpoint technique was foundto be a function of exposed area and willstrongly depend on the individualapplication.

References1 Choquette K. D. and Hou H. Q. 1997 Proc. IEEE

85 1056-1058. 2 Agarwala S., King O., Horst S., Wilson R.,

Stone D. and Dagenais M. 1999, J. Vac. Sci.Technol. A 17(1) 52-55.

3 Johnson D., Westerman R., DeVre M., Lee Y.and Sasserath J. 2000/2001, CompoundSemiconductor 6(9) 62-64.


Figure 4: SEM photograph ofVCSELs structureafter etching with the optimizedprocess; a verticalprofile is observed.

Figure 5: Laser reflectivity as a function of etch time

Figure 6: OES intensity as afunction of etch time

Unaxis Insights

Unaxis SemiconductorsAround the Globe

September 2003

Served Market Segments

AdvancedSilicon

Semiconductors

Customer Support &Training

AdvancedPackaging

Compound Semi &Microtechnology

Process Technologies

- Silicon Processes (CMOS and BICMOS Multilevel Metallization, Ultra-Thin Wafer Backside Metallization)

- SiGe Applications

- Photomask

- Flip Chip UBM (Underbump Metallization)

- Wafer Level CSP (Chip Scale Package)

- Re-Routing

- Integrated Passives

- GaAs, InP, InGaAs

- Photonic Devices (Planar Optics)

- MEMS, MOEMS & Nanotechnology

- SAW, BAW

- GMR (Magnetic Sensors)

Deposition

PVD

PECVD

UHV-CVD

LEPECVD

Etching

RIE

HDP

ICP

SupportingProcesses

RTP

LEPC


Awards do matter! Rather than justgathering dust on the wall they identify acompany’s position among peers,encourage positive competition, provide a benchmark for prospective customersand are a major motivation for everyone on the team. We are especially proud toreceive the VSLI “10 BEST” award,because it is awarded by our customers. It honors all our employees, their hardwork and commitment to excellence.

This year, Unaxis Semiconductorsreceived particularly high scores in theareas of Quality of results Field engineering support Product performance Commitment to meeting

customers’ needs

The survey was carried out byVLSI, who was among decisionmakers in the semiconductorindustry ranking Unaxis in 6th

place in the category of Small

Good, Better,“10 BEST”

“We are honored and proud to see the effectsof our global account management alreadystarting to pay off. This award is an incentivefor us to proceed on this path.”

Ralf Kuhlmann, International Sales and Marketing Manager

Rank Company Overall rating1 Tegal Corporation 8.312 SUSS Micro Tec 7.543 Matrix Integrated Systems 7.464 AIXTRON AG 7.295 SEZ Group 7.146 Unaxis Semiconductors 7.137 Ultratech Stepper, Inc. 7.028 EV Group 6.929 Hitachi Kokusai Electric Inc. 6.84

10 Mattson Technology, Inc. 6.54

Wafer processing equipment (Small suppliers based on revenue)

Lynn Ochs, Sales and Market Manager North America, (left) and Ralf Kuhlmann,International Sales and Marketing Manager, are proud of the achievement and look forwardto an even better position next year.

What is the VLSI 10 BEST Award?The VLSI 10 BEST Award is presentedannually by VLSI Research Inc to chip makingequipment suppliers. It is the industry’sprincipal indicator of how well equipmentmanufacturers perform in meeting theircustomers’ needs. The VLSI ResearchCustomer Satisfaction Survey is not just aboutcustomer service, but about the level oftechnical support and product qualityprovided. Seven different categories aretested: Small Suppliers of Wafer ProcessingEquipment; Large Suppliers of WaferProcessing Equipment; Assembly Equipment;Process Diagnostics Equipment; Test andMaterial Handling Equipment; Large Suppliersof Chip Making Equipment; and FocusedSuppliers of Chip Making Equipment. In 2003,VLSI Research received over 2,100 completedsurveys returned from semiconductorequipment users around the world todetermine the rankings. Survey respondentsare asked to rate suppliers in thirteencategories on a 10-point scale. These thirteencategories include seven measures ofequipment performance and six measures ofcustomer service. The performance measuresare cost of ownership, uptime, software, buildquality, usable throughput, quality of resultsand product performance. The six customerservice categories are process support, fieldengineering support, spares support, supportafter sales, technical leadership, and vendor’soverall commitment.

For the fourth consecutive year, Unaxis Semiconductors hasbeen awarded a place among the “10 BEST” semiconductorequipment suppliers.

Suppliers of Wafer Processing Equipment– moving up two places since last year.

When we last reported on the 10 BESTAward in Chip 7, we wrote about ourplans for ISO certification at theSt.Petersburg site. This major goal hasnow been achieved (see article page 2),as well as a new Customer ComplaintManagement System (see page 3). Weare looking forward to next year’schallenge, and hope to improve on ourcurrent position.

Marion Turner, U.S. Marketing Communications Manager Unaxis Semiconductors

NorthAmericaLynn Ochs Sales and Market ManagerNorth [email protected]

David HartelCustomer Support [email protected]

Eastern NorthAmericaDan PaceSales [email protected]

Peter PotterSales [email protected]

WorldwideKenneth T. BarryPresident,Unaxis [email protected]

Ralf KuhlmannInternational Sales andMarketing [email protected]

Jürg SteinmannGlobal Communications [email protected]

Robert Van der PuttenGlobal Customer [email protected]

Wolfgang RadloffSales and Market Manager [email protected]

EuropeMark HashemiSales and Market [email protected]

Ralf EichertSales and Service ManagerCentral Europe**[email protected]

Fiorenzo SlavieroSales and Service Manager South Europe***[email protected]

Sylvester SeboldCustomer Support [email protected]

Jean Pierre VercellettoCustomer Support South [email protected]

Dr. Gotthard KudlekSales Engineer Central [email protected]

Klaus PetersenSales Engineer Central [email protected]

Jean-Claude Le VelySales Manager [email protected]

Marcel KesslerSystem Sales Support Greater China and [email protected]

Claude DupuySales Engineer South [email protected]

Tom BeensSales and Service Manager North Europe*[email protected]

ChinaWilliam ZhuSales and Service [email protected]

David WuSales [email protected]

Wingo LuCustomer Support [email protected]

Sunday HuangSales [email protected]

Greater ChinaBenjamin LohPresident Unaxis Greater [email protected]

Dr. Gordon ShyuSales and Market ManagerGreater [email protected]

SingaporeChih Heng HanPresident Unaxis [email protected]

Swee Teck OngCustomer Support [email protected]

Boon Kwong TanSales [email protected]

Elaine NgSales [email protected]

KoreaIn-Chul CheonPresident Unaxis Korea [email protected]

Jason ParkSales [email protected]

Ha-Yong KwakSales & Service [email protected]

Kibom KimCustomer Support [email protected]

Daniel KimProject [email protected]

Pearl KimSales [email protected]

JapanDr. Susumu SawadaPresident Unaxis Japan Co. [email protected]

Hirohide FujiiSales & Service [email protected]

Yukihide KajimotoCustomer Support [email protected]

Masatoshi NakamuraCustomer Support [email protected]

Toshihide HarukiSales Manager [email protected]

Wataru MomoseSales Engineer [email protected]

Taeko MatsuiSales [email protected]

Taiwan

Daven HsuCustomer Support [email protected]

Julien WuSales and Service [email protected]

Jimmy ChenSales [email protected]

Aidan HuangSales [email protected]

Bruce LeeSales [email protected]

Joanne TengSales [email protected]

Western NorthAmericaMichael HelmesSales and Service [email protected]

Hermann ObermoserCustomer Support [email protected]

Peter IgnacioSales Engineer [email protected]

Todd SmithSales Engineer [email protected]

Jim GreenwellSales [email protected]

Digital Imagery © copyright 2001 PhotoDisc, Inc.

Our experienced team of R&D, sales and systems support specialists are therefor you, wherever and whenever you may need them – anywhere in the world.

For updates please checkwww.semiconductors.unaxis.com

* Benelux, Ireland, UK, Scandinavia** Austria, Germany, Liechtenstein,

Switzerland*** Israel, Spain and Portugal

Asia

North AmericaUnaxis USA Inc., [email protected] Tel +1 727 577 4999Fax +1 727 577 7035

EuropeUnaxis Deutschland GmbH, [email protected] Tel +49 89 7550 5251 Fax +49 89 7550 5111

ChinaUnaxis (Shanghai) Co., [email protected] Tel +86 21 5057 4646Fax +86 21 5057 4647

SingaporeUnaxis IT Pte. [email protected] Tel +65 6890 6288 Fax +65 6890 6290

KoreaUnaxis Korea Ltd., [email protected] Tel +82 31 708 8666Fax +82 31 708 7666

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