Bus

ΗΥ-220 - Καλοκαιρινός Γιώργος 1

Bus


MCS51


MCS51 External R/W Operation


MCS51 Programme Memory Access


Parallel Port Pin Description


ECP mode Forward


ECP mode Reverse


Parallel Port IPC block


PCI Bus Pin List


Initiator Target


PCI Commands Command Type C/BE[3:0]#• Interrupt Acknowledge 0000• Special Cycle 0001• I/O Read 0010• I/O Write 0011• Memory Read 0110• Memory Write 0111• Configuration Read 1010• Configuration Write 1011• Memory Read Multiple 1100• Dual Address Cycle 1101• Memory Read Line 1110• Memory Write and Invalidate 1100


Basic Read Operation


Basic Write Operation


Basic Arbitration


Master Initiated Termination

• Completion : The master has concluded its

intended transaction.

• Timeout : Termination when the master’s

GNT#_ is deasserted and its internal

Latency Timer has expired.


Master Abort Termination


Master Initiated Termination


Target Initiated Termination

• Retry : Termination requested before any data is tranferred.

• Disconnect : Termination requested with or after data was transferred on the initial phase because the target is unable to respond within the target subsequent latency requirement, and is temporarily unable continue bursting.

• Target Abort : Adnormal termination requested because the target detected a fatal error or the target will never be

able to complete the request.


Target Initiated Termination Signaling Rules 1/2

• A data phase completes on the rising edge on which IRDY# is asserted and either STOP# or TRDY# is asserted.

• Independent of the state of STOP#,a data transfer takes place on every rising edge of clock where both IRDY# and TRDY# are asserted.

• Once the target asserts STOP#, it must keep STOP# asserted until FRAME# is deasserted, whereupon it must deassert STOP#.


Target Initiated Termination Signaling Rules 2/2

• Once a target has asserted TRDY# or STOP#, it cannot change DEVSEL#, TRDY# or STOP# until the current data phase completes.

• Whenever STOP# is asseted, the master must deassert FRAME# as soon as IRDY# can be asserted.

• If not already deasserted, TRDY#, STOP#, and DEVSEL# must be deasserted the clock following the completion of the last data phase and must be tri-stated the next clock.


Target Initiated Termination 1/2


Target Initiated Termination 2/2


Disconnect-1 Without Data Termination


Disconnect-2 Without Data Termination


Retry


PCI Configuration Header


Status Register Bit Assignmet


Command Register Bit Assignmet


Base Address Register Format

Documents

Bus