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8051 Microcontroller
B.Suresh
Asst professor
ECE Department
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
1
Features of 8051 Microcontroller
It is a 8-bit Microcontroller
It is a 40 pin chip available in DIP package
It has 8-bit 4 parallel ports
It contains internal RAM 128 Bytes and internal 4KB ROM
It has 128 user defined flags
Its maximum internal clock frequency rating is 12MHz
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
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20
40
39
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28
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21
31
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
XTAL 2
XTAL 1
GND
Vcc
P0.0(AD0)
P2.0(A8)
P2.1(A9)
P2.2(A10)
P2.3(A11)
P2.4(A12)
P2.5(A13)
P2.6(A14)
P2.7(A15)
PSEN
ALE/PROG
EA/VPP
P0.6(AD6)
P0.7(AD7)
P0.5(AD5)
P0.4(AD4)
P0.3(AD3)
P0.2(AD2)
P0.1(AD1)
(RD) P3.7
P1.7
(Serial)
interrupt
Timer
Ex M W/R
clock
Ext
Memory
Address
Ext Memory
Access Control
Ext Memory
Address
8051
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
4
Pin Description of 8051 Mc
Vcc(pin 40)
Vcc provides supply voltage to the chip. The voltage source is +5V.
GND(pin 20)-ground
XTAL1 and XTAL2(pins 19,18)
These 2 pins provide external clock. Way 1:using a quartz crystal oscillator Way 2:using a TTL oscillator
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
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Pin Description of 8051 Mc RST(pin 9):reset
It is an input pin and is active high(normally low). The high pulse must be high at least 2 machine cycles. Upon applying a high pulse to RST, the microcontroller
will reset and all values in registers will be lost
/EA(pin 31):external access There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is
stored externally. /PSEN & ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. The signal 0 is for external memory access and signal 1
for internal memory access B.Suresh, Asst.prof ,ECE
Department,ASIST,Paritala 6
Pin Description of 8051 Mc /PSEN(pin 29):program store enable
This is an output pin and is connected to the OE pin of the ROM
This is acts as low to read external program code memory
ALE/PROG(pin 30):address latch enable
It is an output pin and is active high.
8051 port 0 provides both address and data.
The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
This pin acts as program pulse input during on-chip EPROM programming
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
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Pin Description of 8051 Mc
I/O port pins
The four ports P0, P1, P2, and P3.
Each port uses 8 pins.
All I/O pins are bi-directional.
The ports has additional functionality also there except PORT 1
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
8
Pin Description of 8051 Mc
PORT P1 (Pins 1 to 8):
The port P1 is a port dedicated for general I/O purpose. The other ports P0, P2 and P3 have dual roles in addition to their basic I/O function
PORT P0 (pins 32 to 39):
When the external memory access is required then Port P0 is multiplexed for address bus and data bus that can be used to access external memory in conjunction with port P2. P0 acts as A0-A7 in address bus and D0-D7 for port data. It can be used for general purpose I/O if no external memory presents.
PORT P2 (pins 21 to 28):
Similar to P0, the port P2 can also play a role (A8-A15) in the address bus in conjunction with PORT P0 to access external memory. B.Suresh, Asst.prof ,ECE
Department,ASIST,Paritala 9
Pin Description of 8051 Mc
PORT P3 (Pins 10 to 17): In addition to acting as a normal I/O port P3.0 can be used for serial receive input pin(RXD) P3.1 can be used for serial transmit output pin(TXD) in a
serial port, P3.2 and P3.3 can be used as external interrupt pins(INT0’
and INT1’), P3.4 and P3.5 are used for external counter input pins(T0
and T1), P3.6 and P3.7 can be used as external data memory write
and read control signal pins(WR’ and RD’)read and write pins for memory access
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
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Architecture of 8051Mc
Accumulator(ACC):
The A Register acts as an operand register. the ACC has allotted an address in the on-chip special function register bank.
B-Register:
It is specially used for multiply and divide operations to store the one of the operand
Program status word(PSW):
this register contain the information about the status of the program. it reflects the status of the CPU. it is treated as special function register
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
13
Stack Pointer(SP):
It is 8-bit wide. it will reside any where in the on-chip ROM. The stack pointer initialized to 07H after reset.
Data Pointer(DPTR):
It is used to hold 16-bit address. it is used as two independent registers as DPH(8-bit),DPL(8-bit)
Port 0 to 3 Latches and Drivers:
These are for four on-chip I/O ports .They acts like pairs
Architecture of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
14
Serial Data Buffer:
The serial data buffer internally contain two independent registers a transmit Buffer(PISO) register and Receive Buffer(SIPO)register.
The Serial Data Buffer identified by the SBUF and is one of the SFRs
Control Registers:
the SFRs ,IP,IE,TMOD,TCON,SCON and PCON contain the control and status information for interrupts ,timers/counter s and serial ports
Architecture of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
15
Timing and control unit:
This unit derives all necessary timing and control signal required for the internal operation of the circuit and also derives the control signal for the external system bus also
Oscillator:
The circuit generates the basic timing clock signal for the operation. Using crystal oscillator it generates the 12MHz clock
Instruction Register:
it decodes the opcode of an instruction to be executed and gives the information to the timing and control unit to generate the necessary signal for execution of the instruction
Architecture of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
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EPROM and Program Address Register:
This block provides the on-chip EPROM and mechanism to internally address it.
RAM and RAM Address Register:
these block provides the internal 128 bytes of RAM and mechanism to address it internally.
ALU:
Arithmetic and Logic Unit
It uses the temporary Registers TMP1 and TMP2 to store the operands
It can not be accessed by the users
Architecture of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
17
SFR Register Bank:
This is a set of SFRs
Address range from 80H to FFH.
Interrupt , serial and timer units:
They control and perform their specified functions under the control timing and control unit
Architecture of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
18
Addressing Modes of 8051Mc
Direct addressing mode:
Operands specified by using the 8-bit address field in the instruction format
Only internal data RAM and SFRRs can be directly addressed
Ex: MOV Ro,90H(address of SFR P1)
Indirect Addressing Mode:
In this 8-bit operand address stored in register and is specified in the instruction
For this we can use Ro and R1 and Stack Pointer
Ex: add A@R1
B.Suresh, Asst.prof ,ECE
Department,ASIST,Paritala 19
Register Addressing Mode:
in this mode operands are stored in the registers R0-R7 of the selected register bank . the register bank is selected using the two bits of PSW.
Ex: ADD A,R5
Register Specific Addressing mode:
In this mode the operand is implicitly specified using one of the registers.
Ex: RRA
Addressing Modes of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
20
Immediate Addressing mode:
In this mode a constant is specified in the instruction
Ex: mov A,#120H
Indexed addressing mode:
Only program memory can be accessed using this addressing mode.
Ex: movc A,@A+DPTR(read program memory at A+DPTR)
movc A,@A+PC(read program memory at A+DPTR)
Addressing Modes of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
21
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of
the 8051
Register structure of 8051
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
22
Register Structure of 8051Mc
Accumulator(ACC):
It is an operand register.
it is 8-bit wide
Address range 0EOH
B-Register:
It is specially used for multiply and divide operations to store the one of the operand.
The address range 0FOH
B.Suresh, Asst.prof ,ECE
Department,ASIST,Paritala 23
Temporary Registers(TMP1 and TMP2):
They hold the operands temporarily.
They are not user accessible
These 8-bit wide each
Stack Pointer:
It is 8-bit wide. it will reside any where in the on-chip ROM. The stack pointer initialized to 07H after reset. this causes the stack to begin at location 08H
It uses the instructions PUSH and CALL
Register Structure of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
24
Program Status word(PSW):
It is 8-bit Register It is given address range 0H0C in the SFRs address range It ha CY,AC,F0,RS1 and RS0,OV,P,X 1. CY – Carry flag 2. AC-Auxiliary carry flag 3. F0-general purpose status flag from user 4. RS1 and RS0-Register bank select bits 5. OV- Overflow flag 6. P-Parity flag 7. X-one user definable flag
Register Structure of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
25
Data Pointer(DPTR):
It is used to hold 16-bit address. it is used as two independent registers as DPH(8-bit),DPL(8-bit)
These have address range 82H(DPH) and 83H(DPL) in the SFRs address range
Program counter(PC)and Program incremented:
These are 16-bit each
The PC holds the address of the next instruction to be executed
PC incremented increments the PC contents by one
Register Structure of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
26
Serial Data Buffer:
It is a a16-bit Register
The address range 99H in the SFRs
The serial data buffer internally contain two independent registers a transmit Buffer(PISO) register and Receive Buffer(SIPO)register.
The Serial Data Buffer identified by the SBUF and is one of the SFRs
Register Structure of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
27
EPROM and Program Address Register:
This is not available in all 8051 versions
This block provides the on-chip EPROM and mechanism to internally address it.
Program Address Register can address up to 4kB of memory
RAM and RAM Address Register:
these block provides the internal 128 bytes of RAM and mechanism to address it internally.
Register Structure of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
28
Instruction Register:
it decodes the opcode of an instruction to be executed and gives the information to the timing and control unit to generate the necessary signal for execution of the instruction
Control Registers:
the SFRs IP,IR,TMOD,TCON,SCON, and PCON contain the control and status information
SFRs Register Bank:
This si a set of SFRs .which can be addressed using their respective address which lie in the range of 80H to FFH
Register Structure of 8051Mc
B.Suresh, Asst.prof ,ECE Department,ASIST,Paritala
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