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BSCAN to JTAG Converterv1.0
LogiCORE IP Product GuideVivado Design Suite
PG365 (v1.0) October 30, 2019
Table of ContentsChapter 1: Introduction.............................................................................................. 3
IP Facts..........................................................................................................................................3
Chapter 2: Overview......................................................................................................4Licensing and Ordering.............................................................................................................. 5
Chapter 3: Product Specification........................................................................... 6Interface Descriptions................................................................................................................ 6
Chapter 4: Designing with the Core..................................................................... 8Clocking........................................................................................................................................ 8Resets............................................................................................................................................8
Chapter 5: Design Flow Steps...................................................................................9Customizing and Generating the Core..................................................................................... 9Constraining the Core...............................................................................................................11Synthesis and Implementation................................................................................................12
Appendix A: Debugging............................................................................................ 13Finding Help on Xilinx.com...................................................................................................... 13Debug Tools............................................................................................................................... 14
Appendix B: Additional Resources and Legal Notices............................. 15Xilinx Resources.........................................................................................................................15Documentation Navigator and Design Hubs.........................................................................15References..................................................................................................................................15Revision History......................................................................................................................... 16Please Read: Important Legal Notices................................................................................... 16
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Chapter 1
IntroductionThe BSCAN to JTAG Converter core is designed to bridge BSCAN and JTAG interfaces. This corecan be useful for applications where a debug interface supports JTAG and not the BSCANinterface provided by the Debug Bridge IP or BSCAN primitive. The BSCAN to JTAG Convertercore can be used in the Vivado® IP integrator or instantiated.
IP FactsLogiCORE™ IP Facts Table
Core Specifics
Supported Device Family1 UltraScale+™, UltraScale™, Zynq®-7000 SoC, 7 series
Supported User Interfaces JTAG Interface
Provided with Core
Design Files Encrypted RTL
Example Design Not Provided
Test Bench Not Provided
Constraints File XDC
Simulation Model Not Provided
Supported S/W Driver N/A
Tested Design Flows
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Xilinx Support web page
Notes:1. For a complete list of supported devices, see the Vivado® IP catalog.2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
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Chapter 2
OverviewThe BSCAN to JTAG Converter core is designed to bridge Xilinx® BSCAN and JTAG interfaces.The IP converts the signals received from a BSCAN interface into JTAG signals that can driveJTAG transactions. For example, the signals found in BSCAN primitive or Debug Bridge IP. The IPcan be used in the Vivado® IP integrator or can be instantiated in HDL in a Vivado project. The IPcan also be used in applications that supports JTAG input interface but does not support BSCANinterface.
The following figure shows the block level design of the BSCAN to JTAG Converter core wheninstantiated in the Vivado IP integrator.
Figure 1: BSCAN to JTAG IP Interface
The following figure shows the available ports in BSCAN and JTAG interfaces:
Chapter 2: Overview
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Figure 2: BSCAN to JTAG IP Port
Licensing and OrderingThis Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®
Design Suite under the terms of the Xilinx End User License.
Note: To verify that you need a license, check the License column of the IP Catalog. Included means that alicense is included with the Vivado® Design Suite; Purchase means that you have to purchase a license touse the core.
For more information about this core, visit the BSCAN to JTAG Converter product web page.
Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx IntellectualProperty page. For information about pricing and availability of other Xilinx® LogiCORE IPmodules and tools, contact your local Xilinx sales representative.
Chapter 2: Overview
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Chapter 3
Product SpecificationThe BSCAN to JTAG Converter core is used to drive data into the design through a JTAGinterface and also reads data from the design through the same JTAG interface. The data iswritten to the BSCAN interface of the IP, which in turn generates JTAG transactions for the JTAGport. There is no buffering mechanism within the IP. Therefore, it drives transactions fromBSCAN to JTAG interface without any delay.
Interface DescriptionsThe following table describes BSCAN to JTAG Converter core interfaces:
Table 1: Interface Descriptions
Signal I/O DescriptionS_BSCAN BSCAN slave interface This slave interface needs to connect to the BSCAN
interface of a BSCAN master.
M_JTAG JTAG master interface This master interface needs to connect to the JTAGinterface of a JTAG slave.
External BSCAN Interface SignalsThe following table describes external BSCAN interface signals:
Table 2: External BSCAN Interface Signals
Signal I/O Width Descriptionbscanid_en I 1 Enable input for BSCAN ID.
capture I 1 CAPTURE input from controller.
drck I 1 Gated TCK input.
reset I 1 Reset input from controller.
runtest I 1 Input asserted when TAP controller is in run Test/Idle state.
sel I 1 USER instruction active input.
shift I 1 SHIFT input from controller.
tck I 1 Test clock input.
tdi I 1 Test data input (TDI) input from controller.
Chapter 3: Product Specification
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Table 2: External BSCAN Interface Signals (cont'd)
Signal I/O Width Descriptiontdo O 1 Test data output (TDO) output for USER function.
tms I 1 Test mode select input.
update I 1 UPDATE input from controller.
JTAG Interface SignalsThe following table describes JTAG interface signals:
Table 3: JTAG Interface Signals
Signal I/O Width DescriptionTCK O 1 Test clock output. Output clock for sampling the data.
TDI O 1 Test data input (TDI) output. Serial data output.
TDO I 1 Test data output (TDO) input. Serial data input.
TMS O 1 Test mode select (TMS) output. Controls the transitions.
Chapter 3: Product Specification
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Chapter 4
Designing with the CoreThis section includes guidelines and additional information to facilitate designing with the core.
ClockingThe S_BSCAN_tck input port is used as a clock port in the BSCAN input interface by BSCAN toJTAG master core. For the output, all JTAG signals are sampled based on the JTAG_TCK outputclock.
ResetsThe S_BSCAN_reset input port is used as a reset port in the BSCAN interface by the BSCAN toJTAG Converter core. For the output JTAG interface there is no specific reset signal.
Chapter 4: Designing with the Core
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Chapter 5
Design Flow StepsThis section describes customizing and generating the core, constraining the core, and thesimulation, synthesis, and implementation steps that are specific to this IP core. More detailedinformation about the standard Vivado® design flows and the IP integrator can be found in thefollowing Vivado Design Suite user guides:
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
• Vivado Design Suite User Guide: Designing with IP (UG896)
• Vivado Design Suite User Guide: Getting Started (UG910)
• Vivado Design Suite User Guide: Logic Simulation (UG900)
Customizing and Generating the CoreThis section includes information about using Xilinx® tools to customize and generate the core inthe Vivado® Design Suite.
If you are customizing and generating the core in the Vivado IP integrator, see the Vivado DesignSuite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IPintegrator might auto-compute certain configuration values when validating or generating thedesign. To check whether the values do change, see the description of the parameter in thischapter. To view the parameter value, run the validate_bd_design command in the Tclconsole.
You can customize the IP for use in your design by specifying values for the various parametersassociated with the IP core using the following steps:
1. Select the IP from the IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the VivadoDesign Suite User Guide: Getting Started (UG910).
Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might varyfrom the current version.
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To access the BSCAN to JTAG Converter core, perform the following:
1. Open a project by selecting File → Open Project or create a new project by selecting File → New Project.
2. Open the IP catalog and navigate to Debug & Verification → Debug.
3. Double-click BSCAN to JTAG Converter to bring up the BSCAN to JTAG Customize IP dialogbox as shown in the following figure:
Figure 3: BSCAN to JTAG Core View in IP Catalog
The following figure shows the BSCAN to JTAG Customize IP dialog box with information aboutcustomizing ports. A configurable parameter is shown named as enable_tck_bufg thatenables a buffer on the clock path of JTAG output.
• Component Name: The Component Name field consist of any combination of alpha-numericcharacters including the underscore symbol. However, the underscore symbol cannot be thefirst character in the component name.
• Enable tck bufg: This user parameter is enabled only if a BUFG is required for tck in highspeed applications.
Chapter 5: Design Flow Steps
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Figure 4: Vivado Customize IP Dialog Box
Output GenerationFor details, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Constraining the CoreRequired Constraints
This section is not applicable for this IP core.
Chapter 5: Design Flow Steps
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Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
This section is not applicable for this IP core.
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.
Synthesis and ImplementationFor details about synthesis and implementation, see the Vivado Design Suite User Guide: Designingwith IP (UG896).
Chapter 5: Design Flow Steps
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Appendix A
DebuggingThis appendix includes details about resources available on the Xilinx® Support website anddebugging tools.
If the IP requires a license key, the key must be verified. The Vivado® design tools have severallicense checkpoints for gating licensed IP through the flow. If the license check succeeds, the IPcan continue generation. Otherwise, generation halts with an error. License checkpoints areenforced by the following tools:
• Vivado Synthesis
• Vivado Implementation
• write_bitstream (Tcl command)
IMPORTANT! IP license level is ignored at checkpoints. The test confirms a valid license exists. It does notcheck IP license level.
Finding Help on Xilinx.comTo help in the design and debug process when using the core, the Xilinx Support web pagecontains key resources such as product documentation, release notes, answer records,information about known issues, and links for obtaining further product support. The XilinxCommunity Forums are also available where members can learn, participate, share, and askquestions about Xilinx solutions.
DocumentationThis product guide is the main document associated with the core. This guide, along withdocumentation related to all products that aid in the design process, can be found on the XilinxSupport web page or by using the Xilinx® Documentation Navigator. Download the XilinxDocumentation Navigator from the Downloads page. For more information about this tool andthe features available, open the online help after installation.
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Answer RecordsAnswer Records include information about commonly encountered problems, helpful informationon how to resolve these problems, and any known issues with a Xilinx product. Answer Recordsare created and maintained daily ensuring that users have access to the most accurateinformation available.
Answer Records for this core can be located by using the Search Support box on the main Xilinxsupport web page. To maximize your search results, use keywords such as:
• Product name
• Tool message(s)
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
Technical SupportXilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP productwhen used as described in the product documentation. Xilinx cannot guarantee timing,functionality, or support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
To ask questions, navigate to the Xilinx Community Forums.
Debug ToolsThere are many tools available to address BSCAN to JTAG Converter design issues. It isimportant to know which tools are useful for debugging various situations.
Appendix A: Debugging
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Appendix B
Additional Resources and LegalNotices
Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.
Documentation Navigator and Design HubsXilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. To open DocNav:
• From the Vivado® IDE, select Help → Documentation and Tutorials.
• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. To access theDesign Hubs:
• In DocNav, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.
ReferencesThese documents provide supplemental material useful with this guide:
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1. Vivado Design Suite User Guide: Designing with IP (UG896)
2. Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898)
3. Vivado Design Suite User Guide: Logic Simulation (UG900)
4. Vivado Design Suite User Guide: Implementation (UG904)
5. Vivado Design Suite User Guide: Programming and Debugging (UG908)
6. Vivado Design Suite User Guide: Getting Started (UG910)
7. Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940)
8. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
Revision HistoryThe following table shows the revision history for this document.
Section Revision Summary10/30/2019 Version 1.0
Initial release. N/A
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Appendix B: Additional Resources and Legal Notices
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www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms containedin a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe orfor use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which canbe viewed at https://www.xilinx.com/legal.htm#tos.
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© Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex,Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the UnitedStates and other countries. All other trademarks are the property of their respective owners.
Appendix B: Additional Resources and Legal Notices
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