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Presented by:Kal Kalbasi
Q & AMarc Petersen
Bridging the Gap between System & Circuit DesignersBridging the Gap between System & Circuit Designers
October 27, 2004
© Copyright 2003 Agilent Technologies, Inc.
Bridging the Gap between System & Circuit Designers Oct 2004
The Gap …
System
System SpecsBER/PER, EVM, CCDF,
…
RF Circuit SpecsNF, P1dB, TOI , …
?
Communication System Design
RF Block-level Circuit Design
Circuit
Problem:
System Design Remains an “Island” …
Circuit Designs Should Meet System Specifications
Problem:
System Design Remains an “Island” …
Circuit Designs Should Meet System Specifications
Bridging the Gap between System & Circuit Designers Oct 2004
Agenda
Meet the Standards & Specification• System & Circuit (Design & Verification)
– Bridging the Gap
• Case Study– WLAN Transmitter/Receiver
• Integration (RF + baseband + …)• Bench Verification
Bridging the Gap between System & Circuit Designers Oct 2004
UserDevice
UserDevice
Wireless Interconnect802.15 WPAN's
Bluetooth, WiMediaUWB, ZigBee
Wireless Networking802.11x WLAN
Broadband Access802.16 WMAN's
802.16e/HPI802.20, 802.18
DOCSISWiMax
Proprietary3G2G2.5G
CWTS
GSM
3GPP
IS-136IS-95A/B
GPRSHSCSD
TD-SCDMAEDGE
3GPP2
1xEV-DOcdma2000 W-CDMA
W-TDDW-CDMA
FDD
ECSD
W-CDMAN-TDD
1xEV-DV
DECT
EGPRS
4G
More Standards, Complexity, InteroperabilityMore Standards, Complexity, Interoperability
Meet the Standards
Bridging the Gap between System & Circuit Designers Oct 2004
Meet The Specification …Comms Theory
TRX Architecture
IC Design
Test & Measurement
Multiple Access
Signal Propagation
Microwave Theory
RFSystemDesign
RFCircuit Design
Supply Voltage Gain
Freq
3rd party IP
EM/Parasitic effects
MMIC
RF Integration
RFVerification
Standards
Specification
Standards
Specification
Noise Power
Linearity
BasebandDesign
Off-chip modules
Other RFICs
Instrument In the loop
Measurement Algorithms
Wireless Standards
WirelessTest Bench
Bridging the Gap between System & Circuit Designers Oct 2004
Evolving Design & Verification Challenges
x I/Q DSP
x
ANALOG / DIGITAL
CONTROL & PROCESSING
I/Q DSP
BASEBAND DATA / VOICE
BasebandRFIC
Design ChallengesArchitecture DC Offset, baseband/RFMulti-mode On-/Off-chipMiniaturization Technology
Verification Challenges•Verification up to 70% of design cycle•Continuous/consistent verification with key metrics BER/FER, EVM •Real world signals (modulated, wideband & wide dynamic range)
Tool integration (system, circuit, ..instruments) is neededTool integration (system, circuit, ..instruments) is needed
Bridging the Gap between System & Circuit Designers Oct 2004
Improved Flow (System + Circuit)
Solution:
Transplant System Test Bench (EVM, BER) On Circuit Page↓
Capture Circuit Distortions at System Level ↑
Solution:
Transplant System Test Bench (EVM, BER) On Circuit Page↓
Capture Circuit Distortions at System Level ↑
Communication System Design
RF Block-level Circuit Design
Layout
System SpecsBER/PER, EVM, CCDF, …
RF Circuit SpecsNF, P1dB, TOI , …
Bridging the Gap between System & Circuit Designers Oct 2004
Bridging the Gap in ADS
Analog/RF
ADS Ptolemy
Circuit Subsystem on System Page
System Benchon Circuit Page
Bridging the Gap between System & Circuit Designers Oct 2004
Wireless Test Bench Dynamic Link
ADS Ptolemy
Bridging the Gap in RFDE
Circuit Schematics in Cadence Virtuoso
Bridging the Gap between System & Circuit Designers Oct 2004
Agenda
• Meet the Standards & Specification– System vs.. Circuit (Design & Verification)– Bridging the Gap
Case Study– WLAN Transmitter/Receiver
• Integration (RF + baseband + …)• Bench Verification
Bridging the Gap between System & Circuit Designers Oct 2004
Transmitter Block Diagram
IQ ModulatorBaseband
Source
RFDE
Signal Band 5.3 GHzTransmitter Output Power 12 dBm maxModulation (PSK+QAM) 4,16, 64 QAMOccupied BW 16.6 MHzChannel Spacing 20 MHzData Rate (Mbps) 6,9,12,18,24,36,48,54
Transmitter EVM -25 dB (< 5.6% rms)PA 11 dB linear gain Pre-amp ~ 25 dB of gain VCO Phase Noise on EVM?
Ideal Mixer
Bridging the Gap between System & Circuit Designers Oct 2004
System Level Transmitter
0.38 GHz
5.2-0.38 GHz
5.2 GHz 20 MHz
Gain =11 dBTOI = 34 dBm1dBc=21 dBm
25 dB
For 54 Mbps EVM should not exceed 5.6 (%RMS)
Bridging the Gap between System & Circuit Designers Oct 2004
Circuit Verification
Bridging the Gap between System & Circuit Designers Oct 2004
802.11a EVM & CCDF Bench
Pin=-40
Pin=-37
Pin=-34
Pin=-31
Pin=-28
Pin=-25
Pass
Fail5.6
-34 dBm
Bridging the Gap between System & Circuit Designers Oct 2004
Rx system and circuit specifications
CircuitInput Signal Band 5.3 GHz
Receiver NF < 6 dB
LO Phase Noise -110 dBc/Hz @1 MHz
Conversion Gain 30 dB
LNA 8 dB
Mixer 12 dB
IF Band 100 MHz
IIP3 (Mixer) > 5 dBm
P1dB -10 dBm
Input Dynamic Range -80 to -30 dBm
SystemInput Signal Band 5.3 GHz
Receiver NF 6 dB max
Modulation (PSK+QAM) 4, 16, 64 QAM
Occupied BW 16.6 MHz
Data Rate 6,9,12,18,24
,36,48,54
Receiver EVM -28 dB
PER {-30 to -80 dBm} < 10%
Bridging the Gap between System & Circuit Designers Oct 2004
System Level Receiver (Baseband + RF)
RF Behavioral
Transistor Level --Verilog
TransmitterReceiver (BB)
Receiver (IF)89600 Glacier Software
Bridging the Gap between System & Circuit Designers Oct 2004
Receiver Front-end
÷2
MatchingNetwork
Receiver
MeasurementEVMBEREyeSpectrum
Baseband
Bridging the Gap between System & Circuit Designers Oct 2004
LNA Circuit AnalysisS-parameter Gain and MatchNoise FigureGroup delay
AC AnalysisAC Voltage gainAC Noise Analysis
Harmonic BalancePin / Pout-1 dB compressionTwo tone analysis
2.6 dB Noise figure Corresponds to 9.14 dB GainMaximum Gain = 14.5 dB
Bridging the Gap between System & Circuit Designers Oct 2004
Harmonic Balance Analysis
fc5.3 GHz
100 kHz
Bridging the Gap between System & Circuit Designers Oct 2004
Envelope Analysis w Modulated Source
Bridging the Gap between System & Circuit Designers Oct 2004
LNA Subsystem with Modulated Source
Bridging the Gap between System & Circuit Designers Oct 2004
EVM @ Different Nodes
+ Noise
LNA
Bridging the Gap between System & Circuit Designers Oct 2004
IQ Imbalance & Filter Bandwidth
Bridging the Gap between System & Circuit Designers Oct 2004
LNA 802.11a Tx Test Bench Analysis
Bridging the Gap between System & Circuit Designers Oct 2004
Bridging the Gap between System & Circuit Designers Oct 2004
CCDF, Peak/Ave Power Ratio, EVM
Bridging the Gap between System & Circuit Designers Oct 2004
802.11a Rx Input Level & Sensitivity
Data Rate (Mbps)6
Minimum sensitivity (dBm)
-82
9
12
18
24
3648
54
-81
-79
-77
-74
-70-66
-65
Minimum input level (Sensitivity) the minimum RF signal level required to achieve a Packet Error Rate (PER) <10% at PSDU length of 1000 bytes.
Maximum input level
The receiver shall provide a maximum PER of 10% at a PSDU lengthof 1000 bytes, for maximum input level of –30dBm at the antenna for all data rates.
Bridging the Gap between System & Circuit Designers Oct 2004
Modeling
Simulator ModelData
Simulator ModelData
Model
Behavioral Model
Verification Models(VME & AVM)
Transistor level Models
Measurement-based Models
Accuracy
Speed
Bridging the Gap between System & Circuit Designers Oct 2004
Modeling for Efficient Verification
• Static nonlinearity (output is strictly dependent on the input.)
• Colored noise modeled as input noise source.
• An FIR filter at the input or the output.
Input Magnitude
input phase
Frequency
Bridging the Gap between System & Circuit Designers Oct 2004
LNA Subsystem Model
Simulation time (AVM) using stored model =7 sec
Simulation time (standard cosim) = 420 sec
60 times Faster!
Bridging the Gap between System & Circuit Designers Oct 2004
LNA Model Accuracy
Bridging the Gap between System & Circuit Designers Oct 2004
LNA Receiver Sensitivity Bench
Bridging the Gap between System & Circuit Designers Oct 2004
LNA Subsystem Receiver Sensitivity
Circuit noise ONSource R @ 16 deg C (Eb/N0 defined at input)
Date Length =1000Bursts = 100Data Rate = 54 Mbps
Bridging the Gap between System & Circuit Designers Oct 2004
Down Converter Test Bench
Bridging the Gap between System & Circuit Designers Oct 2004
BER/PER vs. Gain Imbalance
Ph Im = 0Ph Im = 10Ph Im = 20
Bridging the Gap between System & Circuit Designers Oct 2004
Agenda
• Meet the Standards & Specification– System vs.. Circuit (Design & Verification)– Bridging the Gap
• Case Study– WLAN Transmitter/Receiver
Integration (RF + baseband + …)• Bench Verification
Bridging the Gap between System & Circuit Designers Oct 2004
Integration & Verification Challenges
Problem
How to Seamlessly Integrate RF & Baseband ?
How to Reduce the High Verification Cost?
Problem
How to Seamlessly Integrate RF & Baseband ?
How to Reduce the High Verification Cost?
RF Block-Level Circuit Design
Communication System Design
Integration
Baseband C++, System C
System SpecsBER/PER, EVM, CCDF, …
EM
System Verification
C++, System C
Bridging the Gap between System & Circuit Designers Oct 2004
Agilent Tools for Design & Verification
Simulation Technology
Cosimulation IP integration
Connected Solutions
RF
PtolemyPtolemy
TSDFTSDFENVENV TranTran
AC/DCAC/DC
HBHB
SPSP
MoMMoMOptOpt
Bridging the Gap between System & Circuit Designers Oct 2004
Baseband Integration
Fixed point Filter
HDL Cosim Compiled and Script
Options
Symbolic Defined Components
Bridging the Gap between System & Circuit Designers Oct 2004
Updating Test Bench (Phase Noise)
Simulate 3 Phase noise options
• Ideal Oscillator
• 30 Hz 3dB BW
• 3Hz 3dB BW
With potential transmitter EVM impact
Ideal-3dB linewidth=30Hz=0.01% of subcarrier spacing
-3dB linewidth=3Hz=0.001% of subcarrier spacing
Bridging the Gap between System & Circuit Designers Oct 2004
Exporting Modified Test Bench
1. Modify a template design
2. Leave circuit out with ports
3. Place desired measurements
4. Verify before export
5. Export
34
1
2
5
pre/post-tapeout
Bridging the Gap between System & Circuit Designers Oct 2004
EVM Results with Phase Noise
-37 dBm
-34 dBm PassFail
Max %EVM (rms) for 54 Mbps is 5.6%
5.6
The new test bench includes Oscillator PN as a new option
Bridging the Gap between System & Circuit Designers Oct 2004
Agenda
• Meet the Standards & Specification• System vs.. Circuit (Design & Verification)
– Bridging the Gap
• Case Study– WLAN Transmitter/Receiver
• Integration (RF + baseband + …)Bench Verification
Bridging the Gap between System & Circuit Designers Oct 2004
On Bench Verification
ESG Sig. Gen.
Signal Analyzer
Signal To ESG
Connection Manager
Bridging the Gap between System & Circuit Designers Oct 2004
Simulated vs. Measured for Tx Amplifier
0
2
4
6
8
10
12
14
16
-40 -37 -34 -31 -28 -25
FailPass
5.6% EVM Max,54 Mbps
Input Power dBm
% E
VM
Power amplifier behavior under system conditions shows good agreement with system simulation results.
Simulated
Measured
Bridging the Gap between System & Circuit Designers Oct 2004
Measured Results with Phase Noise
RF Input Simulated EVM w/o Phase Noise
Measured EVM w/o Phase Noise
Simulated EVM with Phase Noise
Measured EVM with Phase Noise
-34 dBm 4.38% 4.33% 5.36% 5.07%
Bridging the Gap between System & Circuit Designers Oct 2004
Summary
System Circuit• Meeting the wireless specifications is a must for circuit & system
designers• Using an improved flow
• system designers can communicate specs more effectively • circuit designers can verify system specs in their own home base
• ADS provides system level analysis + test bench export• RFDE provides verification in the Cadence flow
Bridging the Gap between System & Circuit Designers Oct 2004
Q & A
Bridging the Gap between System & Circuit Designers Oct 2004
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