ee457_Lab6_Part4_r3_for_lecture.fm

10/29/06 19 / 32 C Copyright 2006 Gandhi Puvvada

RegInstr.

Data

FU

PC

IF ID EX MEM WB

Zero

Zero

BRANCH

BR

15-stage pipeline of the late-branch design of the 1st edition

HDU

contr

ol

RegInstr.

HDU

Data

FU

IF ID EX MEM WB

BRANCH

BR

1

5-stage pipeline of the early-branch design of the 3rd ed. and our lab 6

FU_Br

PC

cont

rol

HDU_Br

Zero

RegInstr.TLB

Instr.cache

DataTLB

Datacache

FU

PC

IF1 IF2 ID EX MEM1 MEM2 WB

Zero

Zero

BRANCH

BR

1

7-stage pipelined version of the late-branch design of the 1st edition

HDU

contr

ol

RegInstr.TLB

Instr.cache

HDU

DataTLB

Datacache

FU

IF1 IF2 ID EX MEM1 MEM2 WB

BRANCH

BR

1

7-stage pipelined version of the early-branch design of the 3rd ed. and our lab 6

FU_Br

PC

cont

rol

HDU_Br

Zero

All

4 pi

pelin

es