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BY
Vishwanath c.
1
st
SEM MTECH(VLSI AND EMBEDDED SYSTEMS)
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` DAC is the device that converts digital code into
analog signal( current, voltage or electric charge)
` It schematically includes
Current referenceDac cell array
Dac array decoding logic
Wide swing current mirror with enhanced output
impedence
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` Resolution
` Maximum sampling rate
` Monotonicity
` Total harmonic distortion` Differential non linearity
` Integral non linearity
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` Digital inputs in the form of twos compliment
binary no and out in terms of voltage,
schematically it consists of
` Current reference` Dac cell array(12 bit)
` Dac cell array decoding logic(row64 &col64)
` Wide spread current mirror with enhanced output
impedence(icurrent mirror)
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` Sensitive to noise SNR (signal-to-noise ratio).
` Subject to device nonlinearities THD (total
harmonicdistortion).
` Sensitive to device mismatch and process variations.
` Difficult to design, simulate, layout, test, and debug.`
Inevitable, often limits the overall system performance.
` Scaling scenario:
` Enjoyed scaling until ~0.35-m technology node.
` High-speed, low-resolution ADCs keep benefiting.
` High SNR design difficult to scale with low supplies (
3.3V
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THD is defined as the square root of the ratio of the sum of all
of the
squared second, third, and higher harmonics to the magnitude of
the
fundamental harmonic.
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` Verilog top,verilog structured Net list
` Keep testbenches and model digital
` Analog signals in digital netlist
` System verilog assertions
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` Analog faults
` Presently used analog tests in the industry
` Analog fault modelling/simulation
` Design for test` BIST
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` If the chip has an onchip ADC,DAC and dsp then
they test themselves.
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` Polarity of I/O and control signals
` Dependency on control signals
` Dependency of analog signals
` Timing signals` Bandwidth/slew rate
` Voltage limits
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` Introduces analog verification planning
` constraint random verification for analog nodes
` Assertions on analog code
` Analog code coverage and functional codecoverage
` Regression management
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` AMS assertions
Immediate assertions
Concurrent assertions
AMS checkers
o Threshold checker
o Window checker
o Slew rate checker
o Frequency checker
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` Ability of mixed signal router to understand analogrouting
constraints
` Ability to view the complete design in digitalenvironment
` The ability to mix analog and digital designs insame area
without hierarchy constraints
` Digital timing closure that covers all digital logicand
paths
` Chip assembly routing supports complex analogenvironments as
well as high capacity digitalneeds.
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THANK YOU
