Bipolar IC Process

8/9/2019 Bipolar IC Process

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Wirebond connction to header

!eal pac"age

Bipolar IC #abrication !teps

The starting material is a p$type single crystal silicon wafer ha%ing & to '( ohm$cm resisti%ity

and thic"ness of approximately se%eral hundred micrometers. The diameter can be &() *&)

+(() +'&) or +&( mm. The most standard sie is +(( mm or about , inches

+. - thin layer of !iO2is formed on all surfaces of a p$type silicon wafer by exposing it

to oxygen or water %apour in an electric furnace. The first mas"ing step defines the

area for n+buried layers) also called sub$collector/. The function of this layer is to

reduce the collector resistance of the transistor. The !iO2is remo%ed in these areas by

chemical etching. Thermal diffusion or ion implantation forms the desired hea%ily

doped n$type) that is) n+buried layer region. The resulting structure is shown in the

figure below.

'. The !iO2mas"ing layer is remo%ed) exposing the entire silicon wafer surface. By

epitaxial deposition) an n$type layer is grown) o%er the entire surface. It is n$type

single$crystal silicon ' to & micro meter thic" with its resisti%ity in the range of (.+ to+ ohm$cm. 0uring the epitaxial process) the n$type dopant pre%iously introduced in

the buried layer areas diffuses in all directions. This is shown in the figure below.

1. The wafer with the epitaxial layer is then oxidied at an ele%ated temperature in an

22O ambient. This forms a layer of !iO2) approximately (.& micro meters thic" o%er

the entire surface of silicon. - second mas"ing step defines a border completely

enclosing n$type islands of silicon that are to be electrically isolated collectors of

transistors. 3$type diffusion into the border areas is continued until the entire epitaxial

layer has been penetrated) as shown in the figure below. Thus) islands of n$type

silicon are bounded on all sides by p$type !i. Isolation is achie%ed by applying

%oltages such that this p$n junction is always re%erse$ biased. The p$type diffusionuses boron as impurity. - new layer of thermal oxide is grown o%er the isolation

areas.

,. The third mas"ing step defines base regions of n$p$n transistors. 3atterns of resistors

are formed simultaneously in separate isolated n$type regions. Boron is again diffused

but this time not as deeply/ or implanted to forms bases and resistors. The n$type

collector is con%erted to p$type when the density of p$type impurities exceeds that of

n$type impurities. The resulting structure is shown in figure below.

&. The fourth photolithographic step defines n$type transistor emitters and n$type regions

for low resistance contacts to collector regions) as in the figure below. -gaincon%ersion of p$type base to n$type re4uires impurity compensation.


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5. -n oxide is again thermally grown o%er the entire wafer and %ia photolithography) &th

mas"/ those regions where contact is to be made to the silicon are defined. 6etal -I/

is then deposited by %acuum e%aporation. The photolithographic process 5 thmas"/ is

then used to define the appropriate metalliation inter$connection pattern) and the

remaining metal is remo%ed. The figure below shows the contact areas defined by & th

mas"/ to collector) base) and emitter. The 5thmas"ing step is not shown in figure.

Bipolar IC 6anufacture !teps

-t this point) the ICs are in finished state. 2owe%er before finished form) a protecti%e

passi%ating layer using glass is deposited o%er the entire wafer. This is "nown as die

passi%ation or scratch protection) or glassi%ation. This protects the surface of the wafer from

contamination. 7lassi%ation is done using chemical %apour deposition. This added step

paysoff in protection before and after pac"aging) in higher yields and in better reliability.

- final mas"ing step remo%es the abo%e insulating layer o%er the pads where contacts will be

made. 8ow the IC chip undergoes a probe test. This is necessary because there are many

faulty chips after such highly complicated fabrication steps. The probe test is automaticallycarried out by contacting the pads of e%ery chip with microelectrode probes. 9egistration of

each chip with respect to the probes is done automatically by final mechanical adjustment.

The chip is then tested using a set of test %ectors) which consist of a se4uence of input

%oltages) stimuli to chip input pads/ and expected output %oltage responses from chip output

pads/ that ha%e been pre%iously generated by the design engineer. If the chip passes all test

%ectors) namely all outputs pro%ide the correct results for all input stimuli then the probes are

automatically stepped to the next chip position and all test %ectors are applied to that chip.

This process is repeated until all chips ha%e been tested. Chips that failed to pass all test

%ectors are mar"ed with an in" dot. 0ue to computer controlled operation of wafer probe

e4uipment) upto +5((( test %ectors are tested for each chip of a wafer in some minutes.


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#aulty chips will be thrown away later. 8ow) the entire wafer is bro"en into indi%idual chips.

This is discussed below.

Chip Separation

The entire wafer is di%ided up into indi%idual chips by :scribe$and$brea"; operation using

any one of the following ways.

0iamond$tipped scribe

2igh$intensity laser beam laser scribing/) or

2igh$speed circular saw

!ince this process is similar to glass culling it is called scribing and brea"ing. In the diamond$

tipped scribe method) the groo%es are %ery shallow. In laser scribing method) the groo%es aresomewhat deeper) and may extend more than halfway through the wafer. In the high$speed

circular saw method) the wafer will ha%e a pattern of orthogonally oriented :scribing streets;

which are "ept clear of oxide and metal and are aligned along certain crystallographic

directions to promote the easy and smooth clea%age of the wafer.

- popular process for chip separation is to use a wafer saw to cut entirely through the wafer.

The wafer is mounted on adhesi%e$coated tape prior to the sawing operation so that after

sawing the chips will remain in matrix form for con%enience in further operations.

#aulty chips are identified using probe test mentioned abo%e. 2ence) only good chips are

mounted in containers. The chips are bonded to either metal headers or ceramic substrate.

The metal headers are usually gold$plated


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@ead Bonding

The IC chip is now encapsulated in a metal) ceramic or plastic pac"age. The plastic pac"age

is the lowest in cost) but the metal and ceramic pac"age offer the ad%antage of pro%iding a

hermetic seal and a higher operating temperature range.

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Bipolar IC Process