Eng. Rev. 307/24/14- 1 of 19 - 2014 TriQuint www.triquint.com Bias Techniques for GaN andpHEMT Depletion Mode Devices John Bellantoni Technical Director Wireless Communications TriQuint, Inc. San Jose CA 95434 Introduction Advances in process technology have led to GaN depletion mode devices finding their way out of research labsandintocommunicationsmarkets.Inmanymicrowavewaveapplicationsforexample,theLDMOS devices that have dominated power amplifier designs are giving way to GaN solutions, particularly the final outputstagewhereefficiencyandlinearityarekeyrequirements.Thehighpowerdensity,highefficiency capability of GaN makes it valuable for microwave applications, and the trend of GaN devices finding their way into future communication systems is predicted to continue.As a result, there are incentives to develop novelbiastechniquesthatprovideproperbiascontrolandtemperaturecompensationfordepletionmode devices. These techniques must be compatible with communication applications where stable operation into highcapacitanceloadsisnecessaryforthewidevideobandwidthsfoundinDohertyconfiguredamplifiers thatcarry4GandLTEsignals.AspHEMTdevicesarewellestablishedinnumerousapplications,the approach is to develop universal techniques that work for any type of depletion mode device. Concepts,practicalcircuitrecommendations,measurementdataanddiscussionarepresentedinthe following sections: 1.0 Design Requirements for Depletion Mode Device Biasing 2.0 Temperature Characteristics of TriQuint GaN Devices 3.0 Temperature Compensation Methodology 3.1Temp Comp Made Easy 3.2Temperature Compensation Techniques 4.0 Stability Considerations 5.0 Low-Cost Analog Temperature Compensation Technique 6.0 DAC Control 7.0 Practical Reference Designs 8.0Lab Verification 9.0 Conclusions 10.0 Acknowledgements Eng 201.0MicperquianguntachbiaopeoccwhMowhfallbe theothpeafinais plowClaconuseThetheclaemcon. Rev. 307/24/1014 TriQuint 0 Depletion crowave rformance isiescentcurgle,thegattilthedeshieved.Theaspointsoeration,whcurs,andthere only 180ost common ere the trads within a usclassified asecarrieramherend,deakingamplifal PA stage paramount tow quiescent cassCbiasinnstantenvee a single deefirststepte gate voltagss of operatmbeddedconntrolmethod

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Rev. 307/24/14- 3 of 19 - 2014 TriQuint www.triquint.com2.0 Temperature Characteristics of TriQuint GaN Devices Whathappenswhenafixedvoltageisplacedat thegateofadepletionmodeGaNorpHEMT deviceandthequiescentdraincurrentmeasured overawidetemperaturerange?Figure1 illustratestheexpectedresult,arbitrarily normalized to 1A range.As carrier concentrations, mobility and Schottky barrier voltages change over temperature,sodoesthedraincurrent.The absolute value of the current does vary from unit to unitbasedonpinch-offvoltagevariationsacross thewafer,asillustratedbythreeunits13inFig. 2(a).On the other hand the temperature slope is a derivative that has much less variation.In addition toastronglineardependence,therearesmall percentages of second and third order terms. This semiconductor physics is remarkably consistent for a given process. Forsaturatedoperationtheabovechangesin quiescent current have little effect on overall output powerorefficiencyperformance.Datapresented inSection4willverifythatafixedgatevoltageis sufficient for saturated power applications. Intheworldofmoderndigitalcommunications linearityandefficiencyarethekeyparameters.Devicesinreceiverchainsandintransmitter blocksoutsideofDPDloopsarerequiredtobe highlylinear.FinalstageDohertyamplifiers, driversandpre-driversinsidetheDPDloopare required to be highly efficient and capable of being linearizedwithrealizablepolynomialfunctions. Maintainingafixedquiescentbiaspointover temperatureisoneoftheessentialtechniquesto realizinghighperformancetransmitterchains capableofmeetingspecificationsoverawide rangeofoperatingconditions.Byadjustingthe gatevoltageovertemperature,thequiescent currentcanbeheldconstant.Figure2presents data from the lab, the actual gate voltages required toholdthequiescentcurrentconstantforseveral differentTriQuintGaNdevicesatvariousdifferent current densities.Similar to the fixed voltage plot, thegatevoltagerequiredtomaintainconstant currentovertemperatureshowsastronglinear dependencewithsmallsecondandthirdorder contributions. Fig. 1. Illustration of depletion mode device quiescent drain current dependence over temperature for fixed gate bias voltage. 0.50.70.91.11.31.5-40 -25 -10 5 20 35 50 65 80 95 110 125Quiescent Drain Current (A)Temperature (C)Bias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 4 of 19 - 2014 TriQuint www.triquint.com (a)(b) (c) Fig. 2. Gate voltage over temperature for GaN devices at constant current density. (a) 120W 32V T1G4012032-FS, three devices at 12.5 mA/mm, (b) 30W 28V T1G6003028-FL, one device at 10 mA/mm and one device at 20 mA/mm, and (c) the 55W 28V T1G4005528-FS, one device at 10 mA/mm. 3.0 Temperature Compensation Methodology 3.1 Temp Comp Made Easy Thesimplestandmostexpedientwayto temperaturecompensateadepletionmodedevice is to ignore the entire subject.Simply apply Vgate, afixedvoltagetothegateandthenacceptany subsequentperformancevariationsover temperature.This bare-bone technique is effective inanumberofapplications.Thefurtheradevice is biased into Class AB and Class C operation, the morelikelythatperformanceusingfixedgate voltagebiaswillbesatisfactory.Saturated modulation schemes and applications with relaxed temperaturerequirementsareallidealcandidates for fixed gate voltage bias schemes. There is a lot to be said for the simplicity shown in Fig. 3. RF_OUTVDDRF_INVgatePALCLC Fig. 3. Standard bias network with fixed voltage Vgate applied to device gate. -3.1-3.0-2.9-2.8-2.7-2.6-2.5-40 -15 10 35 60 85Vgq (V)Temperature (C)Unit 1Unit 2Unit 312.5 mA/mm-4.6-4.5-4.4-4.3-4.2-4.1-40 -15 10 35 60 85Vgq (V)Temperature (C)10 mA/mm20 mA/mm-3.8-3.7-3.6-3.5-3.4-3.3-40 -20 0 20 40 60 80Vgq (V)Temperature (C)10 mA/mmBias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 5 of 19 - 2014 TriQuint www.triquint.com3.2 Temperature Compensation Techniques Advancementofmoderndigitalcommunications systems often pushes the technology envelope.In thesesystemsthetemperatureperformanceof powerdevicesisanimportantfactor.Cellular base stations, microwave point-to-point radios and manyISMapplicationsemploybiastechniques that minimize linearity degradations as the ambient temperature varies over the course of the day and seasons.Therearetwoprimaryapproachesto compensating the bias point of power amplifiers as the temperature changes: Closed Loop Open Loop Closedlooptechniquesmonitorthequantityin question,forexampledevicedraincurrent,and feedthatinformationbacktoacontroller.When the loop is closed by the controller, the quantity in question is maintained at the set-point value, within the accuracy of the monitor. Openlooptechniquesapplythesetpointdirectly to the device and change that set point based on a temperaturesensorwithoutregardtotheactual drain current.The consistencies of semiconductor devicesmakeopenloopcontrolpossible,asthe temperaturecharacteristicdoesnotvary appreciablyfromunittounit.Bothclosedand openlooptemperaturecompensationcanbe furtherdividedintoanalogordigitaltechniques.Figure4andFig.5provideasummaryofbias compensation techniques in block diagram form. Eachapproachhasitsownuniquesetof advantagesandissues.Openlooptechniques havelowermaterialcostthanclosedloopbut requirealignmentatfinaltest,andcanbeless accurateovertemperature.Alignmentcanbea manualprocessorautomatedwithdigitally controlleddevices,suchasanEEPOT,adjusted by the test stand until the desired operating point is achieved.Openloopcontrollerscannot compensateforlongtermdriftofdevices,a phenomenonthathasbeenobservedinearly generationsofsemiconductorprocesses.To account for long term drift with an open loop driver, designerscaneitherignorethedriftortake advantage of the fact that the majority of long term driftoccurswithinthefirsthoursofoperation.Devicesareburned-inbeforefinalalignment,a processsuitableforlimitedvolumeproduction.Digitalclosedlooptechniques(Fig.4)donot requiremanualalignmentorburn-inandcan compensateforlongtermdrift.Howevermaterial costs are higher, the loops require development of PIDcontrolleralgorithmsandthesensorsneedto bestableovertemperature.Complicationsarise withclosedlooptechniqueswhentheamplifier must operate continuously, such as in cellular base stations.InformationfromRFpoweroutput monitoringcouldbeaddedintotheequationsfor thedevicedraincurrentsettings,ortheRF removedduringperiodicmaintenancecycles.This additionalcomplexityisaddressableonlyinthe digitaldomain.Largeanalogsuppliersintegrate digitalmonitorandcontrolfunctionsintoproducts designedspecificallyforclosedloopcontrolof multiple PA stages [1]. EMBEDDEDDACMONITORCURRENTRsenseRF_OUTVDDRF_IN PALCLCGATEDRIVERCONTROLLERADCDIGITAL PID Fig.4.Closedloopbiascompensation.Biasstability overtemperatureisdeterminedbythecurrentmonitor function.TheembeddedcontrollerusesaDigitalPID controller loop to adjust the gate voltage to the required drain current when RF is periodically turned off. Bias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 6 of 19 - 2014 TriQuint www.triquint.comAnalogclosedlooptechniques constantlyrespond tochangesindraincurrent,makingthemuseful onlyforsmallsignalClassAconstantcurrent designs.Thereareseveralwell-knownanalog ClassAclosedloopbiascircuitsthatuseasingle opamp,orevenjustamatchedtransistorpair[2, 3].Blockdiagramsforopenlooptechniquesare providedinFig.5.Thethreetechniquesare similarinthatnomonitoringof the draincurrentis performed.ShowninFig.5(a),amechanical potentiometer is used to set the gate voltage, while aDACreplacesthepotentiometerinFig.5(b).The temperature coefficient of the voltage output is setbytheresistorvaluefromthetemperature sensorfeedingintothesummingfunction.This designfeatureisakeycontributiontothe discussionofClassABdevicetemperature compensation.Inthepasttightcouplingbetween thetemperaturesensorandRFdevicewas requiredtotrackgatevoltage.Fortheopenloop designspresentedhere,thetemperaturesensor coefficientcanbearbitrarybecauseitisscaled whenenteringthesummingfunction.Therefore thetempsensordoesnotneedtobeclosetothe RFdeviceanditsoutputdoesnothavetomatch theRFdevice.Figure5(c)differsinthatthe embeddedcontrollerreadsthetempsensor,and then using a look-up table or interpolation trims the gate voltage to the needed value.Since the look-up table scales the temperature sensor coefficient, the response of the sensor can be arbitrary relative totheRFdevice,allowingforawideflexibilityin the selection of the temperature sensor. RF_OUT RF_IN PALCLCGATEDRIVERSet_PointVDD+VSENSORTEMPPALCGATEDRIVERSENSORTEMPRF_OUTLCVDDRF_INEMBEDDEDDACCONTROLLER (a)(b) PALCGATEDRIVERSENSORTEMPRF_OUTLCVDDRF_INEMBEDDEDDACCONTROLLERADC (c) Fig. 5. Open Loop Bias Control Techniques.Gate driver controlled by (a) mechanical set-point and temperature sensor, (b) DAC set-point and temperature sensor and (c) all digital control. Bias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 7 of 19 - 2014 TriQuint www.triquint.com4.0 Stability Considerations Operationalamplifiercircuitsareproneto oscillationswhendrivinglargeloadcapacitances.Whenacapacitorisaddedtotheoutput,apole appears in the response as shown in Fig. 6.While thegainstartstodropat40dB/octaveinsteadof 20dB/octave,thepotentialforinstabilityarises whenthephaseexceeds180degreesbeforethe gainislessthan0dB[4,5],asufficientcondition for oscillation. There are a number of ways to avoid the oscillation condition.Thesedesigntricksaresummarized inFig.7.Eachhasitsownadvantages.InFig. 7(a)aseriesresistorisolatesthecapacitiveload fromtheopampfeedbackloop.Simpleand guaranteedtoalwayswork,theseriesresistance willneedtobelargeenoughtoavoidoscillations.Howeverifthereisappreciablegatecurrentflow, theseriesresistanceisanimpedimenttogetting themaximumperformanceoutoftheRFdevice.Currentflowintothegate,typicalofpHEMT devicesastheyapproachcompression,willpull the gate voltage more negative, shutting the device off.Fordesignsthathavenegligiblegatecurrent flow the series resistor is a preferred approach. Voltageregulatorsaredesignedtodrive essentiallyunlimitedlargecapacitancesasshown inFig.7(b).Thiscanbeusefulformodern Fig. 6.Bode plot for op amp with and without capacitive loading CL [6]. The capacitor loading adds a pole to the response.The pole quickly sends the phase to more than 180 degrees while the gain is still greater than 1, a sufficient condition for oscillation. Bias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 8 of 19 - 2014 TriQuint www.triquint.comDohertyAmplifiersinmulti-carrierenvironments, wherevideobandwidthsgreaterthan100MHz requiresignificantbypassing.Commonlyfoundin thesecommunicationamplifiersarelarge capacitorsplacedinshuntasclosetothegateas possible.Thedisadvantagetothevoltage regulatorapproachisadditionalcomponentcount andassociatedcost.Inaddition,apower consumingshuntresistorisrequiredtomaintain minimumcurrentthroughtheregulatorandsink anynegativecurrentflowfromthegate.Despite thelimitednegativecurrenthandlingcapability, many familiar with using bench power supplies and shuntresistorswillfindappealingsimilaritytothis approach. GainmaybeaddedasshowninFig.7(c).Capacitiveloadingcapabilityincreases proportionallytothegain[6].Asthegain increases over 5X the loop dynamics are such that theaddedcapacitivepolefallsoutsidetheloop bandwidth.Oftentheuseoflargegainsisnot ideal,asthedynamicrangeoftheDACis compressed by the gain in the driver. Anotherapproachemployedinthisworkislead-lagcompensationshowninFig.7(d),adualloop topology.Asecondloopaddedtothefeedback pathplacesazeroinproximitytothepolethus canceling them out [6, 7].The references give the impressionthatthiscancellationapproachis difficult to implement.While true for high speed op ampsandstringentovershootspecifications,the applicationhereisatDCwheredistortionofhigh frequency signals is not a consideration.With the rightcomponentvalueselection,includingthelow GBWopampsemployedhere,awiderrangeof loadcapacitancescanbetoleratedwithdual feedback.Thedesigncanhandlegatecurrent flow without appreciable voltage error as the series resistor is within the feedback loop.The dual loop feedbackconfigurationhasitsadvantages, howeverthereisstillthepotentialforinstability underexcessivecapacitiveloadingconditions. Commonpracticeistoemployvarious combinationsofisolation,gainanddualfeedback for universal gate driver designs. VgateR_IsoC_LOAD (a) VgateVoltageRegulatorVoGndVi VinC_LOAD Rs-V (b) Vgate4RRC_LOAD (c) RsRfbCfbVgateC_LOAD (d) Fig. 7.Stability techniques for driving capacitive loads.(a) Isolation Resistor, (b) voltage regulator, (c) gain, and (d) dual feedback loop. Bias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 9 of 19 - 2014 TriQuint www.triquint.com5.0 Low-Cost Analog Temperature Compensation Techniques ConventionalPNjunctionsareoftenemployedas temperaturesensors.Empiricalworkhasshown that the PN junction of a BJT device is linear over awidetemperaturerange.Inthisworkageneric PNPdeviceisemployedasthePNjunction temperaturesensor.Alow-cost,singlewire sensor can be formed with the collector of the PNP transistorconnectedtoground.UsingaPNP transistor allows die attachment to ground in hybrid assembliesanduseofpackagedpartswith surface mount technology.The single wire sensor simplifieslayout&RFbypassingcomparedto thermistors employed in feedback loops [8]. Figure 8 illustrates the principle of operation for the low-costgatedriverwithtemperature compensation.Bufferedbyaninvertingamplifier thatuseshalfthediodevoltageasreference VREF,theoutputofthecompletetemperature sensoris0Vatroomtemperature,oftentakento be+25C.Inrealitypoweramplifierheatsinks experience a temperature rise in the vicinity of the powerdevicewhentheambienttemperatureis held to +25C.So the bias resistor R_Bias to the PNjunctionisadjustedtoachieve0Voutputat whatevertemperatureequilibriumisachievedat the ambient temperature setting.Thetemperaturesensor0Voutputat+25C ambienttemperatureprovidesaconvenientinput toagroundreferencedsummingjunction.The advantage of the summing junction is that at room temperaturethecurrentthroughR_Slopeiszero, allowingtheDACtosetthegatevoltage independentofthetemperaturesensor.Asthe temperatureincreases,V_TSwillalsoincrease, sending current into the summing junction through R_Slope.When temperature decreases, V_TS will decreasebelow0V,pullingcurrentoutofthe summingjunction.Byadjustingthevalueof R_SlopethechangeinoutputvoltageVgateover temperature can be set. Since the temperature response is set by the value of R_Slope, the temperature sensor does not have tobetightlycoupledtotheRFdevice.Nordoes thetemperaturecoefficientofthesensorneedto beknown.Whateverthecoefficientandthermal couplingmaybe,itisscaledintotheappropriate currentatthesummingjunctionbyR_Slope. Fig. 8. Low cost temperature PNP sensor and ground referenced summing junction forms temperature compensated gate driver. R1=R2, R3=R_Offset.R_Bias is adjusted to set V_TS=0 at ambient temperature conditions.V_REF is set to the PNP Vbe voltage.The PNP temperature sensor often requires a bypass capacitor to avoid RF interactions. R3VgateR_SlopeR2R_OffsetR1DACPNPR_Bias+5VV_TSV_REFA1A20VBias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 10 of 19 - 2014 TriQuint www.triquint.comThatallowsarbitrarytemperatureslopestobe achievedwithafixedtemperaturesensor coefficient,asshowninFig.9.Incontrastmany previousClassABopenloopdriversrequiretight thermalcouplingbetweenamatchedtemperature sensor and the transistor fingers of the RF device.The use of a summing junction eliminates the need fortightthermalcouplingofthetemperature sensorandinteractionsbetweentheoffsetand slopeadjustments.Whattheapproachdescribed heredoesnoteliminateistheneedtoalign quiescentcurrentatfinaltest,aprocessthatis easily automated using DAC or EEPOT control. The final result is provided in Fig. 10.The voltage from the gate driver is superimposed on the actual gate voltage required to hold a constant quiescent currentovertemperature.Thisfirstorderlinear correctionholdsquiescentcurrentconstantover temperature,withonlythesmall2ndorderterm contributing to error. (a) (b) Fig. 9.Output voltage V_Gate over temperature for three values of R_Slope.(a) Voltage output at 0.75V for pHEMT device, and (b) voltage output at 3.4V for a GaN HEMT device. Fig. 10. Gate driver voltage provides 1st Order (linear) approximation to the required gate voltage for constant IDQ.T1G4005528-FS, IDQ=10mA/mm -1.0-0.9-0.8-0.7-0.6-0.5-55 -35 -15 5 25 45 65 85 105 125Gate Voltage (V)Temperature (C)Rs=25 kRs=50 kRs=75 k-4.0-3.8-3.6-3.4-3.2-3.0-55 -35 -15 5 25 45 65 85 105 125Gate Voltage (V)Temperature (C)Rs=50 kRs=100 kRs=200 k-3.70-3.65-3.60-3.55-3.50-3.45-3.40-40 -15 10 35 60 85Vgg (V)Temperature (C)Gate Driver VoltageConstant IDQGate VoltageBias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 11 of 19 - 2014 TriQuint www.triquint.com6.0 DAC Control Initializationofdigitaltoanalogconverterstakes time while the processor boots up, loads the image andexecutescommands.Duringthisstartup intervalmostDACSwillprovide0Voutput,ortri-state.With zero volts at the DAC the output of A2 inFig.8willalsobeat0V,anundesirable saturated drain current (IDSS) condition for depletion mode devices.Under saturated channel operation inadequateheatsinkinginlinearapplicationswill resultinjunctionoverheatinganddecreased device reliability.Whats needed is a simple circuit techniquethatprovidespinch-offgatevoltage ratherthanzerovoltswhiletheDACisbeing initialized.The addition of a simple inverting buffer as shown in Fig. 11 accomplishes this initialization state.WiththeDACatzerovoltsduring initializationtheoutputofA3isatthefullscale DACvoltage.InvertingthroughA2,thepinch-off gatevoltageisappliedtothedepletionmode device. DACsoftendrivethegatedirectlyinclosedloop systemsandautomatedteststands.Duringthe initializationperiodwhentheDACisatzerovolts, a non-inverting circuit with offset provides pinch-off voltagelevels.Figure12showsthenon-inverting bufferandoutputvoltageovertheDACrange.The resistor divider R1-R2 at the DAC output is not onlyneededtomakethevoltageratioswork;for DACsthattri-stateduringinitializationtheshunt resistorkeepstheDACoutputat0Vandthusthe gate at pinch-off. Fig. 11.Inverting the DAC around its half-scale voltage V_HS sets Vgate to 4V while DAC initialization is completed. R4=R5, R_Offset=R3, V_TS=0V at ambient temperature conditions. Fig.12.DAC controlled gate driver (left) and gate voltage as a function of DAC voltage for V_REF=+4V, R1=R2=10 k, Ros=Rfb=2 k, Rs=25, Cfb=330pF. R3VgateR_SlopeR2R_OffsetR1DACPNPR_Bias+5VV_TSV_REFA1A20VR5R4V_HSA3RsV_REFCfbDAC5VRfbR2RosVgateR1-4-3-2-100 1 2 3 4VGATE(V)DAC Voltage (V)Bias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 12 of 19 - 2014 TriQuint www.triquint.com7.0 Practical Reference Designs Theprinciplesoutlinedhereforlow-costuniversal depletion mode devices bias circuits were followed to develop the two reference designs in Fig. 1314 andthecorrespondingBOMsprovidedinTables 12.Eachdesignhasasafeguardtoinsurethat thegatevoltagedoesnotexceed0V,whichcan damage the device. InthebipolaroutputversioninFig.13,the collectorofQ2Aistiedtoground.IfU1Brails positiveduringthepowerupsequence,thenthe forwardbiasedbasecollectorjunctionholdsthe emittertoapproximately0V.Whenjusttheop amp is used as shown in Fig. 14, a Schottky diode clamp prevents excessive voltages at the gate.Inbothdesigns,R1willneedtobedetermined suchthattheoutputvoltageofU1Aisidenticalto thesummationreferencevoltageatambient temperature conditions and quiescent current. The potentiometerR8issettoprovidetheoptimal temperatureperformance.Oncethesettingis determined,thepotentiometercanbeleftasisor replaced by a fixed value resistor.For applications withdemandingtemperatureperformance requirements,anEEPOTmaybesubstitutedand automatedalignmentperformedoneachunitat final test. Fig. 13.Universal depletion mode bias circuit using complementary bipolar output stage.Stable driving capacitances in the uF range and capable of providing more than +/- 200 mA bi-polar current drive.

-VQ2AQ2BVgate22.0KR722.0KQ124.9KR122.0K1.40K1%1%1% 1%1%3.30K1%DACR61.00K1%R3R2R4R5+5V+5VU1A123R810KU1BU1C+5V-VC10.1uFC20.1uF84R93.30K1%R102.001%C3330pFTable 1.BOM, Universal Bias Circuit, Depletion Mode; Bipolar Output Version Ref. Des.ValueDescription U1n/aLM2904, Op Amp, Dual, General Purpose, MSOP-8 Q1n/aMMBT2907A, Transistor, PNP, 60V, SOT-523 Q2n/aFMB3946, Transistor, NPN/PNP, 40V, 700mW, SOT23-6 C1, C20.1 uFCapacitor, Ceramic, 16V, 10%, X7R, 0402 C3330 pFCapacitor, Ceramic, 50V, 10%, X7R, 0402 R124.9 kResistor, Thick Film, 1/16W, 1%, 0402 R2, R3, R422.0 kResistor, Thick Film, 1/16W, 1%, 0402 R51.40 kResistor, Thick Film, 1/16W, 1%, 0402 R61.00 kResistor, Thick Film, 1/16W, 1%, 0402 R7, R93.30 kResistor, Thick Film, 1/16W, 1%, 0402 R810 kTrim Potentiometer, 1/2W, Top Adj, +/-10% R102.00 Resistor, Thick Film, 1/16W, 1%, 0402 Bias Techniques for GaN andpHEMT Depletion Mode Devices Eng. Rev. 307/24/14- 13 of 19 - 2014 TriQuint www.triquint.comFig. 14.Universal low-cost depletion mode bias circuit.The dual loop topology around U1B maintains stability when driving capacitive loads in the uF range.This approach is suitable for GaN biasing, and other applications under +/-20mA gate current flow.For production R8 may be replaced with a chip resistor once the optimal value is determined. D1BAT60AVgateU1C+5V-VC10.1uFC20.1uF8422.0KR722.0KQ124.9KR122.0K1.40K1%1%1% 1%1%3.30K1%DACR61.00K1%R3R2R4R5+5V+5VU1A123R810KR93.30K1%R102.001%U1BC3330pFTable 2.BOM, Universal Bias Circuit, Depletion Mode; Op Amp Output Version Ref. Des.ValueDescription U1n/aLM2904, Op Amp, Dual, General Purpose, MSOP-8 Q1n/aMMBT2907A, Transistor, PNP, 60V, SOT-523 D1n/aBAT60A, Diode, Schottky, 10V, 3A, SOD-323-2 C1, C20.1 uFCapacitor, Ceramic, 16V, 10%, X7R, 0402 C3330 pFCapacitor, Ceramic, 50V, 10%, X7R, 0402 R124.9 kResistor, Thick Film, 1/16W, 1%, 0402 R2, R3, R422.0 kResistor, Thick Film, 1/16W, 1%, 0402 R51.40 kResistor, Thick Film, 1/16W, 1%, 0402 R61.00 kResistor, Thick Film, 1/16W, 1%, 0402 R7, R93.30 kResistor, Thick Film, 1/16W, 1%, 0402 R810 kTrim Potentiometer, 1/2W, Top Adj, +/-10% R102.00 Resistor, Thick Film, 1/16W, 1%, 0402 Eng 20ThecomFigboacomcomloasiminsbet Flo Ta . Rev. 307/24/1014 TriQuint e circuits wemmontempgure15(a)sardandFimpletedasmparisonofadingprovidmulatingthetantaneous tween zero lFig. 15(b).Comow-cost bias cable 3.BiasCircuit Bipolar Op Amp 14 ere fabricateeraturesenshowstheblg.15(b)isssembly. fthetwocdedisageovershoot stepchaoad and thempact bias bocircuit.Actuas Circuit CoPositive C(mA20020d on a singlsorandaqlockdiagramsaphotogTable3 circuits.Thuidelinedeandsettlinngesinle maximum roard with both l size is 1.25 omparison Current A) N0 e PCB with uadopampmofthebiagraphofthprovides hecapacitiveterminedbngtimesfooadcurrenrating. versions of x 1.325.Negative Cu(mA) 200 20 - 14 of 19 - a p.as e a ve by ornt Fig. 1To savcommPNP sensowas srrentMax.pH TempSensorDAC5(a).Block dve space the montobothctemperature orinputatpinsubstituted for Voltage (V) M0 Bias TechHEMT DeplBipolDriveOp Am DriveDACDACTSTSdiagram of thetemperature scircuits.Ajusensoronthn4oftheconr the DAC. Min. Voltage(V) V + 2.3 V + 1.5 hniques foretion Modewww.trilarermpere experimentasensor and DAumperselectshePCBorennector.ApeCapLoa