UPGRADE OF BPM SYSTEM FOR

PS MULTI-TURN EXTRACTION

IN TT2-TT10

BI day 2011T Bogey CERN BE/BI

2

Outline

Overview to the TTpos system Proposed technical solution Performance of the system

• Lab test• Beam test

Planning for 2012 Conclusions

From PS to SPS: Today

PS

SPS

TT2

TT10BPCL100618

BPCL100509

FT16UDC151

FT16UDC211

FT16UDC251

FT16UDC311

FT16UDC346

FT16UDC368

BPCL100407

BPCL100208

BPCL101302

BPCL101502

BPCL101902

BPCL102073

BPCL102302

BPCL102402

BPCL102573

BPCL102739

BPCL102911

BPCL102963

BMU02tSPS Timing

BMU10tSPS Timing

BPCL TT2 TT10

2 planes 66,5mm

6 14

Cables length 90 430 m 160 620 m

Control SPS

Operational since 2001

SPS BA 1

PS BA Y

Old TT2/10 BPM Electronics

4

Logamp

Diff . Ampli

I to VConverter

LPFilter

LPFilter

I to VConverter

Logamp

A

B

Pos (Vout) [log(A/B)] = [log(A)-log(B)]

LogAmp signals (BW < 4 MHz) are sent to the auxiliary buildings, via coaxial cables

A modified version of MOPOS (SPS Position & Orbit) digitizer, with integrator and 14 bit ADC

To improve S/N ratio two integration times were implemented (100 ns and 1 µs)

Acquisition is identical to MOPOS system(VME power PC & PMC mezzanine)

MP O

OS

Old TT2/10 BPM Electronics

BPM electronic provides one position for each SPS user Timing Issues

Logamp does not offer auto-trigger capabilityBased on digital delay units individual for each BPMsBeam and Calibration timing are differentComplex timing system

• Generation of gate for integratorTTpos LSD VME Card (25nS Clock)• Fast timing ( SPS injection pre-pulses, revolution frequency) for

ADCMOPOS VME Sequencer Card (100nS clock)• Slow timing (SPS GMT) to initialize elementary cycle settingsBE/CO TG8 VME Timing Card (1mS clock)

5

Specifications for PS Multi-Turn Extraction

6

With PS to SPS MTE extraction, we must acquire position for the five PS turns long Batch (5x2µS)

For other bunched beam only one gate acquisition is available.

Actually, all TT2/10 monitors are on the SPS timing. Steering optimization requires that the 6 monitors in TT2 line to be put on the PS timing and controlled by the CPS crew

New front-end electronics with a internal sequencer and a multi gate

acquisition.

From PS to SPS: New system

PS

SPS

TT2

TT10BPCL100618

BPCL100509

FT16UDC151

FT16UDC211

FT16UDC251

FT16UDC311

FT16UDC346

FT16UDC368

BPCL100407

BPCL100208

BPCL101302

BPCL101502

BPCL101902

BPCL102073

BPCL102302

BPCL102402

BPCL102573

BPCL102739

BPCL102911

BPCL102963

CFV-269-BPMTFLPS TimingSPS Timing

CFV-BA1-BPMTFLSPS Timing

Few new cables (daisy chain splitting and coax to moved the electronics away from the BPM to avoid de radiation damages) Individual control and MTG timing for CPS and SPS operation

New TT2/10 BPM Electronics Acquisition System

- VME 64x Digital Acquisition BoardLHC DAB64x

Mezzanine Card- performs Manchester decoding- Xilinx FPGA treats data to give

correct input for DAB64x

Final Configuration- 2 VME Crates- 2x5 DABs with 2x10

Mezzanines2 monitors per DAB

- processing data from 20 PUs

8

Front Endelectronic

Front Endelectronic

Front Endelectronic

Front Endelectronic

Down

Pickup

Up

Left

Right

Front Endelectronic

Signal Conditioner

Daisy ChainDriver

CPU ICV 196A

ICV196B

Con

trol

Dat

a ou

t 1

DAB

DB3

DB4

Up to

700

m

Dat

a ou

t 10

DAB

DB1

DB2

DAB

DB5

DB6

DAB

DB7

DB8

DAB

DB9

DB10

CTRP PS

CTRP SPS

Down

Sequencer

VI ntegrator

ΣI ntegrator

HI ntegrator

Log Amp

Logic

Up - Down

Data out

Control

Up

Lef t

Manchester encoder

Xilinx XC9500 CPLD f amily

Right

U + D + L + R

Right - Lef t

14-Bit ADC

14-Bit ADC

14-Bit ADC

FIFO

200/22 MHzBP Filter

Log Amp

Log Amp

Log Amp

Σ

200/22 MHzBP Filter

200/22 MHzBP Filter

200/22 MHzBP Filter

Pickup

New TT2/10 BPM Electronics

9

Calibrator

DirectionalCoupler

DirectionalCoupler

DirectionalCoupler

DirectionalCoupler

Auto Trigger

BPM Front-end

New electronic Card

10

Position and Intensity available• Large dynamic range without requiring gain switching• Two integration times are implemented (200 ns and 1 µs)

Auto-triggered• No requirement for external timing in the tunnel

Calibrator• Remotely triggered• Single or 40 MHz LHC bunch simulation• It offers 0 dB (center) and ± 5 dB ratio (slope)

Analog to digital conversion• Manchester encoded data between BPM and auxiliary

buildings• Only 1 coax cable per pick-up

Logarithmic Normalization

Each signal is compressed by a logarithmic amplifier, filtered and applied to a differential amplifier.

The position response is:

Pos [log(A/B)] = [log(A)-log(B)] (Vout)

where Vout is the voltage difference between the log-amp outputs.

11

Log-Amp performance

12

Complete, Fully Calibrated Log-Limiting IF Amplifier 100 dB Dynamic Range: –91 dBV to +9 dBV ±0.4 dB RSSI Linearity up to 200 MHz Stable RSSI Scaling: 20 mV/dB Slope Input noise: < 1.5 nV/√Hz

We need less than 70dB dynamic in your application Already used in the TT40/41 (CNGS) line

ER

RO

R –

dB

5

DYNAMIC RANGE ±1dB ±3dB 4 10MHz 86 93

50MHz 90 97 3 100MHz 96 100

2

1

0

10MHz –1

50MHz –2

100MHz

–3

–4

–5

–120

–100 (–87dBm)

–80 –60 –40 –20

INPUT LEVEL – dBV

0 20

(+13dBm)

Log Linearity of RSSI Output vs. I nput Level, at TA = +2 5 C, for Frequencies of 10 MHz, 50 MHz and 100 M H z

12dB Limiter12dB 12dB 12dB 12dB 12dBLimiter

OutI nput

Detector Detector Detector Detector Detector Detector4 X

Detector

LogAmpOut

Attenuator

I -V

Functional Block Diagram for AD8306

Full Wave rms detectors are applied among each stage,by summing theirs output signals, a good approximation to logarithmic transfer f unction is obtained.

Five 1µS gate on CNGS Beam

CNGS MTE 10 µS Batch (2.2E13)2000 bunches spaced by 5 ns

13

Log A

Pos ≈ Log A- Log B

Integrator Out

Integrator Gate

2µS

1µS

Pos turn

1 Pos turn 2

Pos turn 3Pos turn 4

Pos turn

5

2µS 2µS 2µS 2µS

14

0 100 200 300 400 500 600 700 800 900 1000

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

FT16 UDC274 Horizontal Position [mm]

Test on heavy ions

1000 extractions with PB54 ions beam

Extractions

mm

Conclusion and perspectives

15

Electronic productions not yet done (expected to be ready by Xmas)

Installation, test, coaxial cables & NE48 daisy chain modifications during winter stop

Schedule: TT2/10 line will be put into operation after 2011/12 “shut-down”

Thanks for your attention

16

Special thanks to : Lars Jensen, Philippe Lavanchy, CPS & SPS OP team

Test on heavy ions

17

Integrator Gate

Pos ≈ Log A- Log B

Log A

LHC Ion PB54

2 PB54 bunches (2x1.3E10) spaced by 200 nS

200nS