slide 3.1

BGA Crosstalk

Xilinx® Virtex-4™ FPGA and Altera® Stratix® II FPGA

Prepared for XilinxTech On-LineMarch 1, 2005

ByDr. Howard Johnson

Details, measured lab results, theory & practiceHundreds of outputs switching at once

© 2005 Signal Consulting, Inc. All rights reserved. Xilinx is a registered trademark, and Virtex-4 a trademark, of Xilinx, Inc.

Altera and Stratix are registered trademarks of Altera Corporation. All other company and product names may be trademarks of their respective companies.

slide 3.2

Measurement SetupCrosstalk victim

(at scope)

Vcc

Gnd

Vcc

Gnd

Gnd

(min. 7 inches)

Victim

•Stuck high, or

•Stuck low SMA cable

DC Block

Multipleaggressors

(two shown)

BGA package

pcb trace

Test board

slide 3.3

Crosstalk Theory (Basic)

C

LGND I/O current

BGA routing

stuck at zero

Die

A

D

Close

F

PCB ground plane

Load

VCC netSolder ball

PCB power plane

+Substrate

VGLITCH

–

slide 3.4

Crosstalk Theory: Advanced

Gnd

A B C

L1 L3L2

BGA Package

Gnd

D E F

Crosstalk varies depending on the proximity of your signal to the nearest return connection.

slide 3.5

Inductive Crosstalk Affects Drivers and Receivers Alike

+ –

Victim

•Stuck high, or

•Stuck low

Fixed voltageVcc

Crosstalk propagates towards receiver

+ –

Aggressor

Nearby receiver

Vcc

Gnd

+ –

GndCrosstalk propagates away from driver

i(t)

Fixed voltage

slide 3.6

Lab SetupYours truly

Altera Stratix IImodel 2S60F1020 pkg. 32x32 BGA

Xilinx Virtex-4model LX60FF1148 pkg.34x34 BGA

Mark Alexander (designed board)

Isolated power for each side(no common grounds)

• 24 layers• 110 mil thick• 3 I/O power regions• 500 active I/O’s

slide 3.7

VictimXilinx

Virtex-4 LX60

FF1148Package

GroundsSignalsPowers

slide 3.8

Distribution of Crosstalk

SC

Crosstalk contributions from nearby signals

A-10 is back here on the first row

5 mV

Only the nearest aggressors contribute significantly to aggregate crosstalk at position A10.

slide 3.9

Crosstalk at Various Victim Locations

SC

A-10Crosstalk from individual neighbors

5 mV

5 mV

SC

SC

W-25

AP-32

5 mV

5 mV

SC

K-14

slide 3.10

Xilinx Virtex-4 FF1148 Package

Victim A10

The FF1148 package is tessellated with a regular array of power and ground pins, called a “sparse chevron”.

slide 3.11

Crosstalk From One Aggressor

Xilinx Crosstalk

• Stuck high (red)

• Stuck low (blue)

Nearby aggressor 4 mA, fast

200 mV/div

A-10

measured

2 mV/div

2 ns/div

Crosstalk moves opposite the aggressor.

Tek TDS6804B Digital Storage Oscilloscope.8 GHz bandwidth, 20 Gs/s

Direct inputs with 40 inch semi hard-line SMA cables

slide 3.12

Crosstalk from Nearby Aggressors

90 95 100 105 110 115 120 125 130 135 140 145

Aggr 1

23

Crosstalk

2 mV/div

5 ns/div

Tek TDS6804B

A-10

Xilinx

Stagger the aggressors to show each individual crosstalk combination.

slide 3.13

Three Measures of Crosstalk

Spiral Test • 100 outputs, individual

Accumulating Test• 100 outputs, accumulating

Hammer Test• 500 outputs, all together at once

slide 3.14

Package ComparisonXilinx Virtex-4 FF148 Altera Stratix II F1120

Many regions devoid of returns

Returns spread evenly

slide 3.15

Spiral Test Pattern: Xilinx

Victim A10(worst-case location)

GroundsSignalsPowers

Xilinx Virtex-4 LX60

Region exercised by spiral test

All outputs1.5 volt LVCMOS

4 ma, fast

slide 3.16

Spiral Test Pattern: Altera

Victim B7(worst-case location) Altera Stratix II 2S60

Region exercised by spiral test

All outputs1.5 volt LVCMOS

4 ma(no speed option)

GroundsSignalsPowers

slide 3.17

Spiral Test Results: Simulation vs. Measurement

Measured

XILINX

Crosstalk from the nearest 100 locations as observed at position A10

Simulation

XILINX

200 ns/div

Tek TDS6804B Digital Storage Oscilloscope.

8 GHz bandwidth, 20 Gs/sDirect inputs with 40 inch semi

hard-line SMA cables

MathCadSignal positionsPower/ground positionsSignal amplitude and rise/fall time (di/dt)Trace depths

5 mV/div 5 mV/div

200 ns/div

slide 3.18

Spiral-Test Comparison

Xilinx

Altera

Tek TDS6804B

10 mV/div

Xilinx: A101.5 volt LVCMOS

4 ma, fast

Altera: B71.5 volt LVCMOS

4 ma(no speed option)

80 ns/div

100 aggressors shown

Waveforms offset for visual clarity

slide 3.19

Accumulating Crosstalk Test

The cumulative effect grows larger with time…Nearest aggressor

Next nearest

. 1.5 volt LVCMOS4 ma, fast.

.

More distant..

<100 total> same pins as spiral test

The cumulative test exercises the nearest 100 aggressors

slide 3.20

Accumulating Test Comparison

474 mV P-P (Altera)

Tek TDS6804B

68 mV p-p (Xilinx)

Aggressors building up

Aggressors shutting down

100 mV/div

Xilinx: A101.5 volt LVCMOS

4 ma, fast

400 ns/div

Altera: B71.5 volt LVCMOS

4 ma(no speed option)

100 aggressors shown

Waveforms offset for visual clarity

slide 3.21

Final Test: The Hammer

500 ns/div

572 mV p-p (Altera)4.5x crosstalk

Tek TDS6804B

(Waveforms time-shifted for visual clarity)

*powered by a range of voltages including 1.5-volt in the near field

123 mV p-p (Xilinx)Xilinx: A102.5V LVCMOS*

8 ma, fast

100 mV/div

Altera: B72.5V LVCMOS*

8 ma(no speed option)

slide 3.22

Rise/Fall Times

Xilinx A-11 rise/fall

Altera B-6 rise/fall

Tek TDS6804B

2.5V LVCMOS driver*8 ma (fast)

200 mV/div

2.5V LVCMOS driver*8 ma (no speed option)

1 ns/div

The Altera component suffers from two artifacts:Excessively fast rise/fall timeOver-concentration of power/ground balls in core region

Together, these two effects combine to produce a 4.5:1 ratio of observed crosstalk in the hammer test.

*powered by 1.5V

slide 3.23

Crosstalk at Other Locations

Ignore exact pattern of trace layers Assumes average trace depth of 0.035 in.

Ignore differences in rise/fall timeAssume both parts produce di/dt = 2E+07 A/s

Ignore details of dog-bone offsetAssumes via-in-pad for simplicity

Computes worst-case aggregate crosstalk for every pin on both devices, not just the few pins instrumented with SMA jacks.

slide 3.24

Simulated Package Performance

ψ ψ

Xilinx Crosstalk

(Volts)

Altera Crosstalk

(Volts)

simulationsimulation

Simulation assumes all outputs generate di/dt=2E+07 A/s; Consistent via depth of 0.035 in.; Via-in-pad

300 mV 300 mV

slide 3.25

For Further Study

Related articles:www.sigcon.com/Pubs/edn/DataCodingLowNoise.htmwww.sigcon.com/Pubs/edn/TimeforAllThings.htmwww.sigcon.com/Pubs/edn/assymnoisemargins.htmwww.sigcon.com/Pubs/news/3_9.htm “Crosstalk and SSO Noise”www.sigcon.com/Pubs/news/7_10.htm “Scrambled Bus”

Website: www.sigcon.comFull schedule of seminars, Seminar course outlines, SiLab films, Newsletters,Article archives, and much more.

Xilinxwww.xilinx.com/signalintegrity Resources useful for high-speed designerswww.xilinx.com/store/dvd My new SI tutorial for Xilinx RocketIO™ serial transceivers—now available on DVD

slide 3.26

Dr. Howard Johnson

BGA Crosstalk

I’ll be doing public courses in

Boston, MAMarch 7-11, 2005

and Austin, TX

April 11-15, 2005

Questions?