Bev BachmayerBev BachmayerSoftware and Solutions groupSoftware and Solutions group

With special thanks to With special thanks to Matthew Wolf Matthew Wolf Georgia Technical UniversitiyGeorgia Technical Universitiy

Pacifying the Pandora's Box of Parallelism: Pacifying the Pandora's Box of Parallelism: Intel's Curriculum Program for Multi-Core and Intel's Curriculum Program for Multi-Core and Multithreaded ProgrammingMultithreaded Programming

Agenda

• Moving to massively parallel environment

• Intel Academic community

3

Today’s Processors Designed Within New MetricsToday’s Processors Designed Within New Metrics

Moore’s Law continues to be validated Moore’s Law continues to be validated

Multiple cores on-die has become the standard to deliver Multiple cores on-die has become the standard to deliver performance at reasonable powerperformance at reasonable power

10s and 100s of Cores will happen10s and 100s of Cores will happen

Intel Research Chip: 80 core Polaris

Intel® Core™ 2 Duo

(Merom, 65nm Process)

L2 L2

4 Cores4 Cores

L2

2 Cores2 Cores

Intel® Core™ 2 Duo

(Penryn, 45nm Process)

4

10s and 100s of Cores – Becoming a Reality10s and 100s of Cores – Becoming a Reality

CoreCacheCore

Cache50%50%50%50%

65nm, 4 Cores1V, 3GHz10mm die, 5mm each coreCore Logic: 6MT, Cache: 44MTTotal transistors: 200M

10mm 10mm45nm

8 Cores, 1V, 3GHz3.5mm each coreTotal: 400MT

10mm32nm

16 Cores, 1V, 3GHz2.5mm each coreTotal: 800MT

10mm22nm

32 Cores, 1V, 3GHz1.8mm each coreTotal: 1.6BT

10mm16nm

64 Cores, 1V, 3GHz1.3mm each coreTotal: 3.2BTNote: the above pictures don’t represent any current or future Intel Note: the above pictures don’t represent any current or future Intel

productsproducts

5

Where Are We Heading with Many Core?Where Are We Heading with Many Core?

Pentium® II ArchitecturePentium® II Architecture

Pentium® 4 ArchitecturePentium® 4 Architecture

Pentium® ArchitecturePentium® Architecture

486486386386

MeromMerom

1.E+061.E+06

1.E+1.E+0707

1.E+081.E+08

1.E+091.E+09

1.E+101.E+10

1.E+111.E+11

1.E+121.E+12

1.E+131.E+13

1.E+141.E+14

1.E+151.E+15

19851985 19901990 19951995 20002000 20052005 20102010

FlopsFlops

Pentium® III ArchitecturePentium® III Architecture

TeraTera

PetaPeta

GigaGiga

Projected Projected Multi/Many Core Multi/Many Core

PerformancePerformance

Source: IntelSource: Intel

Penryn (2H Penryn (2H ’07)’07)

6

SW “joins HW” to lead PerformanceSW “joins HW” to lead Performance

65nm 65nm processprocess

20062006

30nm30nm20n20nmm

45nm 45nm processprocess

20082008

32nm32nmprocessprocess

20102010

15nm15nm

22nm 22nm processprocess

20122012

10nm10nm

Moore’sLawcontinuestransistordensity 2Xevery 24 months

But… SW cannot “just” rely on increasing clock speeds

Performance will come from ParallelismPerformance will come from Parallelism

something new,a paradigm shift

Biggest sea of change for software developers

since the OOO(Out Of Order Machine)- Herb Sutter, Microsoft

7

Think ParallelThink Parallel

something new,a paradigm shift

Developers need to“Think Parallel (or perish)”

- James Reinders, Intel

We have achievedgeneral awareness.

Sequential applications do not result in continued performance improvement on future multi-core and many-core platforms.

Developers have much to learn! Thinking Parallel

Software shipping in 2007have Quad-core processors available to utilize.What is the useful economic life for SW in this new HW reality?

Could be run 16 core processors* in 2010 –is it ready today for a 3 year lifespan?

*assumes doubling of cores every 2 years, start with 4 cores in 2006

8

processor cores

We have a future ahead with whereWe have a future ahead with where

Processors have more and more cores.Processors have more and more cores.

CHALLENGE:CHALLENGE:

UNLOCKING THISUNLOCKING THIS

TREMENDOUSTREMENDOUS

POWER USINGPOWER USING

SOFTWARESOFTWARE

Think ParallelThink Parallel

9

processor cores

software with very limited concurrency

software with very limited concurrency

Aside from servers,Aside from servers,concurrency is mostlyconcurrency is mostlyoutside applications today.outside applications today.

Multiple tasks. Environment.Multiple tasks. Environment.

Limited concurrency.Limited concurrency.

Think ParallelThink Parallel

10

software with very limited concurrency

processor cores

EmergingEmerging

Step are beingStep are beingmade made todaytoday to put concurrency in to put concurrency inmore software development.more software development.

Learning to THINK PARALLEL,Learning to THINK PARALLEL,

New methods to use,New methods to use,

New methods to explore.New methods to explore.

Think ParallelThink Parallel

11

software with very limited concurrency

processor cores

EmergingEmerging

WE KNOWWE KNOW

SOFTWARE DEVELOPERSSOFTWARE DEVELOPERS

NEED TO LEARNNEED TO LEARN

THIS NEW WORLDTHIS NEW WORLD

IN ORDER TO COMPETEIN ORDER TO COMPETE

Think ParallelThink Parallel

12

software with very limited concurrency

processor cores

EmergingRese

arch

Research

We already see a future with evenWe already see a future with evenmore cores. Research today is critical tomore cores. Research today is critical toleading us into the future.leading us into the future.

Think ParallelThink Parallel

13

What advice we haveWhat advice we haveCS Educators

Teach students to think parallel.

Help them answer these questions:1. How will it scale to N

processors?2. How are new correctness

issues addressed?3. How maintainable is the

solution we create?

Future developers1. Learn to THINK PARALLEL.2. Approach all problems looking

for parallelism (not step-by-step sequential methods)

3. Use tools designed for concurrent programming.

4. Program to tasks (chores), never threads. Do not use raw threading packages.

5. For debugability, create programs which can be debugged in a single-threaded mode.

6. Minimize explicit synchronization.

7. Use scalable memory allocation.

8. Plan to scale workloads.

14

What we are doing to helpWhat we are doing to helpHelp mainstream programmers to quickly develop quality code

ResearchResearchTomorrow’sTomorrow’sTechniquesTechniques

TransactionalTransactionalMemoryMemory

Main threadMain thread Speculative Speculative threadthread

SpawnSpawn

CommitCommitspeculative speculative

resultsresults

CC

BBAA

Main threadMain thread Speculative Speculative threadthread

SpawnSpawn

CommitCommitspeculative speculative

resultsresults

CCCC

BBBBAAAASpeculativeSpeculativeMulti-Multi-threadingthreading

EducateEducateTomorrow’sTomorrow’s

ExpertsExperts

• 2006 - Helped 45 universities add2006 - Helped 45 universities addparallel programming coursesparallel programming courses

• 2007 400+ univ. 25000 students2007 400+ univ. 25000 students• 2008 reaching out to 1000+ univ2008 reaching out to 1000+ univ

Intel Intel Academic Academic CommunityCommunity

ACCELERATE TRANSITIONTO PARALLEL PROGRAMMING

ProvideProvideToolsToolsTodayToday

Architect, Architect, Thread, Thread, Debug & Debug & TuneTune

http://www.intel.com/software/products

Intel® Academic CommunityGet Involved!

• Connect with peers & technologists

• Access new technology curriculum

• Lead global discussion forums

• Share your knowledge!– Join the discussions in the

forums– Give your opinions in the blogs– Add your content to the Wiki– Comment on what you are

viewing

http://academiccommunity.intel.com

Join the Intel® Academic Community Forums!

Share your knowledge

Connect with peers

Meet the technologists

Join the Intel® Academic Community Forums!

Share your knowledge

Connect with peers

Meet the technologists

Do you have an opinion?How is parallel programming becoming easier?

Many problems can be parallelized as both task and domain decomposition. What types of problems can be parallelized by only one of these methods, but not another?

Want to know more about potential parallelism?Read “Recognizing Potential Parallelism” for the technologist’s point of view. (Available online at the Intel® Academic Community.)

Do you have an opinion?How is parallel programming becoming easier?

Many problems can be parallelized as both task and domain decomposition. What types of problems can be parallelized by only one of these methods, but not another?

Want to know more about potential parallelism?Read “Recognizing Potential Parallelism” for the technologist’s point of view. (Available online at the Intel® Academic Community.)

http://academiccommunity.intel.com

University ProgramSupporting Your Curriculum Needs

• New technology curriculums developed specifically for the needs of the academic community

• Access to course downloads

• Obtain the latest Intel® Software Development Products for your classroom

• Become a member today!http://academiccommunity.intel.com

Intel Academic Community – Academic Community Collaborating Worldwide

In 51 countries around the worldIn 51 countries around the world ,

at more than 460 Universitiesat more than 460 Universities800 professors are800 professors are

teaching more than 25000 new software professionalsteaching more than 25000 new software professionalsMulti-core programmingMulti-core programming

What are the Universities saying?

“The change to multi-core means a re-emphasis on concurrency and parallelism… It's an interesting challenge for us to educate students in that direction. Whether they build gaming applications, vision applications, robotics applications or traditional applications in the high performance domain, they have to always think parallel. That renewed emphasis in understanding parallelism is important to impart to our students.” Professor Karsten Schwan, College of Computing, Georgia Institute of Technology

Intel University Program provides:

Recipe for SuccessRecipe for Success

Courseware to drop into existing courses

Continual technology

updates

Free Intel® Software

Development Tools licenses for the classroom

Wiki and blog for collaboration,

Forums for specific questions

Courseware to drop into existing courses

Continual technology

updates

Free Intel® Software

Development Tools licenses for the classroom

Wiki and blog for collaboration,

Forums for specific questions

Implementing a parallel curriculum

• CERCS team consists of CS and ECE faculty, awarded equipment and grant funding for multi-core curriculum development:

Key Idea: “… to upgrade the core curriculum at the College of Computing (CoC) and School of Electrical and Computer Engineering (ECE) at Georgia Tech to better prepare future generations of hardware and software practitioners … to harness the potential of current and future multi-core platforms.”

• PIs: AdaGavrilovska, Hsien-Hsin-Lee, Karsten Schwan, SudhaYalamanchili, Matthew Wolf

• Bring concurrency and parallelism back into CS/ CompEeducation by coordinated updates to an entire ecosystem of courses

• Engage broad set of faculty beyond PIs

Georgia Tech Multi-core Background

Summary

• Visit Intel at booth 317

academiccommunity.intel.com

Register for the Intel Academic community

Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.

EUR: Tech U Munich, ETH Zurich, U Politecnica de Catalunya, RWTH Aachen, U Karlsruhe, Budapest Polytechnic Institute

Bev BachmayerBev Bachmayer

Intel University Program Manager Intel University Program Manager Software and Solutions GroupSoftware and Solutions Group

March 14, 2007March 14, 2007

Parallelism