BESIII CGEM-IT Readout ASICCharacterisation and Production Status

Manuel Da Rocha Roloon behalf of the TIGER Test and Design Team

INFN Torino

IHEP, 15 September 2017

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 1 / 8

Update on test activities

Ongoing tests with planar and cylindrical GEMThe induction gap of the planar chamber is 5mm as the final configuration of the CGEM as opposedto 3mm of the CGEM prototype

Collecting data with Fe55, Sr90 and cosmic rays, working on cluster algorithms

Minimum threshold for stable operation around 3-4fC with CGEM, 2,5-3fC with planarchamber

higher than expected electronic noise on TIGERv0sensitivity to grounding scheme and interference noisetemperature sensitivity (corrected in TIGERv1) causes baseline shifts during operation

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 2 / 8

Plan of activities for the Engineering Run

Design Team: Fabio Cossio, Weishuai Cheng, Junying Chai, Angelo Rivetti, Manuel Rolo

Preparation of a database with 3 design splits:TIGERv0 - as per MPW siliconTIGERv1 - engineered version based on CSA, new shaperTIGERv2 - backup solution with RGC amplifier, new shaper

Tapeout preparation with IMEC began end of April

Organisation of a shared reticle with design partners

each partner pays for an allocated area of the reticlevery important reduction of costs, common masksettechnical and administrative organisation handled by INFN Torino and IMEC

An engineering lot of 12 wafers is started with the maskset

all good (quality and electrical pass) wafers are delivered - typically between 10 and 12wafers, yielding up to:

TIGERv0: 936 untested chipsTIGERv1: 1968 untested chipsTIGERv2: 984 untested chips

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 3 / 8

Engineering Run Designs - summary of revisions

TIGERv1 - engineered version based on CSA, new shaper

Baseline drift correctedT-branch drift and temperature dependence well annotated by simulations, root causes identifiedre-design of Shaper Core Amplifier to cope with larger loop currentsre-design of Baseline Holder to increase robustness to PVTre-design of Front-End bias cells (chip periphery)

Decreased resistivity of VREF line used by TDC, can cause bin variations on multi-channeltriggering

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 4 / 8

Engineering Run Designs - summary of revisions

TIGERv2 - backup solution with RGC amplifier, new shaper

Current-mode Input Stage based on a regulated common-gate amplifiercould prove less susceptible to common-mode noisehigher electronic noise, still below 4k ENC and 3 ns r.m.s. for time stamp (Qin = 3 fC)lower input impedance

per-channel 3-bit DAC for gain adjustment

more flexible parametrisation of front-end operation (2x 6-bit DACs, 1x 5-bit DAC onperiphery)

Applies design revisions from TIGERv1

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 5 / 8

Status of Tapeout Procedure

Design preparation:TIGERv0 - design closed, approved by IMEC July 17thTIGERv1 - design closed, approved by IMEC July 20thTIGERv2 - design closed, approved by IMEC July 26th

Dry-run (mask design preparation) issued end of August

JDV Ready and approved, mask production requested

Engineering lot lead time from final GDS-in to wafer delivery: Schedule to be confirmedafter mask approval and wafer start.

BEOL Operations (grinding, dicing, shipment) organised, quotations and payments ready

ECCN1 clearance - verified by IMEC’s Export Team

1Export Control Classification Number

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 6 / 8

Preparation for On-Detector Electronics Production

Pre-production of FE1-L1 and FE2-L1L2pass electrical test

Test Firmware for final boards ready,started testing with TIGERv0

Issue production of FEBs for L1 and L2next week

Preparation of FW/SW for wafer probestation planned (2 weeks)

Start procedure for probecard production (1week schematic preparation, 7 weeksproduction)

Prepare naked chip probing with TIGERv0(end of November)

2 experts, 2 bonding machines assignedfull-time for assembly of 100 FEBs -starting December 2017

Expected chip yield above 90%:↪→ start assembly operations with untested

chips, re-work up to 20% of faulty boards

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 7 / 8

darochar@to.infn.it

The BESIIICGEM project has been funded by European Commission within the call H2020-MSCA-RISE-2014.

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 8 / 8

Backup Slides

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 9

Overview of the channel

Time-based readoutsingle or double thresholdtime stamp on rising/falling edge (sub-50 ps binning quad-buffered TDC)charge measurement with Time-over-Threshold

Time and amplitude samplingtime stamp on rising edge (sub-50 ps binning quad-buffered TDC)Sample-and-Hold circuit for peak amplitude samplingslow shaper output voltage is sampled and digitised with a 10-bit Wilkinson ADC

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 10

TIGER: ASIC Prototype for the CGEM Readout

64 channels: VFE, signal conditioning,TDC/ADC, local controller

on-chip bias and power management

on-chip calibration circuitry

fully digital output, LVDS IO

4 TX SDR/DDR links, 8B/10B encoding

SPI configuration link

power below 10 mW per channel

nominal 160 MHz system clock

sustained rate per channel: above 100 kHz

25 mm2 CMOS

tapeout of first silicon: MPW May 2016

Manuel Da Rocha Rolo (INFN Torino) BESIII CGEM-IT: TIGER status IHEP, 15 September 2017 11