EXPERIMENT 7

(A) NOR GATE CIRCUIT

Objective

To understand how to construct other combinational logic gates using NOR gates.

Procedures:

1) U1a as shown in Figure 7.1 will be used to construct a NOT gate.

2) Connect inputs A, B to Data Switches SW 0, SW 1 and output F1 to logic Indicator L1. Set

SW 0 to “0”, observe states of F1 at SW 1=”0” and SW 1=”0. Does the circuit act as a NOT

gate? (as in Figure 7.2)

3) Insert a connection clip between A and B. Connect A to SW 0 and F1 to L1. What is the state

of F1 when SW 0 = “0” and SW 0 = “1”? Does the circuit act as a NOT gate? Use U1a and U1c

to construct a BUFFER shown in Figure 7.3 (a). Insert connection-clips jumper between A-B;

F1-A1; A1-B1. Connect input A to SW 0 and output F3 to L1. What is the state of F3 when SW

0 = 0 and SW 0 = 1?

5) Use U1a and U1c to construct an OR gate shown in Figure 7.3 (b). Insert connection-clips

jumper between F1-A1 and A1-B1. Connect input A to SW 0, B to SW 1; and output F3 to L1.

Follow the input sequences shown below and record the output states in Table 7-1.

6) Insert connection clips according to the Figure 7.4 below. The circuit will act as

an AND gate.

7) Connect A to SW 0; D to SW 1; F1 to A1; F2 to B1; F3 to L1. Follow the input sequences

given below; record the output states in Table 7-2.

(B) NAND GATE CIRCUIT

Objective

To understand how to construct various combinational logic gates using NAND gates.

Procedures:

1) Insert connection clips according to Figure 7.5 using U2c and U2d to construct the NOT gate

shown in Figure 7-6 (a).

Figure 7.6

(A) Connect input A to Data Switch SW 1 and output F2 to A2 and Logic Indicator L1; connect

B1 to Vcc “1” (Vcc = 1 is the output of 12 V DC power supply). Observe the output states.

When SW 1=0”, F2 = _____________

When SW 1=1”, F2 = _____________

Does the circuit act as NOT gate?

(B) Connect input A 1 to Vcc 1and remove the connection clip between A and A1 to create the

NOT gate shown in Figure 7.6 (b). Other connection remain the same. Observe the output states.

When SW1=0”, F2=_____________

When SW1=1”, F2=_____________

Does the circuit act as NOT gate?

Remove connection clips and insert them again according to Figure 7.7 (a) to construct the

AND gate shown in Figure 7.7 (b). Connect A to SW 1, A1 to SW 2 and F4 to L1. Follow

the input sequences given below and record the outputs in Table 7-3. Does the circuit act as

an AND gate?

(B)

2) Insert connection clips according to Figure 7.8 (a) to construct the circuit of Figure 7.8 (b).

Connect A to A1 and SW 1; F2 to A2; D to B1 and SW 2; F3 to B2; F to L1. Follow the input

sequences in Table 7-4 and record the outputs.

Does the circuit act as an OR gate?

(C) XOR GATE CIRCUIT

Objective

To understand the characteristics of XOR gates.

Procedures:

A. Constructing XOR gate with NAND gate (Module KL-33002 block b)

1) Insert connection clips according to Figure 7.9 (a) to construct the circuit in Figure 7.9 (b).

Connect inputs A to SW 1, D to SW 2; outputs F1 to L1, F2 to L2; F3 to L3 and F4 to L4.

2) Follow the input sequences for A and D in Table 7-5 and record the outputs.

3) Determine the Boolean expression for F1, F2, F3, F4.

B. Constructing XOR Gate with Basic Gate (Module KL-33002 block c)

1) Insert connection clips according to Figure 7.10 (a) to construct the equivalent circuit of

Figure 7.10 (b).

2)

Connect inputs A to SW 1 and B to SW 2; outputs F1, F2, F3 to L1, L2, L3.

3) Follow the input sequences for A and B in Table 7-6 and record the outputs.

(D) AND-OR-INVERTER (A-O-I) GATE CIRCUIT

Objective

To understand the basic principled of combined logic gates.

Procedures:

1) Use U3a, U3b, U3c and U4c on block c of Module KL-33002, shown in Figure 7.11 (a) to

construct the A-O-I gate of Figure 7.11 (b). Figure 7.11 (c) is the equivalent A-O-I circuit which

uses U3a, U3b, U3c used as the OR gate.

2) Connect inputs A, A1, B, B1 to Data Switches SW 0, SW 1, SW 2, SW 3 respectively.

Connect outputs F3, F4 to Logic Indicators L1 and L2.

3) Set B and B1 = 0, follow the input sequences for A and A1 in Table 7-7 and record the

outputs. Does F3 act as an AND gate between A and A1?

4) When B B1, does F3 act as an AND gate between A and A1?

5) When A = A1 = 0, follow the input sequences for B and B1 in Table 7-8 and record the

outputs. Does F3 act as an AND gate between B and B1?

6) When A A1, does F3 act as an AND gate between B and B1?

7) Does F3 equal to (A ∙ A1) + (B ∙ B1)?

RESULTS :A. NOR GATE CIRCUIT

SW1 (B) SW 0 (A) F

0 0 0

0 1 1

1 0 1

1 1 1

Table 7-1

SW1 (D) SW 0 (A) F3

0 0 0

0 1 0

1 0 0

1 1 1

Table 7-2

B. NAND GATE CIRCUIT1.

a) When SW 1 = “0”, F2 = 1

When SW 1 = “1”, F2 = 0

The circuit act as NOR gate.

b) When SW 1 = “0”, F2 = 1

When SW 1 = “0”, F2 = 1

The circuit does not act as NOT gate.

c) The circuit act as an AND gate.

SW2 (A1) SW 1 (A) F4

0 0 0

0 1 0

1 0 0

1 1 1

Table 7-3

2. The circuit act as an OR gate.

SW2 (A1) SW 1 (A) F4

0 0 0

0 1 1

1 0 1

1 1 1

Table 7-4

C. XOR GATE CIRCUIT

a) Constructing XOR Gate with NAND Gate.

INPUT OUTPUT

D A F1 F2 F3 F4

0 0 1 1 1 0

0 1 0 0 1 1

1 0 1 1 0 1

1 1 0 0 0 1

Boolean expression :

F1 = DA + DA

F2 = DA + DA

F3 = DA + DA

F4 = DA + DA + DA

b) Constructing XOR Gate with Basic Gate.

INPUT OUTPUT

SW 2 (B) SW 1 (A) F1 F2 F3

0 0 1 1 0

0 1 0 1 1

1 0 1 0 1

1 1 1 1 0Table 7-6

D. AND-OR-INVERTER (A-O-I) GATE CIRCUIT

3. Yes, F3 act as an AND gate between A and A1.

A1 A F3 F4

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0 Table 7-7

4. Yes, F3 act as an AND gate between B and B1.

B1 B F3 F4

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0 Table 7-8

5. Yes, F3 equal to (A . A1) + (B . B1)

QUESTION.

DISCUSSION:

A logic gate is an idealized or physical device implementing a Boolean function, that is, it

performs a logical operation on one or more logic inputs and produces a single logic output.

Gates are identified by their function: NOT, AND, NAND, OR, NOR, EX-OR and EX-NOR.

Capital letters are normally used to make it clear that the term refers to a logic gate. All other

types of Boolean logic gates such as AND, OR, NOT, XOR, XNOR can be created from a

suitable network of NAND gates. Similarly all gates can be created from a network of NOR

gates. Historically, NAND gates were easier to construct from MOS technology and thus NAND

gates served as the first pillar of Boolean logic in electronic computation

The output Q is true when the input A is NOT true, the output is the inverse of the input Q =

NOT A. A NOT gate can only have one input. A NOT gate is also called an inverter.

Input A Output Q

0 1

1 0

Symbol NOT gate Truth Table

The output Q is true if input A AND input B are both true Q = A AND B. An AND gate can

have two or more inputs, its output is true if all inputs are true.

Input A Input B Output Q

0 0 0

0 1 0

1 0 0

1 1 1

Symbol AND gate Truth Table

This is an AND gate with the output inverted, as shown by the 'o' on the output. The output is

true if input A AND input B are NOT both true: Q = NOT (A AND B). A NAND gate can have

two or more inputs, its output is true if NOT all inputs are true.

Input A Input B Output Q

0 0 1

0 1 1

1 0 1

1 1 0

Symbol NAND gate Truth Table

The output Q is true if input A OR input B is true (or both of them are true) Q = A OR B. An OR

gate can have two or more inputs, its output is true if at least one input is true.

Input A Input B Output Q

0 0 0

0 1 1

1 0 1

1 1 1

Symbol OR gate Truth Table

This is an OR gate with the output inverted, as shown by the 'o' on the output. The output Q is

true if NOT inputs A OR B are true Q = NOT (A OR B). A NOR gate can have two or more

inputs, its output is true if no inputs are true.

Input A Input B Output Q

0 0 1

0 1 0

1 0 0

1 1 0

Symbol NOR gate Truth Table

The output Q is true if either input A is true OR input B is true, but not when both of them are

true Q = (A AND NOT B) or (B AND NOT A). This is like an OR gate but excluding both

inputs being true. The output is true if inputs A and B are different. XOR gates can only have 2

inputs.

Input A Input B Output Q

0 0 0

0 1 1

1 0 1

1 1 0

Symbol XOR gate Truth Table

This is an XOR gate with the output inverted, as shown by the 'o' on the output. The output Q is

true if inputs A and B are the same (both true or both false) Q = (A AND B) or (NOT A AND

NOT B). XNOR gates can only have 2 inputs.

Input A Input B Output Q

0 0 1

0 1 0

1 0 0

1 1 1

Symbol XNOR gate Truth Table

CONCLUSION:

NOT gate can be used to construct any other combinational logic gates.it can combine

with and gate and or gate to produce only one gate which are NOR and NAND. So we

only has a gate NAND and NOR. If we not combine it will has 2 gate to construct circuit

which are NOT And OR or NOT and AND.

This combination gates can give a new gate. It also can simply to reduce the time delay,

reduce gate use and reduce the cost to built it.

REFERENCES:

1. http://www.rexfisher.com/CoE243/CoE243_Lect2.pdf

2. http://www.kpsec.freeuk.com/gates.htm

3. http://en.wikipedia.org/wiki/Logic_gate