Behavior Model

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OverviewOverview

VHDL ProcessesVHDL Processes If-Then-Else and CASE statementsIf-Then-Else and CASE statements Flip-Flop description using VHDLFlip-Flop description using VHDL Sequential circuit description (state Sequential circuit description (state

tables and diagrams) using VHDLtables and diagrams) using VHDL Process synchronizationProcess synchronization

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VHDL ProcessVHDL Process A group of VHDL statements that are A group of VHDL statements that are

“executed” when one signal in a specified “executed” when one signal in a specified group changes.group changes.

Many processes can be executed Many processes can be executed concurrently.concurrently.

““Body” of process implements a Body” of process implements a sequentialsequential program, i.e. program, i.e. signalsignal values are updated only values are updated only when the process completes.when the process completes.

Can also use Can also use variablesvariables, whose value is , whose value is updated immediately.updated immediately.

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VHDL Architecture VHDL Architecture StructureStructure

architecture name_arch of name is

begin

end name_arch;

Signal assignments

Concurrent statements


Process 1

Process 2


Processes contain sequential

statements, but execute

concurrently within the

architecture body

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VHDL Process SyntaxVHDL Process Syntax

P1: process (<sensitivity list>)<variable declarations>begin <sequential statements>end process P1;

Optional process label

Within a process:

Variables are assigned using :=

and are updated immediately.

Signals are assigned using <=

and are updated at the end of

the process.

Signals and/or Variables

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Signals Vs Variables in a Signals Vs Variables in a ProcessProcess

Let A, B, and C be integer data types withLet A, B, and C be integer data types with A=1, B=5, and C=10. A=1, B=5, and C=10.

A, B, C: A, B, C: signalssignals A, B, C: A, B, C: variablesvariables

begin processbegin process begin processbegin process…… ……B <= A;B <= A; B := A;B := A;C <= B;C <= B; C := B;C := B;…… … … end process;end process; end process;end process;

B = 1 and C = 5B = 1 and C = 5 B = 1 and C = 1B = 1 and C = 1( uses original value ( uses original value ( uses new value( uses new value B (=5) when B (=5) when of B (=1) when of B (=1) when computing C ) computing C ) computing C ) computing C )

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Copyright 1995-1999 SCRA

Methodology

ReinventingElectronic

DesignArchitecture Infrastructure

DARPA Tri-Service

RASSPVHDL Sequential Statements

Assignments executed sequentially in processes

Sequential statements {Signal, variable} assignments

Flow control

IF <condition> THEN <statements> [ELSIF <statements] [ELSE <statements>] END IF;

FOR <range> LOOP <statements> END LOOP;

WHILE <condition> LOOP <statements> END LOOP;

CASE <condition> IS WHEN <value> => <statements>

{WHEN <value> => <statements>}

[WHEN others => <statements>]

END CASE;

WAIT [ON <signal>] [UNTIL <expression>] [FOR <time>] ;

ASSERT <condition> [REPORT <string>] [SEVERITY <level>] ;

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Combinational circuit Combinational circuit description using a VHDL description using a VHDL

processprocess

Remember the n-line 4 x 1 Remember the n-line 4 x 1 multiplexer:multiplexer:

a(n-1:0)

b(n-1 :0)y(n-1 :0)

sel(1:0)

8-line4 x 1MUXc(n-1 :0)

d(n-1 :0)

Sel y“00” a“01” b“10” c“11” d

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architecture mux4g_arch of mux4g isbegin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process;end mux4g_arch; Must include ALL posibilities

in case statement

Sel y

“00” a

“01” b

“10” c

“11” d

An n-line 4 x 1 multiplexer:An n-line 4 x 1 multiplexer:using a CASE statementusing a CASE statement

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If-Then-Else statementIf-Then-Else statement

[ if_label:]if boolean_expression then { sequential_statement; }{ elsif boolean_expression then { sequential_statement; } }[ else { sequential_statement; } ]end if [ if_label ];

Notation:Notation:[ ] -- optional{ } -- repeatable

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CASE statementCASE statement

[ case_label:]

case expression is

{ when choices => { sequential statement; }}

end case [case_label];

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Methodology



DARPA Tri-Service

RASSPThe Wait Statement

The wait statement causes the suspension of a process statement or a procedure

wait [sensitivity_clause] [condition_clause] [timeout_clause ] ;

sensitivity_clause ::= ON signal_name { , signal_name }

WAIT ON clock;

condition_clause ::= UNTIL boolean_expression

WAIT UNTIL clock = ‘1’;

timeout_clause ::= FOR time_expression

WAIT FOR 150 ns;

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Methodology



DARPA Tri-Service

RASSPEquivalent Processes

“Sensitivity List” vs “wait on”

Summation: PROCESS( A, B, Cin)BEGIN

Sum <= A XOR B XOR Cin;END PROCESS Summation;

Summation: PROCESS( A, B, Cin)BEGIN

Sum <= A XOR B XOR Cin;END PROCESS Summation;

Summation: PROCESSBEGIN

Sum <= A XOR B XOR Cin;WAIT ON A, B, Cin;

END PROCESS Summation;

Summation: PROCESSBEGIN

Sum <= A XOR B XOR Cin;WAIT ON A, B, Cin;

END PROCESS Summation;

=

if you put a sensitivity list in a process, you can’t have a wait statement!

if you put a wait statement in a process, you can’t have a sensitivity list!

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Flip-Flop description using Flip-Flop description using VHDL:VHDL:

Positive Edge-Triggered D-FF with Positive Edge-Triggered D-FF with ResetReset Entity Declaration:Entity Declaration:

-- Positive Edge-Triggered D Flip-Flop with Reset:-- Positive Edge-Triggered D Flip-Flop with Reset:-- VHDL Process Description -- VHDL Process Description librarylibrary ieee; ieee; useuse ieee.std_logic_1164. ieee.std_logic_1164.allall; ; entityentity dff dff isis

portport(CLK, RESET, D: (CLK, RESET, D: inin std_logic; std_logic; Q, Q_n: Q, Q_n: outout std_logic); std_logic); endend dff; dff; dffD

CLK

RESET Q

Q_n

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Flip-Flop description using Flip-Flop description using VHDL:VHDL:

Positive Edge-Triggered D-FF with Positive Edge-Triggered D-FF with ResetReset Architecture:Architecture:

architecturearchitecture pet_pr pet_pr ofof dff dff isis-- Implements positive edge-triggered bit state storage-- Implements positive edge-triggered bit state storage-- with asynchronous reset.-- with asynchronous reset.signalsignal state: std_logic; state: std_logic;beginbegin Q <= state;Q <= state; Q_n <= not state;Q_n <= not state; processprocess (CLK, RESET) (CLK, RESET) beginbegin ifif (RESET = '1') (RESET = '1') thenthen state <= '0';state <= '0'; elseelse ifif (CLK'event and CLK = '1') (CLK'event and CLK = '1') thenthen state <= D;state <= D; end if;end if; end if;end if; end process;end process;endend;;

dffD

CLK

RESET Q

Q_n

Q(t+1) = D(t).RESET

Specifies FF triggering: positive edge-trigger

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Methodology



DARPA Tri-Service

RASSPInertial vs Transport Delays

AB

C

ENTITY nand2 ISPORT( A, B : IN BIT; C : OUT

BIT);END nand2;

ARCHITECTURE behavior OF nand2 ISBEGIN

C <= NOT(A AND B) AFTER 25 ns;END behavior;

ENTITY nand2 ISPORT( A, B : IN BIT; C : OUT

BIT);END nand2;


C <= NOT(A AND B) AFTER 25 ns;END behavior;

ENTITY nand2 ISPORT( A, B : IN BIT; C : OUT BIT);

END nand2;


C <= TRANSPORT NOT(A AND B)AFTER 25 ns;

END behavior;

ENTITY nand2 ISPORT( A, B : IN BIT; C : OUT BIT);

END nand2;


C <= TRANSPORT NOT(A AND B)AFTER 25 ns;

END behavior;Inertial Timing

Transport Timing

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INERTIAL DELAY MODELINERTIAL DELAY MODEL THIS DELAY OFTEN FOUND IN “SWITHCHING CIRCUIT”

*INPUTS VALUE MUST BE STABLE FOR A SPECIFIED PULSE REJECTION LIMIT DURATION BEFORE THE VALUE IS ALLOWED TO PROPAGATE TO THE OUTPUT .

*IN ADDITION, THE VALUE APPEARS AT THE OUTPUTAFTER THE SPECIFIED INERTIAL DELAY.

*IF THE INPUT IS NO STABLE FOR THE SPECIFIED LIMIT,NO OUTPUT CHANGE OCCURES.

*WHEN USED WITH SIGNAL ASSIGNMENTS, THE INPUT VALUE IS REPRESENTED BY THE VALUE OF EXPRESSION ON THE RIGHT HAND SIDE AND THE OUTPUT IS REPRESENTED BY THE TARGET SIGNAL.

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TRANSPORT DELAY MODELTRANSPORT DELAY MODEL

THE DELAYS IN HARDWARE THAT DO NOT

EXHIBIT ANY INERTIAL DELAY.

*THIS DELAY REPRESENTS PURE PROPAGATION DELAY, THAT IS ANY CHANGES ON AN INPUTARE TRANSPORTED TO THE OUTPUT, NO MATTER HOW

SMALL, AFTER THE SPECIFIED DELAY.

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Apr 8, 2023

MKM - 20Copyright 1995-1999 SCRA

Methodology



DARPA Tri-Service

RASSPTestbenches

Testbench is the system’s top level component Its entity declaration does not contain any PORT signals

It instantiates all the necessary components that comprise the system

Testbenches may serve three additional useful purposes:

May generate stimulus for simulation:

Behavioral descriptions can be used to generate input vectors

May apply stimulus to the entity under test

Locally declared signals can be connected to PORTS of components in the system

May compare output responses with expected values

Behavioral descriptions can be used to compare model outputs to expected responses

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EXAMPLE OF TEST BENCHEXAMPLE OF TEST BENCH

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FINITE STATE MACHINESFINITE STATE MACHINES

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Definition of a State Definition of a State MachineMachine

All programmable logic designs can All programmable logic designs can be specified in Boolean form. be specified in Boolean form. However some designs are easier to However some designs are easier to conceptualize and implement using conceptualize and implement using non-Boolean models. The State non-Boolean models. The State Machine model is one such model. Machine model is one such model.

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Definition of a State Definition of a State MachineMachine

A state machine represents a system A state machine represents a system as a set of states, the transitions as a set of states, the transitions between them, along with the between them, along with the associated inputs and outputs.associated inputs and outputs.

So, a state machine is a particular So, a state machine is a particular conceptualization of a particular conceptualization of a particular sequential circuit. State machines can sequential circuit. State machines can be used for many other things beyond be used for many other things beyond logic design and computer architecture.logic design and computer architecture.

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Finite State MachinesFinite State Machines

Any Circuit with Memory Is a Finite State Any Circuit with Memory Is a Finite State MachineMachine Even computers can be viewed as huge FSMsEven computers can be viewed as huge FSMs

Design of FSMs InvolvesDesign of FSMs Involves Defining statesDefining states Defining transitions between statesDefining transitions between states Optimization / minimizationOptimization / minimization

Above Approach Is Practical for Small Above Approach Is Practical for Small FSMs OnlyFSMs Only

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State Machines: Definition State Machines: Definition of Termsof Terms

State DiagramState DiagramIllustrates the form and Illustrates the form and function of a state machine. function of a state machine. Usually drawn as a bubble-Usually drawn as a bubble-and-arrow diagram.and-arrow diagram.

StateStateA uniquely identifiable set of A uniquely identifiable set of values measured at various values measured at various points in a digital system.points in a digital system.

Next StateNext StateThe state to which the state The state to which the state machine makes the next machine makes the next transition, determined by the transition, determined by the inputs present when the inputs present when the device is clocked.device is clocked.

BranchBranchA change from present A change from present state to next state.state to next state.

Mealy MachineMealy MachineA state machine that A state machine that determines its outputs determines its outputs from the present state from the present state and from the inputs.and from the inputs.

Moore MachineMoore MachineA state machine that A state machine that determines its outputs determines its outputs from the present state from the present state only.only.

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Present State and Next Present State and Next StateState

On a well-drawn state diagram, all possible transitions will be On a well-drawn state diagram, all possible transitions will be visible, including loops back to the same state. From this diagram visible, including loops back to the same state. From this diagram it can be deduced that if the present state is State 5, then the it can be deduced that if the present state is State 5, then the previous state was either State 4 or 5 and the next state must be previous state was either State 4 or 5 and the next state must be either 5, 6, or 7.either 5, 6, or 7.

State 6 State 7

State 5

State 4 For any given state, there is a finite number of possible next states. On each clock cycle, the state machine branches to the next state. One of the possible next states becomes the new present state, depending on the inputs present on the clock cycle.

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Moore and Mealy MachinesMoore and Mealy Machines Both these machine types follow the basic Both these machine types follow the basic

characteristics of state machines, but differ in the characteristics of state machines, but differ in the way that outputs are produced.way that outputs are produced.

Moore MachineMoore Machine:: Outputs are independent of the inputs, ie outputs Outputs are independent of the inputs, ie outputs

are effectively produced from within the state of are effectively produced from within the state of the state machine.the state machine.

Mealy MachineMealy Machine:: Outputs can be determined by the present state Outputs can be determined by the present state

alone, or by the present state and the present alone, or by the present state and the present inputs, ie outputs are produced as the machine inputs, ie outputs are produced as the machine makes a transition from one state to another.makes a transition from one state to another.

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Machine ModelsMachine ModelsInputs

CombinatorialLogic to

Determine State

Present StateRegister Bank


DetermineOutput Based on: Present State

Output

Moore Machine

Inputs


Determine State

Present StateRegister Bank


DetermineOutput Based on: Present State Present Inputs

Output

Mealy Machine

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EXAMPLEEXAMPLE

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MEALY MACHINEMEALY MACHINE

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FSM VHDL Design ExampleFSM VHDL Design Example 0110 sequence detector, 0110 sequence detector,

Mealy machine no Mealy machine no pattern overlappingpattern overlapping

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0110 Detector Mealy FSM0110 Detector Mealy FSMNo overlapping No overlapping

library IEEE;library IEEE;

use use IEEE.STD_LOGIC_1164.allIEEE.STD_LOGIC_1164.all;;

entity MEALY0110NV isentity MEALY0110NV is

port (CLK,RST,X : in port (CLK,RST,X : in std_logic;std_logic;

Z : out std_logic);Z : out std_logic);

end entity MEALY0110NV;end entity MEALY0110NV;

architecture NOOV of architecture NOOV of MEALY0110NV isMEALY0110NV is

type STATE_TYPE is type STATE_TYPE is (IDLE,S0,S01,S011);(IDLE,S0,S01,S011);

signal CS,NS: STATE_TYPE;signal CS,NS: STATE_TYPE;

beginbegin

SEQ: process (CLK,RST) isSEQ: process (CLK,RST) is

beginbegin

if (rising_edge(CLK)) thenif (rising_edge(CLK)) then

if (RST=‘1’ ) thenif (RST=‘1’ ) then

CS<=IDLE;CS<=IDLE;

elseelse

CS <= NS;CS <= NS;

end if;end if;

end if;end if;

end process SEQ;end process SEQ;

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0110 Detector Mealy FSM0110 Detector Mealy FSMNo overlapping No overlapping

COM: process (CS,X) isCOM: process (CS,X) is

beginbegin

Z<=‘0’;Z<=‘0’;

case CS iscase CS is

when IDLE =>when IDLE =>

if (X = ‘0') thenif (X = ‘0') then

NS<=S0;NS<=S0;

elseelse

NS<=IDLE;NS<=IDLE;

end if;end if;

when S0 =>when S0 =>


NS<=S0;NS<=S0;

elseelse

NS<=S01;NS<=S01;

end if;end if;

when S01=>when S01=>


NS<=S0;NS<=S0;

elseelse

NS<=S011;NS<=S011;

end if;end if;



NS<=IDLE;NS<=IDLE;

Z<=‘1’;Z<=‘1’;

elseelse

NS<=IDLE;NS<=IDLE;

end if;end if;

end case;end case;

end process COM;end process COM;

end architecture NOOV;end architecture NOOV;

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0110 Detector Moore FSM No overlapping0110 Detector Moore FSM No overlapping

Another VHDL code styleAnother VHDL code style (three processes)(three processes)

library IEEE;library IEEE;

use use IEEE.STD_LOGIC_1164.allIEEE.STD_LOGIC_1164.all;;

entity MOORE0110NV isentity MOORE0110NV is

port (CLK,RST,X : in port (CLK,RST,X : in std_logic;std_logic;

Z : out std_logic);Z : out std_logic);

end entity MOORE0110NV;end entity MOORE0110NV;

architecture NOOV of MOORE0110NV isarchitecture NOOV of MOORE0110NV is

type STATE_TYPE is type STATE_TYPE is (IDLE,S0,S01,S011,S0110);(IDLE,S0,S01,S011,S0110);

signal CS,NS: STATE_TYPE;signal CS,NS: STATE_TYPE;

beginbegin

SEQ:SEQ: process (CLK)process (CLK) is is

beginbegin

if (rising_edge(CLK)) thenif (rising_edge(CLK)) then

if (RST=‘1’ ) thenif (RST=‘1’ ) then

CS<=IDLE;CS<=IDLE;

elseelse

CS <= NS;CS <= NS;

end if;end if;

end if;end if;

end process SEQ;end process SEQ;

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0110 Detector Moore FSM0110 Detector Moore FSMNo overlapping No overlapping

COMCOM: : process (CS,X)process (CS,X) is is

beginbegin


when IDLE =>when IDLE =>


NS<=S0;NS<=S0;

elseelse

NS<=IDLE;NS<=IDLE;

end if;end if;



NS<=S0;NS<=S0;

elseelse

NS<=S01;NS<=S01;

end if;end if;



NS<=S0;NS<=S0;

elseelse

NS<=S011;NS<=S011;

end if;end if;



NS<=S0110;NS<=S0110;

elseelse

NS<=IDLE;NS<=IDLE;

end if;end if;


NS<=IDLE;NS<=IDLE;

end case; end case;

end process COM;end process COM;

No output Z in the COM process

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0110 Detector Moore FSM0110 Detector Moore FSMNo overlapping No overlapping

OUTPUTZOUTPUTZ: : process (CS)process (CS) isis

beginbegin


when IDLE|S0|S01|when IDLE|S0|S01|S011=>S011=>

Z<=‘0’;Z<=‘0’;


Z<=‘1’;Z<=‘1’;

end case;end case;

end process OUTPUTZ;end process OUTPUTZ;

end architecture NOOV; end architecture NOOV;

Z<=‘1’ when CS=S0110 Z<=‘1’ when CS=S0110 elseelse

‘ ‘0’;0’;

end architecture NOOV;end architecture NOOV;

OR

3rd process defines the output function

Documents

Behavior Model