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BECAUSE TESTING MATTERSBECAUSE TESTING MATTERS
Next Generation ICT Testing Challenges
Next Generation ICT Testing Challenges
IEEE BTW 2008 WorkshopSeptember, 2008
Fort Collins, ColoradoPresented by: Alan Albee
Teradyne ICT Product Manager
22 Teradyne Confidential2
Next Generation ICT ChallengesNext Generation ICT Challenges
• Diverse ICT Manufacturing Requirements
– High performance vs “Just-Enough-Test” systems
• Ultra-low voltage technologies
– How to test reliably and safely
• Shrinking package geometries
– How to maintain acceptable fault coverage with Vectorless Test techniques
• High Density Interconnect designs
– How to maintain acceptable fault coverage without physical test access
• Proliferating boundary scan and DFT technologies
– How can ICT best take advantage of these PCB testability features
• Skill levels of test developers and operators
– How do you improve user productivity of test developers and operators
• Increasing test throughput requirements
– How to keep up with increasing Assembly Equipment speeds and eliminate test bottlenecks
• Diverse ICT Manufacturing Requirements
– High performance vs “Just-Enough-Test” systems
• Ultra-low voltage technologies
– How to test reliably and safely
• Shrinking package geometries
– How to maintain acceptable fault coverage with Vectorless Test techniques
• High Density Interconnect designs
– How to maintain acceptable fault coverage without physical test access
• Proliferating boundary scan and DFT technologies
– How can ICT best take advantage of these PCB testability features
• Skill levels of test developers and operators
– How do you improve user productivity of test developers and operators
• Increasing test throughput requirements
– How to keep up with increasing Assembly Equipment speeds and eliminate test bottlenecks
Changing Technologies, Testing Philosophies, and Economic conditions…
44 Teradyne Confidential4
Differing Demands on ICT Testers…Differing Demands on ICT Testers…
• Low margin manufacturers demand low cost
• Untrained operators demand simple and easy to use operation
• Highly skilled test engineers demand powerful programming capabilities
• High reliability product manufacturers demand high fault coverage and safe testing
• High volume manufacturers demand ever higher test throughputs
• Outsourcing business models demand turnkey solutions and equipment compatibility
• Complex PCB Manufacturers demanding high pincount capacity systems
• Different market segments and regions implementing different test philosophies
• Low margin manufacturers demand low cost
• Untrained operators demand simple and easy to use operation
• Highly skilled test engineers demand powerful programming capabilities
• High reliability product manufacturers demand high fault coverage and safe testing
• High volume manufacturers demand ever higher test throughputs
• Outsourcing business models demand turnkey solutions and equipment compatibility
• Complex PCB Manufacturers demanding high pincount capacity systems
• Different market segments and regions implementing different test philosophies
55 Teradyne Confidential5
Historical Bed-Of-Nails Electrical Test AlternativesHistorical Bed-Of-Nails Electrical Test Alternatives
Performance
Fault Coverage
OperationSimple Complex
High
Low
Manufacturing Defect Analyzers
Standard In-Circuit Testers
High Performance ICT
PriceLow High
66 Teradyne Confidential6
Teradyne’s Scalable ICT Product Platform StrategyTeradyne’s Scalable ICT Product Platform Strategy
TestStation LH TestStation TestStation LX
Pin Count
Common Instruments and Options
Common Software Environment
Common Technologies
Pin Capacity
Pure Hybrid
Analog Only
Multiplexed
77 Teradyne Confidential7
Selectable Pin Board OptionsSelectable Pin Board Options
Pin Board Type
Analog Test
Digital Test
Pure Pin High Density
Pin Board
Mix
Real Pin Ratio
Analog 121 Yes, with
Ultra II 1210/128
Ultra II 121 Yes, with
Analog 121128/128
Ultra II 124 Yes, with
Ultra II 128L
32/128
Ultra II 128L Yes, with
Ultra II 12432/256
Ultra II 124L No 64/256
Multiple pin board options to match manufacturer’s pin count, technology, and budget requirements…
88 Teradyne Confidential8
• Clock/Sync/Trigger VLSI test capabilities
– Advanced digital device testing and timing control
• Backdrive measurement and high accuracy features
– Increased accuracy and safety when testing low-voltage parts
• System frequency test module
– Frequency and time event measurements
• Power supplies
– Up to 14 programmable and three fixed user supplies
• Deep serial memory module
– Enhanced performance of FLASH/ISP/BSCAN tests
• Analog functional test module
– Complex analog and mixed signal device testing
• Custom function board
– Vehicle control interface for automotive protocols
– Integration of custom and third-party test application circuitry
• Clock/Sync/Trigger VLSI test capabilities
– Advanced digital device testing and timing control
• Backdrive measurement and high accuracy features
– Increased accuracy and safety when testing low-voltage parts
• System frequency test module
– Frequency and time event measurements
• Power supplies
– Up to 14 programmable and three fixed user supplies
• Deep serial memory module
– Enhanced performance of FLASH/ISP/BSCAN tests
• Analog functional test module
– Complex analog and mixed signal device testing
• Custom function board
– Vehicle control interface for automotive protocols
– Integration of custom and third-party test application circuitry
Scalable Hardware FeaturesScalable Hardware Features
Add these capabilities as needed…
99 Teradyne Confidential9
Scalable ICT Platform GoalScalable ICT Platform Goal
Unpowered Analog
Shorts
RLC
Analog comp values
Vectorless Test
Opens on digital pins and connector pins
Misoriented components
Powered Analog
Amplifiers
Frequency
Analog functional
BSCAN Instrument
BSCAN components
PLD programming
Digital Vectors
Fast detection of open digital pins
Missing / wrong digital components
Faults on mixed BSCAN / conventional nets
Fault Coverage
• Buy only the test capability you need• Grow or reduce fault coverage without changing the tester• No need to change programs and test fixtures• No need to learn different test systems
MDA
MDA + ICT ICT ++
< $100K
1111 Teradyne Confidential11
‘ ‘Low Voltage’ Challenge For ICT...Low Voltage’ Challenge For ICT...
• Multiple voltage levels per IC
• More susceptible to damage from ‘over-voltage’ spikes
• More susceptible to damage from current ‘over-driving’
• I/O logic levels are differentiated by milli-volts
– Logic drivers & sensors must resolve to milli-volts levels
– Voltage instability must not trigger logic transitions even under variable load conditions
• Multiple voltage levels per IC
• More susceptible to damage from ‘over-voltage’ spikes
• More susceptible to damage from current ‘over-driving’
• I/O logic levels are differentiated by milli-volts
– Logic drivers & sensors must resolve to milli-volts levels
– Voltage instability must not trigger logic transitions even under variable load conditions
Source of unstable tests & high false fails
Source of device stress and potential damage
1212 Teradyne Confidential12
Newer Parts Are More Sensitive to Over-Newer Parts Are More Sensitive to Over-Voltage ConditionsVoltage Conditions
Safety Limits for 1.2V AGTL Logic
1.4
1.45
1.5
1.55
1.6
1.65
1.7
1.75
1.8
0 2 4 6 8 10Overvoltage Time (nsec)
Sig
nal V
olta
ge (V
)
5nsec clock
50nsec clock
• Today’s processors
have strict over-
voltage/time
specification
• AGTL signals should
never exceed 1.8V
• Should not exceed
1.5V for >10nsec
• Must ensure voltages
remain in Safe
Operating Region
Source : Intel Corp. Itanium 2 processor datasheet
Overvoltage conditions must be controlled
1313 Teradyne Confidential13
Tim
e to
63%
Fai
lure
(se
c)
2nsec
200nsec
10usec
1msec
Tim
e to
Fai
lure
(se
con
ds)
11 7.3 5.5 4.4 3.6 3.1 2.7 2.4 2.2
Gate OxideVoltage (Volts)
Graph Source : IEEE Transactions on Electron Devices, Vol 51, 08/2004
9V backdrive spike for 40nsec, 16V peak for 10nsec !These spikes can occur without proper isolation
74LVT240A 3.3V.Backdriven high thenTri-stated.
Studies Prove that Over-Voltage Conditions Destroy Studies Prove that Over-Voltage Conditions Destroy or Damage Partsor Damage Parts
Data taken from a study sponsored by the National Science Foundation and the Semiconductor Research Corporation
1414 Teradyne Confidential14
ScreenPrint
ChipShooter
ReflowSolder
Fine PitchPlacement
ICT Functional Test
AOI
Potential Economic Impact of Using ICT not Potential Economic Impact of Using ICT not designed for designed for Low Voltage DevicesLow Voltage Devices
AOI
• Reduced Fault Coverage
– Unable to test components without violating device specifications
• Increased False Failures
– Needless replacement of good devices
– Increased repair and re-test costs
– Possible damage to product during the repair cycle
• Damaged Components
– Catastrophic or latent failures related to gate oxide breakdown, ESD protection diode over-stress or CMOS latchup
• Reduced Fault Coverage
– Unable to test components without violating device specifications
• Increased False Failures
– Needless replacement of good devices
– Increased repair and re-test costs
– Possible damage to product during the repair cycle
• Damaged Components
– Catastrophic or latent failures related to gate oxide breakdown, ESD protection diode over-stress or CMOS latchup
1515 Teradyne Confidential15
ICT Capabilities that Teradyne Designed into TestStation to ICT Capabilities that Teradyne Designed into TestStation to Enable Safe LowEnable Safe Low Voltage TestingVoltage Testing
• Test Software Controls – Multi-level digital isolation– Programmable backdrive controls– Backdrive measurement reports
• Accurate Driver/Sensors– Closed loop, low impedance pin– Guaranteed 15mV D/S accuracy– 2.3mV programming resolution– Real-time current measurement– Automatic driver verification– Programmable per-pin logic levels– Dual-level thresholds
• Dedicated Digital Controller – Fast test throughput– Consistent and repeatable timing– Reduced backdrive duration
1818 Teradyne Confidential18
Increasing Reliance on Vectorless Test Techniques to Detect Increasing Reliance on Vectorless Test Techniques to Detect FaultsFaults
• ICT capacitive test technique that is used to detect open pins on components and connectors
• Benefits– Does not require the PCBA to be Powered-Up
– Fast implementation (Learn techniques do not require the creation of complex test vectors)
– Precise pin-level diagnostics
• Limitations– Requires extra fixture hardware
– Slower test time
– Does not verify that device functions correctly
– Limitations detecting open power and ground pins
– Internal ground planes can limit fault coverage
– Small geometries reduce signal magnitudes, possibly making pins untestable or measurements unrepeatable
• ICT capacitive test technique that is used to detect open pins on components and connectors
• Benefits– Does not require the PCBA to be Powered-Up
– Fast implementation (Learn techniques do not require the creation of complex test vectors)
– Precise pin-level diagnostics
• Limitations– Requires extra fixture hardware
– Slower test time
– Does not verify that device functions correctly
– Limitations detecting open power and ground pins
– Internal ground planes can limit fault coverage
– Small geometries reduce signal magnitudes, possibly making pins untestable or measurements unrepeatable
1919 Teradyne Confidential19
Teradyne’s 3Teradyne’s 3rdrd Generation Vectorless Test Solution – Generation Vectorless Test Solution – Framescan FX 2.0Framescan FX 2.0
•Hardware and Software Enhancements
–Redesigned multiplexer and amplifier hardware
–Signal to noise ratio improvements of more than 20dbV
–Conformally coated amplifier for better noise immunity
–Includes advanced learn algorithms for setting test limits
•Provides increased fault coverage
–Improves test coverage on the smallest package technologies
–Increased measurement sensitivity (5pA @9.5KHz)
•Provides increased measurement stability
–Improves pin threshold settings
–Reduces risk of false calls on device pins
–Enhances board to board consistency
•Hardware and Software Enhancements
–Redesigned multiplexer and amplifier hardware
–Signal to noise ratio improvements of more than 20dbV
–Conformally coated amplifier for better noise immunity
–Includes advanced learn algorithms for setting test limits
•Provides increased fault coverage
–Improves test coverage on the smallest package technologies
–Increased measurement sensitivity (5pA @9.5KHz)
•Provides increased measurement stability
–Improves pin threshold settings
–Reduces risk of false calls on device pins
–Enhances board to board consistency
0
50
100
150
200
250
300
350
2 5 6 7 8 11 12 13 14 17 18 19 20
OpenXpress FrameScan FS with new FX probe
0
50
100
150
200
250
300
350
2 5 6 7 8 11 12 13 14 17 18 19 20
OpenXpress FrameScan FS with new FX probe
2121 Teradyne Confidential21
Trends Driving Loss of Physical AccessTrends Driving Loss of Physical Access
• Increasingly more complex bare boards (HDI)
• Blind and buried vias, via in pad– 4 mil diameter finished holes
• Track width and spacing decreasing– 3 mil lines 3 mil spacing 1 oz copper
– 2 mil lines 2 mil spacing ½ oz copper
• Less copper available on board surface for electrical test access
• High Speed Busses– Nets cannot tolerate additional impedance of test pads
– Differential signals double I/O pincount and reduce voltage swings
• Serial DFT Protocols like BSCAN and CAN– Allow designers to remove test points
• Increasing test fixture costs and complexity– Reduce costs with less probes
• Increasingly more complex bare boards (HDI)
• Blind and buried vias, via in pad– 4 mil diameter finished holes
• Track width and spacing decreasing– 3 mil lines 3 mil spacing 1 oz copper
– 2 mil lines 2 mil spacing ½ oz copper
• Less copper available on board surface for electrical test access
• High Speed Busses– Nets cannot tolerate additional impedance of test pads
– Differential signals double I/O pincount and reduce voltage swings
• Serial DFT Protocols like BSCAN and CAN– Allow designers to remove test points
• Increasing test fixture costs and complexity– Reduce costs with less probes
0.005”
0.003”
2222 Teradyne Confidential22
What Loss of Electrical Test Access Means for ICT...What Loss of Electrical Test Access Means for ICT...
• Elimination of ICT as a viable test strategy for some products
– Portable consumer products like cell phones, audio players, etc
• Increased requirements for integrated reduced access tools
– Boundary scan interconnect and virtual pin testing
– Adaptive test generation
– Indirect testing through serial resistors and buffers
– Functional cluster testing
– Sophisticated diagnostic algorithms
– Combined boundary scan and vectorless test techniques
• Increased need to complement ICT with other test techniques
– AOI, AXI, and Functional test
– BSCAN and BIST
– Distributed Test Strategies
• ICT systems configured for reduced test roles
– Scalable ICT systems to match reduced test requirements
– Ability to integrate easily with other 3rd party tools
• Elimination of ICT as a viable test strategy for some products
– Portable consumer products like cell phones, audio players, etc
• Increased requirements for integrated reduced access tools
– Boundary scan interconnect and virtual pin testing
– Adaptive test generation
– Indirect testing through serial resistors and buffers
– Functional cluster testing
– Sophisticated diagnostic algorithms
– Combined boundary scan and vectorless test techniques
• Increased need to complement ICT with other test techniques
– AOI, AXI, and Functional test
– BSCAN and BIST
– Distributed Test Strategies
• ICT systems configured for reduced test roles
– Scalable ICT systems to match reduced test requirements
– Ability to integrate easily with other 3rd party tools
2323 Teradyne Confidential23
Teradyne Limited Access ICT ToolsTeradyne Limited Access ICT Tools
• Scan Pathfinder
• Digital Jumpers
• Remote Drive / Sense
• Indirect Vectorless Test
• Cluster Testing
• Functional Testing
• Adaptive Test Generators
• Combined BSCAN and Vectorless Test
• Scan Pathfinder
• Digital Jumpers
• Remote Drive / Sense
• Indirect Vectorless Test
• Cluster Testing
• Functional Testing
• Adaptive Test Generators
• Combined BSCAN and Vectorless Test
ComponentunderTestNail 1
ComponentunderTest Nail 2
Nail 3
Remote Drive
Digital Jumper
Remote Sense
Component under TestPCB
Standard NailValues below 10K
In VoutR
FrequencyDC 100K
-3db
2424 Teradyne Confidential24
Low Noise Active Buffer
Connector or non-BS ICUnder-Test
PrintedCircuit Board
FilterFilter
Multiplexer
Synchronous Digitizer
Probe Plate Sensor
GainGain
FrameScanMultiplexer Board
Output Signal
Combined BSCAN and Vectorless Test TechniqueCombined BSCAN and Vectorless Test Technique
Boundary Scan BGA
Test Access Port (TAP)
ATE Digital Drivers
High Speed Signalswith no Test Pad Access
Re-gain testability on high speed signals through virtual access
2525 Teradyne Confidential25
Define multiplestrategies
Import PCB data
Compare coveragesand select final
strategy
Export embedded strategy specific machine
files automatically
Models multiple test strategies Objectively reports fault coverage Supports test point reductions Selects optimal test strategy
AOI Reflow AXI Prober ICT
Implement Test Strategy
Test Strategy Analysis ToolTest Strategy Analysis Tool
2727 Teradyne Confidential27
Teradyne BSCAN Survey FindingsTeradyne BSCAN Survey Findings
• Boundary scan designs are increasing– More boundary scan parts to choose from– No longer a price disadvantage to use them– Design tools support boundary scan– Viable reduced access test strategy
• Boundary scan features are being used throughout the product life cycle– Design, Prototype, NPI, Production, Field Operation, and Service/Repair depot
• Manufacturers are using many different boundary scan solutions– No clear market winner– They prefer to use the benchtop solution with which they are most familiar– General confidence that all solutions can perform standard boundary scan tests– Mixed feelings regarding how to use boundary scan at ICT
• Features rated most important in a good boundary scan solution1. Vector Portability2. ATPG software and Debug Tools3. Diagnostic Accuracy4. ICT/MDA Integration5. Cost
• Boundary scan designs are increasing– More boundary scan parts to choose from– No longer a price disadvantage to use them– Design tools support boundary scan– Viable reduced access test strategy
• Boundary scan features are being used throughout the product life cycle– Design, Prototype, NPI, Production, Field Operation, and Service/Repair depot
• Manufacturers are using many different boundary scan solutions– No clear market winner– They prefer to use the benchtop solution with which they are most familiar– General confidence that all solutions can perform standard boundary scan tests– Mixed feelings regarding how to use boundary scan at ICT
• Features rated most important in a good boundary scan solution1. Vector Portability2. ATPG software and Debug Tools3. Diagnostic Accuracy4. ICT/MDA Integration5. Cost
2828 Teradyne Confidential28
Teradyne’s ICT Boundary Scan StrategyTeradyne’s ICT Boundary Scan Strategy
1) Maintain native Teradyne 1149.1 BSCAN Solutions– BasicSCAN and Scan Pathfinder
– For manufacturers who are not already using benchtop BSCAN solutions
– For manufacturers who do not have a BSCAN test portability requirement
– For manufacturers who do not want to add extra instruments or special fixture wiring
2) Collaborate with Popular Benchtop BSCAN Vendors– Provide “integration friendly” tester environment for Benchtop BSCAN
solutions (Goepel, JTAG Technologies, Asset, Corelis, Acculogic)
– For manufacturers who have BSCAN test requirements beyond 1149.1
– For manufacturers who want to re-use boundary scan tests created in their engineering labs
1) Maintain native Teradyne 1149.1 BSCAN Solutions– BasicSCAN and Scan Pathfinder
– For manufacturers who are not already using benchtop BSCAN solutions
– For manufacturers who do not have a BSCAN test portability requirement
– For manufacturers who do not want to add extra instruments or special fixture wiring
2) Collaborate with Popular Benchtop BSCAN Vendors– Provide “integration friendly” tester environment for Benchtop BSCAN
solutions (Goepel, JTAG Technologies, Asset, Corelis, Acculogic)
– For manufacturers who have BSCAN test requirements beyond 1149.1
– For manufacturers who want to re-use boundary scan tests created in their engineering labs
2929 Teradyne Confidential29
Fostering Partnerships with 3Fostering Partnerships with 3rdrd Party Party BSCAN Solutions BSCAN Solutions
• Level 3: Product Available (from Bscan Vendor) – Goepel SFX Plug-In Card
Designed by Goepel with Teradyne’s support and cooperation Introduced at Electronica in November 2006
– JTAG Symphony 228X Converts JTAG vectors to Teradyne test language – no JTAG instrumentation required
• Level 2: Semi-Automated– JTAG Symphony 228X Plus
Incorporates JTAG instrumentation into TestStation for fast PLD programming TestStation Hybrid Test Model available
– Acculogic CFB Connection TAP signals are routed through Teradyne CFB
• Level 1: Application Note– Asset Intertech Scanworks
Application implemented at Mil/Aero and Storage manufacturers
– Corelis ScanPlus Application Note available on Support site
• Level 3: Product Available (from Bscan Vendor) – Goepel SFX Plug-In Card
Designed by Goepel with Teradyne’s support and cooperation Introduced at Electronica in November 2006
– JTAG Symphony 228X Converts JTAG vectors to Teradyne test language – no JTAG instrumentation required
• Level 2: Semi-Automated– JTAG Symphony 228X Plus
Incorporates JTAG instrumentation into TestStation for fast PLD programming TestStation Hybrid Test Model available
– Acculogic CFB Connection TAP signals are routed through Teradyne CFB
• Level 1: Application Note– Asset Intertech Scanworks
Application implemented at Mil/Aero and Storage manufacturers
– Corelis ScanPlus Application Note available on Support site
Inte
grat
ion
Lev
els
Integration and partnership activities are driven by customer opportunities
3030 Teradyne Confidential30
Example 3Example 3rdrd Party Bscan Product Solutions Party Bscan Product Solutions
• Goepel CFB plug-in card– Integrated on TestStation CFB– Allows re-use of Goepel bscan tests– Three versions supported with different
capacity and pricing
• Two JTAG Technologies Integration Options– CFM option for TestStation CFB– Test language converter using DSM– Allows re-use of JTAG bscan tests – Product name Symphony
• Goepel CFB plug-in card– Integrated on TestStation CFB– Allows re-use of Goepel bscan tests– Three versions supported with different
capacity and pricing
• Two JTAG Technologies Integration Options– CFM option for TestStation CFB– Test language converter using DSM– Allows re-use of JTAG bscan tests – Product name Symphony
3232 Teradyne Confidential32
ICT Operation ChallengesICT Operation Challenges
• Manufacturing move to lower cost regions– Untrained test operators
– High employee turnover
– May only understand local language
• Time to market pressures– Not enough time for training
– Learn on the job
– Difficulty using advanced features of the tester
– Limited time to debug marginal tests or optimize fault coverage
– Compromised fault coverage results
Need for program development and debug accelerators…
• Manufacturing move to lower cost regions– Untrained test operators
– High employee turnover
– May only understand local language
• Time to market pressures– Not enough time for training
– Learn on the job
– Difficulty using advanced features of the tester
– Limited time to debug marginal tests or optimize fault coverage
– Compromised fault coverage results
Need for program development and debug accelerators…
3333 Teradyne Confidential33
• Short learning curve– Easy access to debug and production tasks
– Graphical editing of tests
– Quick access to board data
– Exposes powerful features of the tester
• Charts reveal quality of test measurement
• Linked CAD and schematic views
• Optional performance meters
• Local language capability
• Flexible Limit modes prevents unauthorized operator changes
• Standard Windows controls
• “Classic” mode available for expert users
New Operator User Interfaces Simplify and Shorten New Operator User Interfaces Simplify and Shorten Typical ICT Debug and Production ActivitiesTypical ICT Debug and Production Activities
3434 Teradyne Confidential34
New User Interfaces Simplify Vectorless Test Debug New User Interfaces Simplify Vectorless Test Debug ActivitiesActivities
• New User Interface simplifies Vectorless Test Debug Activities
• Detailed measurement results for each pin
• Point and click debug
• No Test Language Required
• New User Interface simplifies Vectorless Test Debug Activities
• Detailed measurement results for each pin
• Point and click debug
• No Test Language Required
3535 Teradyne Confidential35
Automated Tools Measure and Enhance Test QualityAutomated Tools Measure and Enhance Test Quality
• Test Quality Tools– AutoDebug - Automatically debugs failing and marginal tests
– AutoAdjust – Can automatically shift and/or widen test limits
– Analyze (Allfault) – Reports fault coverage and test reliability
• Customizable based on user defined quality criteria– User specifies metrics for both accuracy and stability per test type
– Command file provides hands-off execution
• Test Quality Tools– AutoDebug - Automatically debugs failing and marginal tests
– AutoAdjust – Can automatically shift and/or widen test limits
– Analyze (Allfault) – Reports fault coverage and test reliability
• Customizable based on user defined quality criteria– User specifies metrics for both accuracy and stability per test type
– Command file provides hands-off execution
3737 Teradyne Confidential37
Challenges for High Volume ManufacturersChallenges for High Volume Manufacturers
• PCB assembly equipment speeds continue to increase– Manufacturing beat rates can be less than 30 seconds
• In-circuit tester becomes bottleneck on manufacturing line– ICT test times limit the amount of boards that can be manufactured
• Manufacturing facilities often have limited floor space– Adding additional test equipment is not always possible
• PCB assembly equipment speeds continue to increase– Manufacturing beat rates can be less than 30 seconds
• In-circuit tester becomes bottleneck on manufacturing line– ICT test times limit the amount of boards that can be manufactured
• Manufacturing facilities often have limited floor space– Adding additional test equipment is not always possible
ChipShooter
ReflowSolder
ScreenPrinter
Fine PitchPlacement AOI
ICT
Functional Test
3838 Teradyne Confidential38
Program Optimization Tools Can Help…Program Optimization Tools Can Help…
• Optimizes AC measurement parameters• Select fastest Shorts testing algorithm (linear or binary)• Reduces program Delay values• Optimizes expected values to minimize Instrument Autoranging
3939 Teradyne Confidential39
• TestStation TSR Models
– Tester Instruments available in 19” rack mount chassis
– Power Controller Assembly
– Integration Manual
• Custom Configurations– Three receiver options– Selectable multiplexing– Vacuum or Press-Down
• Automation partners
– Nutek, IPTE, Hirata
• TestStation TSR Models
– Tester Instruments available in 19” rack mount chassis
– Power Controller Assembly
– Integration Manual
• Custom Configurations– Three receiver options– Selectable multiplexing– Vacuum or Press-Down
• Automation partners
– Nutek, IPTE, Hirata
Inline Automated Solutions can Eliminate Handling TimesInline Automated Solutions can Eliminate Handling Times
IPTE
Hirata
Nutek
ICT instruments available as Rack Mount components for easy integration into automated
handler systems
4040 Teradyne Confidential40
Other Methods Used to Satisfy High Volume Test Other Methods Used to Satisfy High Volume Test Requirements… and their DrawbacksRequirements… and their Drawbacks
• Add additional testers to the manufacturing line– Increases capital equipment, test fixture, and operation costs
– Requires additional manufacturing floor space and test cells
• Underutilize tester by removing tests– Reduced fault coverage
– Extra program maintenance
• Remove in-circuit test from manufacturing line– Implement less effective inspection strategy
– Increased chance of shipping defective products
• Add additional testers to the manufacturing line– Increases capital equipment, test fixture, and operation costs
– Requires additional manufacturing floor space and test cells
• Underutilize tester by removing tests– Reduced fault coverage
– Extra program maintenance
• Remove in-circuit test from manufacturing line– Implement less effective inspection strategy
– Increased chance of shipping defective products
ChipShooter
ReflowSolder
ScreenPrinter
Fine PitchPlacement AOI
ICTFunctional
Test
4141 Teradyne Confidential41
• Completely concurrent test operation
– Supports simultaneous testing of two boards
– All test techniques support parallel test
• Twice the throughput of standard ICT testers
– Doubles test throughput in the same footprint as single test system
• Manual or automated versions
– Easy integration into automated manufacturing lines
• Significant cost savings
– Less expensive equipment, fixture, and operation costs
• Completely concurrent test operation
– Supports simultaneous testing of two boards
– All test techniques support parallel test
• Twice the throughput of standard ICT testers
– Doubles test throughput in the same footprint as single test system
• Manual or automated versions
– Easy integration into automated manufacturing lines
• Significant cost savings
– Less expensive equipment, fixture, and operation costs
A New Concurrent Test SolutionA New Concurrent Test Solution
4242 Teradyne Confidential42
Concurrent Test Solution – Economic Benefits Concurrent Test Solution – Economic Benefits
Existing Single ICT Solution
2 Single ICT Solution Solution
Capital Cost
(5 year dep.)$30K $60K $56K
Fixture Costs $30K $60K $33K
Labor Costs(2 Shifts)
$70K $140K $70K
Extra Test Cell Cost
$0K $75K $0K
Total Cost $130K $335K $159K
Panels Tested Per Year 140,000 280,000 280,000
Test Cost per Panel per Year
$0.93 $1.20 $0.57
Duo solution saved manufacturer $176K and reduced cost per panel by $0.63
Does not meet requirements
4444 Teradyne Confidential44
Teradyne ICT Test Platform SummaryTeradyne ICT Test Platform Summary
• Scalable ICT system design– Configurable from MDA+ to high performance / high pincount digital
• New Driver/Sensor Pin Electronics– For safe, accurate and reliable testing of low voltage technologies
• Improved vectorless test technologies– For reliable testing of microBGA and small package components and connectors
– New techniques for combining BSCAN and Framescan technologies
• Reduced access test solutions– For gaining test access to nets that do not have physical test access
• Flexible boundary scan solutions– Allows 3rd Party boundary scan tests to be re-used
– Teradyne Native 1149.1 boundary scan support
• Graphical mouse-based debug and production user interfaces– Software that is easier to use and learn
• Configurable for high volume requirements– Optimized test throughput tools
– Integrated inline solutions
– Concurrent test capabilities
• Scalable ICT system design– Configurable from MDA+ to high performance / high pincount digital
• New Driver/Sensor Pin Electronics– For safe, accurate and reliable testing of low voltage technologies
• Improved vectorless test technologies– For reliable testing of microBGA and small package components and connectors
– New techniques for combining BSCAN and Framescan technologies
• Reduced access test solutions– For gaining test access to nets that do not have physical test access
• Flexible boundary scan solutions– Allows 3rd Party boundary scan tests to be re-used
– Teradyne Native 1149.1 boundary scan support
• Graphical mouse-based debug and production user interfaces– Software that is easier to use and learn
• Configurable for high volume requirements– Optimized test throughput tools
– Integrated inline solutions
– Concurrent test capabilities