Beaglebone Black Reference Menu

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REF: BBONEBLK_SRM BeagleBone Black SystemReference Manual

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Table of Contents

FIGURES ....................................................................................................................................................... 4

TABLES ......................................................................................................................................................... 5

1.0 INTRODUCTION ............................................................................................................................... 6

2.0 CHANGE HISTORY .......................................................................................................................... 6

2.1 CHANGE HISTORY ............................................................................................................................. 6

3.0 BEAGLEBONE BLACK OVERVIEW ............................................................................................. 6

3.1 BEAGLEBONE COMPATIBILITY .......................................................................................................... 63.2 IN THE BOX ....................................................................................................................................... 73.3 SERIAL DEBUG CABLE ....................................................................................................................... 83.4 HDMICABLE .................................................................................................................................... 83.5 5VDCPOWER SUPPLY....................................................................................................................... 9

4.0 BEAGLEBONE BLACK FEATURES AND SPECIFICATION .................................................. 10

4.1 BOARD COMPONENT LOCATIONS .................................................................................................... 11

5.0 BEAGLEBONE BLACK HIGH LEVEL SPECIFICATION ....................................................... 12

5.1 BLOCK DIAGRAM ............................................................................................................................ 125.2 PROCESSOR ...................................................................................................................................... 125.3 MEMORY ......................................................................................................................................... 13

5.3.1 DDR3L ............ ........... .......... ........... .......... ........... .......... ........... .......... ........... .......... ........... .. 135.3.2 EEPROM ........... .......... ........... .......... ........... .......... ........... ........... .......... ........... .......... .......... . 135.3.3 Embedded MMC ......... ........... .......... .......... ........... .......... ........... .......... ........... .......... .......... ... 135.3.4 MicroSD Connector ............ ........... .......... ........... .......... ........... ........... .......... ........... .......... ... 135.3.5 Boot Modes ........... .......... ........... .......... ........... .......... ........... .......... ........... .......... ........... ........ 14

5.4 POWER MANAGEMENT .................................................................................................................... 145.5 PCUSBINTERFACE ........................................................................................................................ 155.6 SERIAL DEBUG PORT ....................................................................................................................... 15

5.7 USB1HOST PORT ............................................................................................................................ 155.8 POWER SOURCES ............................................................................................................................. 155.9 RESET BUTTON ................................................................................................................................ 165.10 INDICATORS ................................................................................................................................ 165.11 CTIJTAGHEADER .................................................................................................................... 165.12 HDMIINTERFACE ...................................................................................................................... 165.13 CAPE BOARD SUPPORT ............................................................................................................... 16

6.0 DETAILED HARDWARE DESIGN ............................................................................................... 18

6.1 POWER SECTION .............................................................................................................................. 196.1.1 TPS65217C PMIC ................................................................................................................. 196.1.2 DC Input ........... .......... ........... .......... ........... .......... ........... ........... .......... ........... .......... .......... .. 216.1.3 USB Power ............................................................................................................................ 21

6.1.4 Power Selection ........... .......... ........... .......... ........... ........... .......... ........... .......... ........... .......... . 226.1.5 Power Consumption ................... .......... ........... .......... ........... .......... .......... ........... .......... ........ 236.1.6 Processor Interfaces .......... .......... ........... .......... ........... .......... ........... ........... .......... ........... ..... 236.1.7 Power Rails .................. .......... ........... ........... .......... ........... ........... .......... ........... ........... ........ . 246.1.8 Power LED .......... ........... .......... ........... .......... ........... ........... .......... ........... .......... ........... ........ 276.1.9 TPS65217C Power Up Process ............................................................................................. 276.1.10 Processor Control Interface .......... .......... ........... .......... ........... .......... ........... ........... ......... 286.1.11 Low Power Mode Support .......... .......... ........... .......... .......... ........... .......... .......... .......... .... 28

6.2 XAM3359ZCZPROCESSOR ............................................................................................................ 296.2.1 Description ........... ........... .......... ........... ........... .......... ........... ........... .......... ........... .......... ....... 29


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6.2.2 High Level Features .......... .......... ........... ........... .......... ........... ........... ........... .......... ........... .... 306.2.3 Documentation ............... ........... ........... ........... .......... ........... ........... .......... ........... ........... ...... 30

6.3 DDR3MEMORY .............................................................................................................................. 316.3.1 Memory Device.......... .......... ........... ........... .......... ........... ........... .......... ........... ........... .......... .. 316.3.2 DDR3 Memory Design .................... .......... ........... .......... ........... .......... ........... .......... ........... .. 316.3.3 Power Rails .................. .......... ........... ........... .......... ........... ........... .......... ........... ........... ........ . 33

6.3.4 VREF ..................................................................................................................................... 336.4 EMMCMEMORY ............................................................................................................................. 34

6.4.1 eMMC Device ........................................................................................................................ 346.4.2 eMMC Circuit Design ........................................................................................................... 34

6.5 MICRO SECURE DIGITAL.................................................................................................................. 366.5.1 uSD Design ............................................................................................................................ 36

6.6 USER LEDS ..................................................................................................................................... 376.7 BOOT CONFIGURATION .................................................................................................................... 37

6.7.1 Boot Configuration Design....... ........... .......... ........... .......... ........... .......... ........... ........... ........ 376.7.2 Boot Options ......... ........... .......... ........... ........... .......... ........... .......... ........... .......... ........... ....... 38

6.8 10/100ETHERNET ............................................................................................................................ 396.8.1 Ethernet Processor Interface .......... ........... .......... ........... ........... .......... ........... ........... .......... .. 396.8.2 Ethernet Connector Interface ........... .......... ........... .......... ........... .......... ........... .......... ........... . 40

6.8.3 Ethernet PHY Power, Reset, and Clocks ......... ........... ........... .......... ........... .......... ........... ...... 416.8.4 LAN8710A Mode Pins ........... .......... ........... .......... ........... .......... ........... ........... .......... ........... . 426.9 HDMIINTERFACE ........................................................................................................................... 42

6.9.1 HDMI Framer ................. .......... ........... ........... .......... ........... ........... .......... ........... ........... ...... 436.9.2 HDMI Video Processor Interface .......... ........... .......... ........... .......... ........... .......... ........... ...... 436.9.3 HDMI Control Processor Interface .......... ........... ........... .......... ........... ........... .......... ........... .. 436.9.4 Interrupt Signal ................. ........... .......... ........... .......... .......... ........... .......... ........... .......... ...... 446.9.5 Audio Interface ........... .......... ........... .......... ........... .......... ........... .......... ........... ........... .......... .. 446.9.6 Power Connections .......... ........... ........... .......... ........... .......... ........... .......... ........... .......... ....... 456.9.7 HDMI Connector Interface ................ .......... ........... .......... ........... .......... ........... ........... ......... 46

7.0 CONNECTORS ................................................................................................................................. 47

7.1 EXPANSION CONNECTORS ............................................................................................................... 47

7.1.1

Connector P8 ......................................................................................................................... 48

7.1.2 Connector P9 ......................................................................................................................... 507.2 POWER JACK .................................................................................................................................... 527.3 USBCLIENT .................................................................................................................................... 537.4 USBHOST ....................................................................................................................................... 547.5 SERIAL HEADER .............................................................................................................................. 557.6 HDMI .............................................................................................................................................. 567.7 USD ................................................................................................................................................. 577.8 ETHERNET ....................................................................................................................................... 58

8.0 CAPE BOARD SUPPORT ............................................................................................................... 59

8.1 EEPROM ........................................................................................................................................ 598.1.1 EEPROM Address ......... ........... ........... .......... ........... .......... ........... .......... ........... .......... ......... 608.1.2 I2C Bus .......... .......... .......... ........... .......... ........... .......... .......... ........... .......... ........... .......... ...... 608.1.3 EEPROM Write Protect ......... .......... ........... .......... ........... .......... ........... .......... ........... ........... 618.1.4 EEPROM Data Format .......... .......... ........... .......... ........... .......... ........... .......... ........... ........... 628.1.5 Pin Usage .......... ........... .......... ........... .......... ........... .......... ........... .......... ........... ........... ......... . 63

8.2 PIN USAGE CONSIDERATION ............................................................................................................ 678.2.1 Boot Pins .................. ........... .......... ........... .......... ........... .......... ........... ........... .......... .......... .... 67

8.3 EXPANSION CONNECTORS ............................................................................................................... 688.3.1 Non-Stacking Headers-Single Cape .......... .......... ........... .......... .......... ........... .......... ........... .. 688.3.2 Battery Connector- Single ........... .......... ........... .......... ........... .......... ........... ........... .......... ...... 698.3.3 Main Expansion Headers-Stacking .......... ........... .......... .......... ........... .......... .......... .......... ..... 70


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8.3.4 Stacked Capes w/Signal Stealing ........................................................................................... 718.3.5 Retention Force ........... ........... .......... ........... .......... ........... .......... ........... .......... ........... .......... . 718.3.6 BeagleBone Black Female Connectors ............... .......... ........... ........... .......... ........... .......... ... 72

8.4 SIGNAL USAGE ................................................................................................................................ 728.5 CAPE POWER ................................................................................................................................... 73

8.5.1 Main Board Power ......... ........... .......... ........... .......... .......... ........... .......... ........... .......... ......... 73

8.5.2 Expansion Board External Power .......... .......... ........... .......... .......... ........... .......... .......... ....... 748.6 MECHANICAL .................................................................................................................................. 74

8.6.1 Standard Cape Size ............................................................................................................... 758.6.2 Extended Cape Size .................... .......... ........... .......... ........... .......... ........... .......... ........... ....... 758.6.3 Enclosures ........... ........... .......... ........... .......... ........... .......... ........... .......... ........... .......... ......... 76

9.0 BEAGLEBONE BLACK MECHANICAL SPECIFICATION ..................................................... 77

10.0 DESIGN INFORMATION........................................................................................................... 79

Figures

Figure 1. FTDI Serial cable ............................................................................................ 8Figure 2. Micro HDMI Cable ......................................................................................... 8Figure 3. 5VDC Power Supply....................................................................................... 9Figure 4. Key Components ........................................................................................... 11Figure 5. BeagleBone Black Block Diagram ............................................................... 12Figure 6. Block Diagram .............................................................................................. 18Figure 7. High Level Power Block Diagram ................................................................ 19Figure 8. TPS65217C Block Diagram ......................................................................... 20Figure 9. DC Power Connections ................................................................................. 21Figure 10. USB Power Connections........................................................................... 22Figure 11. Power Rails ............................................................................................... 24

Figure 12. Power Sequencing ..................................................................................... 26Figure 13. Power Sequencing ..................................................................................... 26Figure 14. Power Processor Interfaces ....................................................................... 27Figure 15. XAM3359 Block Diagram ........................................................................ 29Figure 16. DDR3 Memory Design ............................................................................. 32Figure 17. DDR3 VREF Design................................................................................. 33Figure 18. eMMC Memory Design ............................................................................ 35Figure 19. uSD Design ............................................................................................... 36Figure 20. User LEDs ................................................................................................. 37Figure 21. Processor Boot Configuration Design ...................................................... 38Figure 22. Processor Boot Configuration ................................................................... 38

Figure 23. Ethernet Processor Interface ..................................................................... 39Figure 24. Ethernet Connector Interface .................................................................... 40Figure 25. Ethernet PHY, Power, Reset, and Clocks ................................................. 41Figure 26. Ethernet PHY Mode Pins .......................................................................... 42Figure 27. HDMI Framer Processor Interface ............................................................ 44Figure 28. HDMI Power Connections ........................................................................ 45Figure 29. Connector Interface Circuitry ................................................................... 46Figure 30. Expansion Connector Location ................................................................. 47


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Figure 31. 5VDC Power Jack ..................................................................................... 52Figure 32. USB Client Connector .............................................................................. 53Figure 33. USB Host Connector................................................................................. 54Figure 34. Serial Debug Header ................................................................................. 55Figure 35. FTDI USB to Serial Adapter ..................................................................... 55

Figure 36. HDMI Connector ...................................................................................... 56Figure 37. HDMI Connector ...................................................................................... 56Figure 38. uSD Connector .......................................................................................... 57Figure 39. Ethernet Connector ................................................................................... 58Figure 40. Expansion Board EEPROM No Write Protect ......................................... 60Figure 41. Expansion Board EEPROM Write Protect ............................................... 61Figure 42. Expansion Boot Pins ................................................................................. 67Figure 43. Single Expansion Connector ..................................................................... 68Figure 44. Single Cape Expansion Connector............................................................ 69Figure 45. Battery/Backlight Expansion Connector ................................................... 69Figure 46. Expansion Connector ................................................................................ 70

Figure 47. Stacked Cape Expansion Connector ......................................................... 70Figure 48. Stacked w/Signal Stealing Expansion Connector ..................................... 71Figure 49. Connector Pin Insertion Depth.................................................................. 72Figure 50. Cape Board Dimensions .......................................................................... 75Figure 51. Board Top Side Profile ............................................................................. 77Figure 52. Board Bottom Profile ................................................................................ 78

TablesTable 1. Change History ............................................................................................... 6Table 2. BeagleBone Black Features .......................................................................... 10

Table 3. BeagleBone Power Consumption(mA@5V) ................................................ 23Table 4. Processor Features ........................................................................................ 30Table 5. eMMC Boot Pins .......................................................................................... 35Table 6. TDA19988 I2C Address ............................................................................... 43Table 7. Expansion Header P8 Pinout ........................................................................ 49Table 8. Expansion Header P9 Pinout ........................................................................ 51Table 9. Expansion Board EEPROM .......................................................................... 62Table 10. EEPROM Pin Usage ..................................................................................... 64Table 11. Single Cape Connectors ................................................................................ 69Table 12. Single Cape Backlight Connectors ............................................................... 70Table 13. Stacked Cape Connectors ............................................................................. 71

Table 14. Expansion Voltages ...................................................................................... 73


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1.0 Introduction

This document is the System reference Manualfor the BeagleBone Black. It covers thedesign for the BeagleBone Black. The board will be referred to in the remainder of thisdocument as BeagleBone Black. There are also references to the original BeagleBone aswell.

This design is subject to change without notice as we will work to keep improving thedesign as the product matures.

2.0 Change History

2.1 Change History

Table 1. Change History

Rev Changes Date By

A4 Preliminary January 4, 2013 GC

3.0 BeagleBone Black Overview

The BeagleBone Black is the latest addition to the BeagleBoard.org family and like itspredecessors, is designed to address the Open Source Community, early adopters, andanyone interested in a low cost ARM Cortex A8 based processor. It has been equippedwith a minimum set of features to allow the user to experience the power of the processorand is not intended as a full development platform as many of the features and interfacessupplied by the processor are not accessible from the BeagleBone Black via onboardsupport of some interfaces.

3.1 BeagleBone Compatibility

The BeagleBone Black is intended to be compatible with the original BeagleBone asmuch as possible. There are a several areas where there are differences between the twodesigns. These differences are listed below along with the reasons for the differences.

AM3358A Processor, 800MHz operation

512MB DDR3Lo Cost reduction


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o Performance increaseo Memory size increaseo Lower power

No Serial port by default.o Cost reductiono Can be added by buying a TTL to USB Cable that is widely available

No JTAG emulation over USB.o Cost reductiono JTAG header is not populated, but can easily be mounted.

Onboard Managed NANDo Cost reductiono Performance boost x8 vs. x4 bitso Performance boost due to deterministic properties vs. SD card

GPMC bus may not be accessible from the expansion headers in some caseso Result of eMMC on the main boardo Signals are routed to the expansion connectoro If eMMC is not used, signals can be used via expansion if eMMC is held

in reset

There may be 10 less GPIO pins availableo Result of eMMCo If eMMC is not used, could be used

No power expansion Headero Cost reductiono Space reduction

HDMI interface onboardo Feature additiono Audio and video capableo Micro HDMI

No onboard USB JTAG emulationo Major cost reduction

No three function USB cableo Major cost reduction

3.2 In The Box

The BeagleBone Black will ship with the following components:

BeagleBone Black 5 pin miniUSB Cable


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3.3 Serial Debug Cable

Additional cables that are not supplied with the board may be needed.

To access the serial debug port on the processor, a serial to TTL cable is required. The

part number is TTL-232R-3V3 and can be purchased from numerous different sources.

This cable can be purchased for FTDI athttp://apple.clickandbuild.com/cnb/shop/ftdichip?op=catalogue-products-null&prodCategoryID=105&title=USB-TTL+0.1%94+Socket

For a list of sales channels go to http://www.ftdichip.com/FTSalesNetwork.htm

Figure 1. FTDI Serial cable

3.4 HDMI Cable

To access the HDMI output, a microHDMI cable is required as pictured below.

Figure 2. Micro HDMI Cable

The cable is available from numerous sources such as Amazonhttp://www.amazon.com/Amzer-Micro-HDMI-Speed-Cable/dp/B003OBZSHC.


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Prices can range from $10 to $25.

3.5 5VDC Power Supply

Current via the USB port is limited to 500mA by the power management device on theboard. Exceeding this current will cause the board to shut off. Running from an externalDC power supply solves this issue. The board uses the same power supply as the originalBeagleBoard. A minimum of 5V at 1A is recommended. The power supply should bewell regulated and 5V +/-.5V.

A good choice for a power supply can be found athttp://www.adafruit.com/products/276

Figure 3. 5VDC Power Supply


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4.0 BeagleBone Black Features and Specification

This section covers the specifications and features of the BeagleBone Black and providesa high level description of the major components and interfaces that make up the board.

Table 2provides a list of the BeagleBone Black features.

Table 2. BeagleBone Black Features

Feature

ProcessorAM3358/9

600MHZ-USB Powered (TBD)800MHZ-DC Powered

SDRAM Memory 512MB DDR3L 606MHZ

Flash eMMC 2GB, 8bit

PMIC TPS65217C PMIC regulator and one additional LDO.

Debug Support Optional Onboard 20-pin CTI JTAG

PowerminiUSB USB or DC

Jack5VDC External Via Expansion

Header

PCB 3.4 x 2.1 6 layers

Indicators 1-Power, 2-Ethernet, 4-User Controllable LEDs

HS USB 2.0 Client PortAccess to the USB1 Client mode via miniUSB

HS USB 2.0 Host Port USB Type A Socket, 500mA LS/FS/HS

Serial Port UART0 access via 6 pin Header. Header is populated

Ethernet 10/100, RJ45

SD/MMC Connector microSD , 3.3V

User Input 1-Reset Button, 1-User Boot Button

Video Out 16b HDMI , w/ CEC

Audio Via HDMI Interface

Expansion Connectors

Power 5V, 3.3V , VDD_ADC(1.8V)3.3V I/O on all signals

McASP0, SPI1, I2C, GPIO(65), LCD, GPMC, MMC1, MMC2, 7AIN(1.8V MAX), 4 Timers, 3 Serial Ports, CAN0,

EHRPWM(0,2),XDMA Interrupt, Power button, Expansion Board ID(Up to 4 can be stacked)

Weight 1.4 oz (39.68 grams)

NOTE: THE INITIAL A4 VERSIONS WERE BUILT USING THE AM3352

PROCESSOR. THIS WAS A RESULT OF RECEIVING MISMARKED PARTS

FROM THE SUPPLIER. DUE TO THE TIGHT SCHEDULE, THE DECSION WAS

MADE TO BUILD WITH THE AM3352 VERSION AS REV A4. PRODUCTION

VERSION IS REV A5 AND WILL HAVE THE CORRECT PROCESSOR. REV A4

DOES NOT HAVE SUPPORT FOR THE PRU OR SGX


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4.1 Board Component Locations

Figure 4below shows the locations of the key components on the PCB layout of theBeagleBone Black.

Figure 4. Key Components

The Sitara AM3358is the processor.512MB DDR3is the processor dynamic RAM memory.Serial Debugis the serial debug port.PMICprovides the power rails to the various components on the board.DC Poweris the main DC input that accepts 5V power.10/100 Ethernetis the connection to the LAN.Ethernet PHYis the physical interface to the network.USB Clientis a miniUSB connection to a PC that can also power the board.

There are four blue LEDS that can be used by the user.Reset Button allows the user to reset the processor.eMMCis an onboard MMC chip that hold sup to 2GB of data.HDMIFramer provides control for an HDMI or DVI-D display.BOOT Buttoncan be used to force a boot from the SD card or from the USB port.uSDslot is where a uSD card can be installed.The microHDMIconnector is where the display is connected.USB Hostcan be connected different USB interfaces such as Wifi, BT, Keyboard, etc,


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5.0 BeagleBone Black High Level Specification

This section provides the high level specification of the BeagleBone Black.

5.1 Block Diagram

Figure 5below is the high level block diagram of the BeagleBone Black.

Figure 5. BeagleBone Black Block Diagram

5.2 Processor


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For the initial release, the board uses the XAM3359AZCZ processor in the 15x15package. This is the same processor as used on the original BeagleBone. It does use theupdated 2.0 revision with several fixes as opposed to the original BeagleBone. None ofthese fixes provide substantial additional features. Eventually the board will move to theAM3358AZCZ device once readily available. The move does provide for a frequency

increase to 800MHz.

NOTE: THE INITIAL A4 VERSIONS WERE BUILT USING THE AM3352

PROCESSOR. THIS WAS A RESULT OF RECEIVING MISMARKED PARTS

FROM THE SUPPLIER. DUE TO THE TIGHT SCHEDULE, THE DECSION WAS

MADE TO BUILD WITH THE AM3352 VERSION AS REV A4. PRODUCTION

VERSION IS REV A5 AND WILL HAVE THE CORRECT PROCESSOR. REV A4

DOES NOT HAVE SUPPORT FOR THE PRU OR SGX

5.3 Memory

Described in the following sections are the three memory devices found on theBeagleBone Black.

5.3.1 DDR3L

A single 512Mb x16 bit DDR3L 4Gb memory device is used. The memory used is theMT41K512M16HA-125 from Micron. It will operate at a clock frequency of 303MHzyielding an effective rate of 606MHZ on the DDR3 bus allowing for 1.2GB of DDR3bandwidth.

5.3.2 EEPROM

A single 32KB EEPROM is provided on I2C0 that holds the board information. Thisinformation includes board name, serial number, and revision information. This will bethe same as found on the original BeagleBone. It has a test point to allow the device tobe programmed and otherwise to provide write protection when not grounded.

5.3.3 Embedded MMC

A single 2GB embedded MMC (eMMC) device is on the board. The device will connectto the MMC1 port of the processor, allowing for 8bit wide access. Default boot mode forthe board will be MMC1 with an option to change it to MMC0 for SD card booting.

MMC0 cannot be used in 8Bit mode because the lower data pins are located on the pinsused by the Ethernet port. But this does not interfere with SD card operation but it doesmake it unsuitable for use as an eMMC port if the 8 bit feature is needed.

5.3.4 MicroSD Connector


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The board is equipped with a single microSD connector to act as the secondary bootsource for the board and if selected as such, can be the primary boot source. Theconnector will support larger capacity SD cards. No SD card is provided with the board.Booting from MMC0 will be used to flash the eMMC in the production environment orby the user to update the SW as needed.

5.3.5 Boot Modes

As mentioned earlier, there are four boot modes supported:

eMMC BootThis is the default boot mode and will allow for the fastest boottime and will enable the board to boot out of the box without having to purchasean SD card or an SD card writer.

SD BootThis mode will boot from the uSD slot. This mode can be used tooverride what is on the eMMC device and can be used to program the eMMC

when used in the manufacturing process or for filed updates. Serial BootThis mode will use the serial port to allow downloading of the

software direct. A separate serial cable is required to use this port.

USB BootThis mode supports booting over the USB port.

A switch is provided to allow switching between the modes.

Holding the switch down during boot without an SD card will force the bootsource to be the USB port and if nothing is detected on the USB port, it willgo to the serial port for download.

Without holding the switch, the board will boot from eMMC. If it is empty,

then it will try booting from the uSD slot, followed by the serial port, and thenthe USB port.

5.4 Power Management

The TPS65127C power management device is used along with a separate LDO toprovide power to the system. The TPS65127Cversion provides for the proper voltagesrequired for DDR3. This is the same device as used on the original BeagleBone with theexception of the power rail configuration settings which will be changed in the internalEEPROM to the TPS65217 to support the new voltages.

DDR3 requires 1.5V instead of 1.8V on the DDR2 as is the case on the originalBeagleBone. The 1.8V regulator has been changed to 1.5V for the DDR3. The LDO33.3V rail has been changed to 1.8V to support those rails on the processor. LDO4 is still3.3V for the 3.3V rails on the processor. An external LDOTLV70233provides the 3.3Vrail for the rest of the board.


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5.5 PC USB Interface

The board has a miniUSB connector that connects the USB0 port to the processor. This isthe same connector as used on the original BeagleBone.

5.6 Serial Debug Port

Serial debug is provided via UART0 on the processor via a single 1x6 pin header. Inorder to use the interface a USB to TTL adapter will be required. The header iscompatible with the one provided by FTDI and can be purchased for about $12 to $20from various sources. Signals supported are TX and RX. None of the handshake signalsare supported.

5.7 USB1 Host Port

On the board is a single USB Type A female connector with full LS/FS/HS Host support

that connects to USB1 on the processor. The port can provide power on/off control andup to 500mA of current at 5V. Under USB power, the board will not be able to supply thefull 500mA, but should be sufficient to supply enough current for a lower power USBdevice supplying power between 50 to 100mA.

You can use a wireless keyboard/mouse configuration or you can add a HUB for standardkeyboard and mouse interfacing.

5.8 Power Sources

The board can be powered from four different sources:

A USB port on a PC

A 5VDC 1A power supply plugged into the DC connector.

A power supply with a USB connector.

Expansion connectors

The USB cable is shipped with each board. This port is limited to 500mA by the PowerManagement IC.

The power supply is not provided with the board but can be easily obtained from

numerous sources. A 1A supply is sufficient to power the board, but if there is a capeplugged into he board, then more current may needed from the DC supply.

Power routed to the board via the expansion header could be provided from powerderived on a cape.

The DC supply should be well regulated and 5V +/-.25V.


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5.9 Reset Button

When pressed and released, causes a reset of the board. The reset button used on theBeagleBone Black is a little larger than the one used on the original BeagleBone. It has

also been moved out to the edge of the board so that it is more accessible.

5.10 Indicators

There are five total blue LEDs on the board.

One blue power LED indicates that power is applied and the powermanagement IC is up. If this LED flashes when applying power, it meansthat an excess current flow was detected and the PMIC has shutdown.

Four blue LEDs that can be controlled via the SW by setting GPIO pins.

In addition, there are two LEDs on the RJ45 to provide Ethernet status indication. One isyellow and the other is green.

5.11 CTI JTAG Header

A place for an optional 20 pin CTI JTAG header is provided on the board to facilitate theSW development and debugging of the board by using various JTAG emulators. Thisheader is not supplied standard on the board. To use this, a connector will need to besoldered onto the board.

5.12 HDMI Interface

A single HDMI interface is connected to the 16pin LCD interface on the processor. TheNXP TDA19988BHN is used to convert the LCD interface to HDMI and convert theaudio as well. The HDMI device does not support HDCP copy protection.

The signals are still connected to the expansion headers to enable the use of LCDexpansion boards or access to other functions on the board as needed.

5.13 Cape Board Support

The BeagleBone Black has the ability to accept up to four expansion boards or capes thatcan be stacked onto the expansion headers. The word cape comes from the shape of theboard as it is fitted around the Ethernet connector on the main board. This notch acts as akey to insure proper orientation of the Cape.

The majority of capes designed for the original BeagleBone will work on the BeagleBoneBlack. The two main expansion headers will be populated on the board. There are a few


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exceptions where certain capabilities may not be present or are limited to the BeagleBoneBlack. These include:

GPMC bus may NOT be available due to the use of those signals by the eMMC.If the eMMC is used for booting only and the file system is on the SD card, then

these signals could be used. Another option is to use the SD or serial boot modes and not use the eMMC.

The power expansion header is not on the BeagleBone Black so those functionsare not supported.


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6.0 Detailed Hardware Design

Figure 6below is the high level block diagram of the BeagleBone Black.

Figure 6. Block Diagram


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6.1 Power Section

Figure 7is the high level block diagram of the power section.

Figure 7. High Level Power Block Diagram

This section describes the power section of the design and all the functions performed by theTPS65217C.

6.1.1 TPS65217C PMIC

The main Power Management IC (PMIC) in the system is the TPS65217Cwhich is asingle chip power management IC consisting of a linear dual-input power path, threestep-down converters, and four LDOs. The system is supplied by a USB port or DCadapter. Three high-efficiency 2.25MHz step-down converters are targeted at providingthe core voltage, MPU, and memory voltage for the board.

The step-down converters enter a low power mode at light load for maximum efficiencyacross the widest possible range of load currents. For low-noise applications the devicescan be forced into fixed frequency PWM using the I2C interface. The step-downconverters allow the use of small inductors and capacitors to achieve a small solution

size.

LDO1 and LDO2 are intended to support system-standby mode. In normal operation theycan support up to 100mA each. LDO3 and LDO4 can support up to 285mA each.

By default only LDO1 is always ON but any rail can be configured to remain up inSLEEP state. Especially the DCDC converters can remain up in a low-power PFM modeto support processor suspend mode. The TPS65217C offers flexible power-up and

PWR_EN

Interrupt

RTC_PORZ

SYS_RESET

Power Rails

I2C0

TPS65217C

DC IN

LDO3V3


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power-down sequencing and several house-keeping functions such as power-good output,pushbutton monitor, hardware reset function and temperature sensor to protect thebattery. Note that support for the battery is not provided on the BeagleBone Black

For more information on the TPS65217C, refer to http://www.ti.com/product/tps65217.

Figure 8is the high level block diagram of theTPS65217C.

Figure 8. TPS65217C Block Diagram


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6.1.2 DC Input

The Figure 9shows how the DC input is connected to the TPS65217C.

VDD_5V

P1

PJ-200A

11

33

22

DGND

DGND

C1

10uF,10V

C2

10uF,10V

DGND

U2

TPS65217C

AC10

USB12

SYS17

SYS28

VIN_DCDC121

VIN_DCDC332

VINLDO2

LDO3_IN39

VIN_DCDC222

LDO4_IN42

USB_DC

U4

TL5209

IN2

OUT3

GND15 EN1

ADJ4

GND36

GND27

GND48

DGND

VDD_3V3A

DGND

C17

2.2uF,6.3V

Figure 9. DC Power Connections

A 5VDC supply can be used to provide power to the board. The power supply currentdepends on how many and what type of add on boards are connected to the board. Fortypical use, a 5VDC supply rated at 1A should be sufficient. If heavier use of theexpansion headers or USB host port is expected, then a higher current supply will berequired.

The connector used is a 2.1MM center positive x 5.5mm outer barrel. The 5VDC rail isconnected to the expansion header. It is possible to power the board via the expansion

headers from an add-on card. The 5VDC is also available for use by the add-on cardswhen the power is supplied by the 5VDC jack on the board.

6.1.3 USB Power

The board can also be powered from the USB port. A typical USB port is limited to500mA max. When powering from the USB port, the VDD_5V rail is not provided to


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the expansion header. So capes that require the 5V rail to supply the cape direct,bypassing the TPS65217C, will not have that rail available for use. The 5VDC supplyfrom the USB port is provided on the SYS_5V, the one that comes from theTPS65217C,rail of the expansion header for use by a cape. Figure 10is the design of the USB powerinput section.

DGND

C1

10uF,10V

U2

TPS65217C

USB12

C36

0.1uf,6.3V

DGND P4 mini USB-B

D-2 D+3

VB1

ID4

G2

7

G3

6

G15 G

5

8

G4

9

DGND

Figure 10. USB Power Connections

6.1.4 Power Selection

The selection of either the 5VDC or the USB as the power source is handled internally tothe TPS65217Cand automatically switches to 5VDC power if both are connected. SWcan change the power configuration via the I2C interface from the processor. In addition,

the SW can read the TPS65217C and determine if the board is running on the 5VDCinput or the USB input. This can be beneficial to know the capability of the board tosupply current for things like operating frequency and expansion cards.

It is possible to power the board from the USB input and then connect the DC powersupply. The board will switch over automatically to the DC input.


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6.1.5 Power Consumption

The power consumption of the board varies based on power scenarios and the board bootprocesses. Table 3is an analysis of the power consumption of the board in these variousscenarios.

Table 3. BeagleBone Black Power Consumption(mA@5V)

MODE USB DC DC+USB

Reset TBD TBD TBD

UBoot TBD TBD TBD

Kernel Booting (Peak) TBD TBD TBD

Kernel Idling TBD TBD TBD

The current will fluctuate as various activates occur, such as the LEDs on and SD cardaccesses.

6.1.6 Processor Interfaces

The processor interacts with the TPS65217C via several different signals. Each of thesesignals is described below.

6.1.6.1 I2C0I2C0 is the control interface between the processor and the TPS65217C. It allows theprocessor to control the registers inside the TPS65217C for such things as voltagescaling and switching of the input rails.

6.1.6.2 PMC_POWR_ENON power up the VDD_RTCrail activates first. After the RTC circuitry in the processorhas activated it instructs the TPS65217C to initiate a full power up cycle by activatingthe PMIC_POWR_ENsignal by taking it HI.

6.1.6.3 LDO_GOODThis signal connects to the RTC_PORZnsignal, RTC power on reset. As the RTC

circuitry come sup first, this signal indicated that the LDOs, the 1.8V VRTC rail, is upand stable. This starts the power up process.

6.1.6.4 PMIC_PGOODOnce all the rails are up, the PMIC_PGOOD signal goes high. This release the PORZnsignal on the processor which was holding the processor reset.


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6.1.6.5 WAKEUPThe WAKEUP signal from the TPS65217Cis connected to the EXT_WAKEUPsignalon the processor. This is used to wake up the processor when it I sin a sleep mode and anevent from the TPS65217C, such as the power button, is pressed.

6.1.6.6 PMIC_INTThe PMIC_INTsignal is an interrupt signal to the processor. If the power button featureis used, pressing he power button will send an interrupt to the processor allowing it toimplement a power down mode in an orderly fashion.

6.1.7 Power Rails

The Figure 11shows the connections of each of the rails to theTPS65217C.

VDD_3V3AUX

VDD_3V3AUX

C18

2.2uF,6.3VDGND

C9

10uF,10V

D1

LTST-C191TBKT

C12

10uF,10V

C11

10uF,10V

VDD_3V3A

R12

820,5%

1.5V

PWR_LEDR

C15

10uF,10V

DGND

C14

10uF,10VDGND

DGND

C16

2.2uF,6.3V

VDD_MPU

VDD_1V8

DGND

VDDS_DDR

VRTC

VDD_CORE

P_L1

VDCDC2

VDCDC1

P_L3

P_L2

VDCDC3

L3

LQM2HPN2R2MG0L

1 2

L2

LQM2HPN2R2MG0L

1 2

L1

LQM2HPN2R2MG0L

1 2

DGNDDGND

U2

TPS65217C

L120

VDCDC119

L223

VDCDC224

L331

VDCDC329

LDO340

LDO443

VLDO13

VLDO21

AGND

41

PGND

30

PPAD

49

C200.1uf,6.3V500mA

U4

TL5209

IN2

OUT3

GND15 EN1

ADJ4

GND36

GND27

GND48

VDD_3V3B

DGND DGNDDGNDDGND

SYS_5V

R10470K,1% R11280K,1%

DGND

DGND

C19470pF,6.3V

C17

2.2uF,6.3V

R60,1%

R50,1%

Figure 11. Power Rails


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6.1.7.1 VRTC RailThe VRTCrail is a 1.8V rail that is the first rail to come up in the power sequencing. Itprovides power to the RTC domain on the XAM3359ZCZprocessor and the I/O rail ofthe TPS65217C. It can deliver up to 250mA maximum.

6.1.7.2 VDD_3V3A RailThe VDD_3V3Arail is supplied by the TPS65217Cand provides the 3.3V for theprocessor rails and can provide up to 400mA.

6.1.7.3 VDD_3V3B RailThe current supplied by the VDD_3V3A rail is not sufficient to power all of the 3.3Vrails on the board. So a second LDO is supplied, U4, a TL5209A, which sources theVDD_3V3Brail. It is powered up just after the VDD_3V3Arail.

6.1.7.4 VDD_1V8 RailThe VDD_1V8 rail can deliver up to 400mA and provides the power required for the1.8V rails on the processor. This rail is not accessible for use anywhere else on the board.

6.1.7.5 VDD_CORE RailThe VDD_CORErail can deliver up to 1.2A at 1.1V. This rail is not accessible for use

anywhere else on the board and only connects to the processor. This rail is fixed at 1.1Vand is not scaled.

6.1.7.6 VDD_MPU RailThe VDD_MPUrail can deliver up to 1.2A. This rail is not accessible for use anywhereelse on the board and only connects to the processor. This rail defaults to 1.1V and can bescaled up to allow for higher frequency operation. Changing of the voltage is set via theI2C interface from the processor.

6.1.7.7 VDDS_DDR RailThe VDDS_DDRrail defaults to 1.5Vto support the DDR3 rails and can deliver up to1.2A. It is possible to adjust this voltage rail down to 1.35Vfor lower power operation ofthe DDR3L device. Only DDR3L devices can support this voltage setting of 1.35V.


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6.1.7.8 Power SequencingThe power up process is made up of several stages and events. Figure 12is the eventsthat make up the power up process for the system.

Figure 12. Power Sequencing

Figure 13 is the way the TPS65217C powers up and the voltages on each rail. Thepower sequencing starts at 15 and then goes to one. That is the way the TPS65217C isconfigured.

Figure 13. Power Sequencing


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6.1.8 Power LED

The power LED is a blue LED that will turn on once the TPS65217Chas finished thepower up procedure. If you ever see the LED flash once, that means that theTPS65217Cstarted the process and encountered an issue that caused it to shut down. The connection

of the LED is shown in Figure 8.

6.1.9 TPS65217C Power Up Process

Figure 14shows the interface between the TPS65217Cand the processor.

R16

100K,1%

DGND

U15

SN74LVC1G07DCK

A2

Y4

GND

3

VCC

5

NC

1

DGND

VRTCVDD_3V3A

C155

0.1uf,6.3V

DGND

R13 10K,1%

C23

0.1uf,6.3V

DGND

LDO_PGOOD 3

PORZ 3

VDD_3V3A

PMIC_POWR_EN4

U2

TPS65217C

PWR_EN9

SCL28

SDA27

PGOOD26

LDO_PGOOD46

WAKEUP13

INT45 WAKEUP 4I2C0_SCL4,10,11

I2C0_SDA4,10,11

R4

1.5K,5%

R3

1.5K,5%

VDD_3V3A

R1

100K,1%

PMIC_INT 3

Figure 14. Power Processor Interfaces

When voltage is applied, DC or USB, the TPS65217Cconnects the power to the SYSoutput pin which drives the switchers and LDOS in theTP65217C.

At power up all switchers and LDOs are off except for the VRTC LDO(1.8V), whichprovides power to the VRTC rail and controls the RTC_PORZ input pin to theprocessor, which starts the power up process of the processor. Once the RTC rail powersup, the RTC_PORZpin of the processor is released.

Once the RTC_PORZ reset is released, the processor starts the initialization process.After the RTC stabilizes, the processor launches the rest of the power up process byactivating the PMIC_PWR_ENsignal that is connected to the TPS65217Cwhich startsthe TPS65217Cpower up process.

The LDO_PGOOD signal is provided by the TPS65217C to the processor. As thissignal is 1.8V from the TPS65217Cby virtue of the TPS65217C VIO rail being set to


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1.8V, and the RTC_PORZsignal on the processor is 3.3V, a voltage level shifter,U4, isused. Once the LDOs and switchers are up on the TPS65217C, this signal goes activereleasing the processor. The LDOs on the TPS65217Care used to power the VRTC railon the processor.

6.1.10 Processor Control Interface

Figure 11above shows two interfaces between the processor and the TPS65217Cusedfor control after the power up sequence has completed.

The first is theI2C0bus. This allows the processor to turn on and off rails and to set thevoltage levels of each regulator to supports such things as voltage scaling.

The second is the interrupt signal. This allows the TPS65217C to alert the processorwhen there is an event, such as when the optional power button is pressed. The interruptis an open drain output which makes it easy to interface to 3.3V of the processor.

6.1.11 Low Power Mode Support

This section covers three general power down modes that are available. These modes areonly described form a Hardware perspective as it relates to the HW design.

6.1.11.1 RTC OnlyIn this mode all rails are turned off except the VDD_RTC. The processor will need toturn off all the rails to enter this mode. The VDD_RTC staying on will keep the RTC

active and provide for the wakeup interfaces to be active to respond to a wake up event.

6.1.11.2 RTC Plus DDRIn this mode all rails are turned off except the VDD_RTCand the VDDS_DDR, whichpowers the DDR3 memory. The processor will need to turn off all the rails to enter thismode. The VDD_RTCstaying on will keep the RTC active and provide for the wakeupinterfaces to be active to respond to a wake up event.

The VDDS_DDRrail to the DDR3 is provided by the 1.5V rail of theTPDS65217Candwith VDDS_DDR active, the DDR3 can be placed in a self refresh mode by the processorprior to power down which allows the memory data to be saved.

6.1.11.3 Voltage ScalingFor a mode where the lowest power is possible without going to sleep, this mode allowsthe voltage on the ARM processor to be lowered along with slowing the processor


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frequency down. The I2C0 bus is used to control the voltage scaling function in theTPS65217C.

6.2 XAM3359ZCZ Processor

The board is designed to use the AM3358 series processors in the 15 x 15 package. Theinitial units built will use the XAM3359AZC processor from TI. This is the sameprocessor as used on the original BeagleBone except for a different revision. Later, wewill switch to the AM338 device.

6.2.1 Description

Figure 15 is a high level block diagram of the processor. For more information on theprocessor, go to http://www.ti.com/product/am3358.

Figure 15. XAM3359 Block Diagram


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6.2.2 High Level Features

Table 4below shows a few of the high level features of the AM3358 processor.

Table 4. Processor Features

Operating SystemsLinux, Android, Windows

Embedded CEMMC/SD 3

Standby Power 7 mW CAN 2

ARM CPU 1 ARM Cortex-A8 UART (SCI) 6

ARM MHz (Max.) 275,500,600,800 ADC 8-ch 12-bit

ARM MIPS (Max.) 1000,1200,2000 PWM (Ch) 3

Graphics Acceleration 1 3D eCAP 3

Other HardwareAcceleration

2 PRU-ICSS,CryptoAccelerator

eQEP 3

On-Chip L1 Cache 64 KB (ARM Cortex-A8) RTC 1

On-Chip L2 Cache256 KB (ARM Cortex-A8)

I2C 3

Other On-Chip

Memory128 KB McASP 2

Display Options LCD SPI 2

General Purpose

Memory

1 16-bit (GPMC, NAND

flash, NOR Flash, SRAM)DMA (Ch) 64-Ch EDMA

DRAM1 16-bit (LPDDR-400,

DDR2-532, DDR3-606)IO Supply (V)

1.8V(ADC),3.3V

USB 2

Operating

Temperature

Range (C)

-40 to 90

6.2.3 Documentation

Full documentation for the XAM3359 processor can be found on the TI website athttp://www.ti.com/product/am3359. Make sure that you always use the latest datasheetsand Technical Reference Manuals (TRM).


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6.3 DDR3 Memory

The BeagleBone Black uses a single MT41K256M16HA-125 512MB DDR3L devicefrom Micron that interfaces to the processor over 16 data lines, 16 address lines, and 14control lines. The following sections provide more details on the design.

6.3.1 Memory Device

The design will support standard DDR3 and DDR3L x16 devices. A single x16 device isused on the board and there is no support for two x8 devices. The DDR3 devices work at1.5V and the DDR3 devices can work down to 1.35V to achieve lower power. Thespecific Micron device used is the MT41K256M16HA-125. It comes in a 96-BALLFBGA package with 0.8 mil pitch. Other standard DDR3 devices can also be supported,but the DDR3L is the lower power device and was chosen for its ability to work at 1.5Vor 1.35V. The standard frequency that the DDR3 is run at is 303MHZ.

6.3.2 DDR3 Memory Design

Figure 16is the schematic for the DDR3L memory device. Each of the groups of signalsis described in the following lines.

Address Lines:Provide the row address for ACTIVATE commands, and the columnaddress and auto precharge bit (A10) for READ/WRITE commands, to select onelocation out of the memory array in the respective bank. A10 sampled during aPRECHARGE command determines whether the PRECHARGE applies to one bank(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs alsoprovide the op-code during a LOAD MODE command. Address inputs are referenced to

VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled duringREAD and WRITE commands to determine whether burst chop (on-the-fly) will beperformed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).

Bank Address Lines: BA[2:0] define the bank to which an ACTIVATE, READ,WRITE, or PRECHARGE command is being applied. BA[2:0] define which moderegister (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.BA[2:0] are referenced to VREFCA.

CK and CK# Lines: are differential clock inputs. All address and control input signalsare sampled on the crossing of the positive edge of CK and the negative edge of CK#.

Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

Clock Enable Line:CKE enables (registered HIGH) and disables (registered LOW)internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabledis dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKELOW provides PRECHARGE power-down and SELF REFRESH operations (all banksidle) or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit.


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Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH.CKE is referenced to VREFCA.

DDR_CKE3DDR_CLKn3DDR_CLK3

DDR_WEn3DDR_CASn3DDR_RASn3DDR_CSn3

DDR_RESETn3

C124

0.1uf,6.3V

DDR_DQM03DDR_DQM13

R9710K,1%

R9610K,1%

R10010K,1%

R99240E

R9810K,1%

C123

0.001uf,50V

DDR_ODT

U12

MT41K256M16HA-125

CKJ7

CKnK7

CKEK9

CSnL2

RASnJ3

CASnK3

WEnL3

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10L7

A11R7

A12N7

A13T3

A14T7

BA0M2

BA1N8

BA2M3

DQ0E3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

ODTK1

VSS1A9

VSS2B3

VSS3E1

VSS4G8

VSSQ4D8VSSQ3D1VSSQ2B9VSSQ1B1

VSSQ5E2

VDDQ1A1

VDDQ2A8

VDDQ3C1

VDDQ4C9

VDDQ5D2

VDD1B2

VDD2G7

UDQSnB7

UDMD3

LDME7

LDQSnG3

UDQSC7

LDQSF3

DQ8D7

DQ10C8

DQ11C2

DQ14B8

DQ12

A7

DQ15A3

DQ13A2

VDD9D9

VSSQ6E8

VDDQ7E9

VDDQ8F1

VSSQ7F9

VSSQ8G1

VSSQ9G9

VREF_DQH1

VDDQ9H2

VDDQ10H9

NC1J1

NC2J9

VSS5J2

VSS6J8

VDD4K2

VDD5K8

NC3L1

ZQL8

NC4L9

VSS7M1

NC5M7

VREF_CAM8

VSS8M9

VDD6N1

VDD7N9

VSS9P1

VSS10P9

VDD8R1

VDD3R9

VSS11T1

RESET#T2

VSS12T9

DQ9C3

VDDS_DDR

DGND

DGND

DGND

DDR_D10DDR_D11

VDDS_DDR

DDR_D8

DDR_D15

DDR_D13DDR_D14

DDR_D9

VDDS_DDR

DGND

DDR_D12

DGND

DDR_ODT 3

VDDS_DDR

DDR_DQS03

DDR_DQSN03

DDR_D1DDR_D2DDR_D3

DDR_DQSN13DDR_DQS13

DDR_D4

DDR_D0

DDR_D7

DDR_D5DDR_D6

DDR_A1

DDR_A3

DDR_A[14..0] 3

DDR_BA[2..0] 3

DDR_A6

DDR_A2

DDR_A8DDR_A9

DDR_A4

DDR_A0

DDR_D[15..0]3 DDR_A7

DDR_A13DDR_A14

DDR_A10

DDR_A5

DDR3 SDRAM

DDR_BA1DDR_BA2

DDR_BA0

DDR_A11DDR_A12

DDR_A[14..0]

DDR_BA[2..0]

Figure 16. DDR3 Memory Design

Chip Select Line:CS# enables (registered LOW) and disables (registered HIGH) thecommand decoder. All commands are masked when CS# is registered HIGH. CS#provides for external rank selection on systems with multiple ranks. CS# is consideredpart of the command code. CS# is referenced to VREFCA.


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Input Data Mask Line:DM is an input mask signal for write data. Input data is maskedwhen DM is sampled HIGH along with the input data during a write access. Although theDM ball is input-only, the DM loading is designed to match that of the DQ and DQSballs. DM is referenced to VREFDQ.

On-die Termination Line:ODT enables (registered HIGH) and disables (registeredLOW) termination resistance internal to the DDR3 SDRAM. When enabled in normaloperation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, andDM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored ifdisabled via the LOAD MODE command. ODT is referenced to VREFCA.

6.3.3 Power Rails

The DDR3Lmemory device and the DDR3 rails on the processor are supplied by the

TPS65217C. Default voltage is 1.5V but can be scaled down to 1.35V if desired.

6.3.4 VREF

The VREF signal is generated from a voltage divider on the VDDS_DDR rail thatpowers the processor DDR rail and the DDR3L device itself. Figure 17below shows theconfiguration of this signal and the connection to the DDDR3 memory device and theprocessor.

U12

MT41K256M16HA-125

VREF_DQH1

VREF_CAM8

15mm x 15mm Package

U5A

XAM3359AZCZ

VREFSSTLJ4

C124

0.1uf ,6.3V

R10010K,1%

R9810K,1%

C123

0.001uf,50V

DGND

DDR_VREF

VDDS_DDR

DGND

DGND

C28

0.1uf,6.3V

DDR_VREF

Figure 17. DDR3 VREF Design


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6.4 eMMC Memory

The eMMC is a communication and mass data storage device that includes a Multi-MediaCard (MMC) interface, a NAND Flash component, and a controller on anadvanced 11-signal bus, which is compliant with the MMC system specification. The

nonvolatile eMMC draws no power to maintain stored data, delivers high performanceacross a wide range of operating temperatures, and resists shock and vibration disruption.

One of the issues faced with SD cards is that across the different brands and even withinthe same brand, performance can vary. Cards use different controllers and differentmemories, all of which can have bad locations that the controller handles, but thecontroller may be optimized for reads or writes. You never know what you will begetting. This can lead to varying rates of performance. The eMMC card is a knowncontroller and when coupled with the 8bit mode, 8 bits of data instead of 4, you getdouble the performance which should result in quicker boot times.

The following sections describe the design and device that is used on the BeagleBoneBlack to implement this interface.

6.4.1 eMMC Device

The device used in a Micron MTFC2GMTEA-0F_WT 2GB eMMC device. This is anew device and so for documentation and support, you will need to contact your localMicron representative.

The package is a 153 ball WFBGA device. The footprint on the BeagleBone Black for

this device supports 4GB and 8GB devices. As this is a JEDEC standard, there are othersuppliers that may work in this design as well. The only device that has been tested is theMTFC2GMTEA-0F_WT.

6.4.2 eMMC Circuit Design

Figure 18 is the design of the eMMC circuitry. The eMMC device is connected to theMMC1 port on the processor. MMC0 is still used for the uSD card as is currently done onthe original BeagleBone.

The device runs at 3.3V both internally and the external I/O rails. The VCCI is aninternal voltage rail to the device. The manufacturer recommends that a 1uf capacitor beattached to this rail, but a 2.2uF was chosen to provide a little margin.

Pullup resistors are used to increase the rise time on the signals to compensate for anycapacitance on the board.


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DGND

VDD_3V3B

C125

2.2uF,6.3V

DGND

R101

10K,1%

R102

10K,1%

R104

10K,1%

R103

10K,1%

VDD_3V3B

R105

10K,1%

R106

10K,1%

R107

10K,1%

R108

10K,1%

R109

10K,1%

R110

10K,1%

U13

MEM_MNAND_2GB

DAT0A3

DAT1A4

DAT2A5

DAT3B2

DAT4B3

DAT5B4

DAT6B5

DAT7B6

VCCI

C2

VSSQ4

C4

VCCQ4

C6

VCC3

E6

VSS2

E7

VSS5

N5

VCC2

F5

VSS1

G5

VSS3

H10

VSS4

K8

VCC1

K9

VCCQ5

M4

CMDM5

CLKM6

VSSQ1

N2

VCCQ3

N4

VCCQ1

P3

VSSQ3

P4

VCCQ2

P5

VSSQ2

P6

RSTK5

VCC0

J10

R111

10K,1%

U5A

AM3358_ZCZ

MMC1_CLKU9MMC1_CMDV9

MMC1_DAT0U7

MMC1_DAT1V7

MMC1_DAT2R8

MMC1_DAT3T8

MMC1_DAT4U8

MMC1_DAT5V8

MMC1_DAT6R9

MMC1_DAT7T9

GPIO2_0T13 R162

0,1%,DNI

Figure 18. eMMC Memory Design

The pins used by the eMMC1 in the boot mode are listed below inTable 5.

Table 5. eMMC Boot Pins

For eMMC devices the ROM will only support raw mode. The ROM Code reads out rawsectors from image or the booting file within the file system and boots from it. In rawmode the booting image can be located at one of the four consecutive locations in themain area: offset 0x0 / 0x20000 (128 KB) / 0x40000 (256 KB) / 0x60000 (384 KB). Forthis reason, a booting image shall not exceed 128KB in size. However it is possible toflash a device with an image greater than 128KB starting at one of the aforementionedlocations. Therefore the ROM Code does not check the image size. The only drawback isthat the image will cross the subsequent image boundary. The raw mode is detected byreading sectors #0, #256, #512, #768. The content of these sectors is then verified forpresence of a TOC structure. In the case of a GP Device, a Configuration Header (CH)mustbe located in the first sector followed by a GP header. The CH might be void (only

containing a CHSETTINGS item for which the Valid field is zero).

The ROM only supports the 4-bit mode. After the initial boot, the switch can be made to8-bit mode for increasing the overall performance of the eMMC interface.


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6.5 Micro Secure Digital

The uSD connector on the board will support a uSD card that can be used for booting orfile storage on the BeagleBone Black.

6.5.1 uSD Design

Figure 19below is the design of the uSD interface.

U5A

AM3358_ZCZ

MMC0_CLKG17

MMC0_CMDG18

MMC0_DAT0G16

MMC0_DAT1G15

MMC0_DAT2F18

MMC0_DAT3F17

MMC0_SDCDC15

DGND

SD_CD

DGND

R150

1

0K,1%

R153

1

0K,1%

R151

1

0K,1%

R157 10K,1%

R152

1

0K,1%

R154

1

0K,1%

R155

1

0K,1%

VDD_3V3B

VDD_3V3B

DGND

C153

10uF,10V

microSD

P7

MOLEX 502570-001

DAT21

CD/DAT32

CMD3

VDD4

CLOCK5

VSS6

DAT07

DAT18

GND9

GND110

CD11

GND212

GND313

GND414

C154

0.1uf,6.3V

Figure 19. uSD Design

The signalsMMC0-3are the data lines for the transfer of data between the processor andthe uSD connector.

The MMC0_CLKsignal clocks the data in and out of the uSD card.

The MMCO_CMDsignal indicates that a command versus data is being sent.

There is no separate card detect pin in the uSD specification. It uses MMCO_DAT3forthat function. However, most uSD connectors still supply a CD function on theconnectors. In the BeagleBone Black design, this pin is connected to the MMC0_SDCDpin for use by the processor. You can also change the pin to GPIO0_6, which is able towake up the processor from a sleep mode when an SD card is inserted into the connector.

Pullup resistors are provided on the signals to increase the rise times of the signals toovercome PCB capacitance.

Power is provided from the VDD_3V3B rail and a 10uf capacitor is provided forfiltering.


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6.6 User LEDs

There are four user LEDs on the BeagleBone Black. These are connected to GPIO pinson the processor. Figure 20shows the interfaces for the user LEDs.

R76100K,1%

R77100K,1%

D2 LTST-C191TBKT

DGNDDGND

47k

10

kQ1A

DMC56404

1

6

247k

10k Q1B

DMC56404

4

3

5

DGNDDGND

USR13

USR03

LEDAC

LEDBC

USR0

R73820,5%

R72820,5%

LEDAA

LEDBA

SYS_5V

D 3 LTST-C 191TBKT D 4 LTST-C 191TBKT D5 LTST- C191TBKT

R78100K,1% R79

100K,1%

DGND

47k

10k Q2A

DMC56404

1

6

2

47k

10k Q2B

DMC56404

4

3

5

DGND

USR23

DGNDDGND

USR33

USR1

LEDDC

LEDCC USR3

USR2

R74820,5%L

EDCA

LEDDA

R71820,5%

Figure 20. User LEDs

6.7 Boot Configuration

The design supports two groups of boot options on the board. The user can switchbetween these modes via the Boot button. The primary boot source is the onboard eMMcdevice. By holding the Boot button, the user can force the board to boot from the uSDslot. This enables the eMMC to be overwritten when needed or to just boot an alternateimage. The following sections describe how the boot configuration works.

6.7.1 Boot Configuration Design

Figure 21 shows the circuitry that is involved in the boot configuration process. On

power up, these pins are read by the processor to determine the boot order. S2 is used tochange the level of one bit from Hi to LO which changes the boot order.


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R80

100K,1%

R83

100K,1%

R84

100K,1%

R85

100K,1%

R87

100K,1%

R86

100K,1%

R89

100K,1%

R88

100K,1%

R82

100K,1%

R95

100K,1%

uSD BOOT

VDD_3V3A

SYS_BOOT10SYS_BOOT9SYS_BOOT8

SYS_BOOT15SYS_BOOT14SYS_BOOT13SYS_BOOT12SYS_BOOT11

SYS_BOOT4



SYS_BOOT3

DGND

LCD_DATA5 4,10,11LCD_DATA4 4,10,11LCD_DATA3 4,10,11

R65

1

00K,1%




LCD_DATA1 4,10,11LCD_DATA0 4,10,11

LCD_DATA15 4,10,11

LCD_DATA2 4,10,11

R69

1

00K,1%,DNI

R93

100K,1%,DNI

R92

100K,1%,DNI

S2KMR231GLFS

1 3

2 4

R68

1

00K,1%

R91

100K,1%,DNI

DGND

R90

100K,1%,DNI

R64

1

00K,1%,DNI

R75 100

R70

1

00K,1%,DNI

R63

1

00K,1%,DNI

R56

1

00K,1%

R67

1

00K,1%

R66

1

00K,1%

R62

1

00K,1%,DNI

R61

1

00K,1%,DNI

R60

1

00K,1%,DNI

R94

100K,1%

R59

1

00K,1%,DNI

R58

1

00K,1%,DNI

R57

1

00K,1%,DNI

R81

100K,1%,DNI

R55

1

00K,1%,DNI

Figure 21. Processor Boot Configuration Design

It is possible to override these setting via the expansion headers. But be careful not to add toomuch load such that it could interfere with the operation of the HDMI interface or LCD panels.

6.7.2 Boot Options

Based on the selected option found inFigure 19below, each of the boot sequences foreach of the two settings is shown.

Figure 22. Processor Boot Configuration

The first row in Figure 22is the default setting. On boot, the processor will look for theeMMC on the MMC1 port first, followed by USB0 and UART0. In the event there is nouSD card and the eMMC is empty, UART0 or USB0 could be used as the board source.


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If you have a uSD card from which you need to boot from, hold the boot button down.On boot, the processor will look for the SPIO0 port first, then uSD on the MMC0 port,followed by USB0 and UART0. In the event there is no uSD card and the eMMC isempty, USB0 or UART0 could be used as the board source.

6.8 10/100 Ethernet

The BeagleBone Black is equipped with a 10/100 Ethernet interface. It uses the samePHY as is used on the original BeagleBone. The design is described in the followingsections.

6.8.1 Ethernet Processor Interface

Figure 23shows the connections between the processor and the PHY. The interface is inthe MII mode of operation.

RXER/PHYAD0

RXD1/MODE1RXD0/MODE0

CRS

R 131 100, 1%R 133 100, 1%

R129 100,1%

R 139 100, 1%

R 125 100, 1%R 126 100, 1%

R 138 100, 1%

R119

1.5K,5%

R 128 100, 1%R 127 100, 1%

R134 100, 1%

VDD_3V3B

RXD3/PHYAD2RXD2/RMIISEL

MODE2

TXCLK

REFCLKORXDV

U14

LAN8710A

QFN32_5X5MM_EP3P3MM

MDIO16

MDC17

RXD3/PHYAD28

RXD2/RMIISEL9

RXD1/MODE110

RXD0/MODE011

RXDV26

RXCLK/PHYAD17

RXER/RXD4/PHYAD013

TXCLK20

TXEN

21

TXD022

TXD123

TXD224

TXD325

COL/CRS_DV/MODE215

CRS14

U5B

AM3358_ZCZ

GMII1_CRSH17

GMII1_TXD0 K17

GMII1_TXD1K16

GMII1_TXD2K15

GMII1_TXD3J18

GMII1_TXCLKK18

GMII1_TXEN

J16

GMII1_RXERRJ15

GMII1_RXDVJ17

GMII1_RXCLKL18

GMII1_RXD0M16GMII1_RXD1L15GMII1_RXD2L16GMII1_RXD3L17MDIO_CLKM18MDIO_DATAM17

GMII1_COLH16

Figure 23. Ethernet Processor Interface


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6.8.2 Ethernet Connector Interface

The off board side of the PHY connections are shown inFigure 24below.

ACTIVE W HEN AT 100MB

ACTIVE W HEN LINK PRESENT.BLINKS OFF DURING ACTIVITY.

GRN_C

ETH_TXD4

TXNTXP

TCT_RCT

RXPRXN

RBIAS

ESD_RING

C138

15pF,DNI

C139

15pF,DNIU14

LAN8710A

QFN32_5X5MM_EP3P3MM

RBIAS32

RXP31

RXN30

TXN28TXP29

nINT/TXER/TXD418

LED2/nINTSEL2LED1/REGOFF3

R1370,1%

C140

15pF,DNI

R136

.1,0805C141

0.022uF,10V

R13510K,1%

R14510K,1%

R120

49.9,1%

R130 470,5%

R132 470,5%

P5

WE_7499010211A

TCT5

TD+3

TD-6

RD+1

RD-2

RCT4

YELC11

YELA12

GRNC10

GRNA9

GND8

SHD113

SHD214

NC7

R121

49.9,1%

R122

49.9,1%

R14412.1K,1%

R123

49.9,1%

C137

15pF,DNI

VDD_PHYA

DGND

DGND

DGND

DGND

VDD_PHYA

D GN D D GN DD GN D DGN D

DGND

DGND

DGND

YELA

GRNA

YEL_C

Figure 24. Ethernet Connector Interface


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6.8.3 Ethernet PHY Power, Reset, and Clocks

Figure 25show the power, reset, and lock connections to theLAN8710APHY. Each ofthese areas is discussed in more detail in the following sections.

PHY_VDDCR

PHY_XTAL2

PHY_XTAL1

PHYX

REFCLKO

C1350.1uf,6.3V

C1310.1uf,6.3V

C1320.1uf,6.3V

R 131 100, 1%

R142 0,1%

FB4150OHM800mA

1 2

R14310,1%

C143

30pF,50V

U14

LAN8710A

nRST19

XTAL1/CLKIN5

XTAL24

GND_

EP

33

VDDIO

12

VDD1A

27

VDD2A

1

VDDCR

6

RXCLK/PHYAD17

R140 0,1%,DNI

C1341uF,10V

C142

30pF,50V

Y3

25.000MHzXTAL150SMD_125X196

12

C136470pF,6.3V

R12 4 10,1%,DNI

R1411M,1%,DNI

DGND

VDD_PHYA

VDD_3V3B

DGND

DGND

DGNDDGND

DGND

DGND

DGND

SYS_RESETn3,11

RMII1_REFCLK4

C133

10uF,10V

RCLKIN

Figure 25. Ethernet PHY, Power, Reset, and Clocks

6.8.3.1 VDD_3V3B RailThe VDD_3V3B rail is the main power rail for the LAN8710A. It originates at theVD_3V3B regulator and is the primary rail that supports all of the peripherals on theboard. This rail also supplies the VDDIO rails which set the voltage levels for all of theI/O signals between the processor and the LAN8710A.

6.8.3.2 VDD_PHYA RailA filtered version of VDD_3V3B rail is connected to the VDD rails of the LAN8710 andthe termination resistors on the Ethernet signals. It is labeled as VDD_PHYA. Thefiltering inductor helps block transients that may be seen on the VDD_3V3B rail.


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6.8.3.3 PHY_VDDCR RailThe PHY_VDDCRrail originates inside the LAN8710A. Filter and bypass capacitorsare used to filter the rail. Only circuitry inside the LAN8710A uses this rail.

6.8.3.4 SYS_RESETThe reset of the LAN8710A is controlled via theSYS_RESETnsignal, the main boardreset line.

6.8.3.5 Clock SignalsA crystal is used to create the clock for the LAN8710A. The processor uses theRMII_RXCLKsignal to provide the clocking for the data between the processor and theLAN8710A.

6.8.4 LAN8710A Mode Pins

There are mode pins on the LAN8710A that sets the operational mode for the PHY whencoming out of reset. These signals are also used to communicate between the processorand the LAN8710A. As a result, these signals can be driven by the processor which cancause the PHY not to be initiated correctly. To insure that this does not happen, three lowvalue pull up resistors are used. Figure 26below shows the three mode pin resistors.

MODE2

RXD1/MODE1

RXD0/MODE0

R114

1.5K,1%

R112

1.5K,1%

R113

1.5K,1%

VDD_3V3B

Figure 26. Ethernet PHY Mode Pins

This will set the mode to be 111, which enables all modes and enables auto-negotiation.

6.9 HDMI Interface

The BeagleBone Black has an onboard HDMI framer that converts the LCD signals andaudio signals to drive a HDMI monitor. The design uses an NXP TDA199988HDMIFramer.


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The following sections provide more detail into the design of this interface.

6.9.1 HDMI Framer

The TDA19988is a High-Definition Multimedia Interface (HDMI) 1.4a transmitter. It isbackward compatible DVI 1.0 and can be connected to any DVI 1.0 or HDMI sink. TheHDCP mode is not used in the design. The non-HDCP version of the device is used in theBeagleBone Black design.

This device provides additional embedded features like CEC (Consumer ElectronicControl). CEC is a single bidirectional bus that transmits CEC over the home appliancenetwork connected through this bus. This eliminates the need of any additional device tohandle this feature. While this feature is supported in this device, as of this point, the SWto support this feature has not been implemented and Is not a feature that is consideredcritical.

It can be switched to very low power Standby or Sleep modes to save power when HDMIis not used. TDA19988 embeds I2C-bus master interface for DDC-bus communication toread EDID. This device can be controlled or configured via I2C-bus interface.

6.9.2 HDMI Video Processor Interface

The Figure 27 shows the connections between the processor and the HDMI framerdevice. There are 16 bits of display data, 5-6-5 that is used to drive the framer. Thereason for 16 bits I stat allows for compatibility with display and LCD capes already

available on the original BeagleBone. The unused bits on the TDA19988 are tied low. Inaddition to the data signals are the VSYNC, HSYNC, DE, and PCLK signals that roundout the video interface from the processor.

6.9.3 HDMI Control Processor Interface

In order to use the TDA19988, the processor needs to setup the device. This is done viathe I2C interface between the processor and the TDA19988. There are two signals on theTDA19988 that could be used to set the address of the TDA19988. In this design they areboth tied low. The I2C interface supports both 400kHz and 100KhZ operation.Table 6shows the I2C address.

Table 6. TDA19988 I2C Address


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DATA_OUT

WORD_SYNC

SCLK

DGND

U5B

AM3358_ZCZ

LCD_DATA0R1

LCD_DATA1R2

LCD_DATA2R3

LCD_DATA3R4

LCD_DATA4T1

LCD_DATA5T2

LCD_DATA6T3

LCD_DATA7T4

LCD_DATA8U1

LCD_DATA9U2

LCD_DATA10U3

LCD_DATA11U4

LCD_DATA12V2

LCD_DATA13V3

LCD_DATA14V4

LCD_DATA15T5

LCD_PCLKV5

LCD_VSYNCU5

LCD_HSYNCR5

LCD_AC_BIAS_ENR6

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Beaglebone Black Reference Menu