BCA 2050 Computer Organization Model Question Paper

8/17/2019 BCA 2050 Computer Organization Model Question Paper

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Model Question Paper

Subject Code: BCA 2050 Book ID: B1642Subject Name: Computer Organization

Credits: 4 Marks: 140

Part A (Descriptive questions) (4*10 = 40 marks)

1. What is RAID technology? What are its most commonly used levels? [10 marks]

2. A) Discuss the three types of contentions in a multiprocessor system. [5 marks]

B) What are the different techniques used for reducing contention? [5marks]

3. A) Define the basic elements of the processor. [4 marks]

B) Describe the micro-operations that the processor performs. [6marks]

4. A) Discuss the different types of mapping functions. [5 marks]

B) Describe the various replacement algorithms in detail. [5 marks]

Part B (One mark questions) (50*1 = 50 marks)

1. A ............... is a processor designed with complete computer instruction set to provide

maximum capabilities in the most efficient way.

a. UMA b. NUMA

c. RISC

d. CISC

2. Which of the following is not an approach to enhance the vector-processing capability?

a. Using a vectorizing compiler

b. Choosing suitable algorithmsc. Combining scalar instructions

d. Diluting the vector instruction set

3. Conventional CISC architecture uses a ............. for holding both instructions and data.

a. Unified cache


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b. Unified register

c. Varied cache

d. Varied register

4. Which of the following is not a technique for reducing contention?

a. Better interconnection network b. Cache memory

c. Read-only memory

d. Memory allocation

5. Coprocessors are capable of enhancing the system performance by relieving the main

processor of ................ tasks.

a. Data-intensive

b. Processor-intensivec. Function-intensive

d. Operation-intensive

6. Attaching a separate cache memory to each processor in a multiprocessor system may help in

.............. the memory traffic.

a. Scanning b. Maintaining

c. Reducing

d. Increasing

7. In ............., all I/O is performed under the control of an “I/O handling procedure.’’

a. I/O Bus

b. I/O Interfacesc. Serial I/Od. Program-controlled I/O

8. There are three kinds of the ................ mode, that is, Mode 0, 1, and 2.a. Single-cycle

b. Burst

c. Bit set/resetd. Input/output

9. The PCI bus utilizes its internal ................ system for handling requests from the cards on the

bus.a. Processing

b. Memory

c. Database

d. Interrupt


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10. ................... is a removable cartridge storage device that may be used to store compressed

data.

a. DVD drive b. Zip drive

c. CD-ROM

d. CD-RW

11. The technique of ................. has improved the fidelity of the recorded audio signal by

increasing the effective linearity of the recording medium.

a. AC biasing b. DC biasing

c. Compact cassettes

d. Digital audio tape

12. .............. is now used as an umbrella term for computer data storage schemes that can divide

and replicate data among multiple physical drives.a. CRT b. DDC

c. DAT

d. RAID

13. In ............., whole capacity needs to be erased by ultraviolet radiation before a new

programming activity.a. ROM

b. DRAM

c. EPROM

d. SRAM

14. A priority is given to the ................ over the CPU bus to ensure that no information is lost,

during simultaneous requests.a. Read/write circuits

b. Refresh

c. Sense/write circuit

d. Decoder block

15. In a/an ................, information decays naturally or is lost when electrical power is switched

off.

a. Erasable memory b. Volatile memory

c. Non-volatile memory

d. Non-erasable memory

16. ................ are those registers that may seem like operands of the logical, arithmetic, and

associated instructions.


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a. Flag registers

b. Index registers

c. Segment registersd. General purpose registers

17. The ax register is known as the ............... .a. Base register

b. Accumulator

c. Count register

d. Data register

18. The .............. saves the physical memory address on which the subsequent instruction is

placed or on which the subsequent piece of data will be written.

a. Memory Data Register b. Memory Address Register

c. Program Counterd. Operand

19. IEEE 754-1985 was an industry standard for representing .............. numbers in computers,

officially adopted in 1985 and superseded in 2008 by IEEE 754-2008.a. Normalized

b. Mantissa

c. Exponentd. Floating-point

20. A floating-point number is said to be normalized if the most significant digit of the mantissa

is ............ .a. One

b. Zero

c. Nonzerod. Three

21. The ones' complement form of a negative binary number is the bitwise ............ applied to it.

a. NOT b. OR

c. AND

d. NOR

22. The ............... was designed to calculate the entries of a table automatically and transfer them

through steel punches to an engineer ’s plate from which the tables could be printed.

a. Analytical engine

b. Difference enginec. EDVAC

d. UNIVAC


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23. The ............... corresponds to a modern Arithmetic Logic Unit. It was capable of performing

four basic arithmetic operations.a. Variable card

b. 90 Operation card

c. Stored. Mill

24. ............. provide/provides a means of communication among the control unit, ALU, and

registers of the CPU.a. Arithmetic Logic Unit

b. Control Unit

c. CPU interconnections

d. Registers

25. ................ are small, simple devices that are often used to control other devices.a. Embedded computers b. Supercomputers

c. Laptop computers

d. Electronic computers

26. Which of the following is not a fundamental design issue in designing an instruction set?

a. Registers b. Logical Data

c. Data Types

d. Operation Repertoire

27. Which of the following factors does not determine the use of addressing bits?

a. Number of register sets

b. Register versus address rangec. Number of operands

d. Number of addressing modes

28. ............. are a straight forward, simple binary representation.a. Decimals

b. Floating-point numbers

c. Unsigned integers

d. Signed integers

29. ............... is concerned with addresses that refer to the memory other than registers.

a. Operand b. Register set

c. Address range

d. Address granularity


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30. The ............... occurs at the beginning of every instruction.

a. Fetch cycle b. Instruction cycle

c. Execute cycle

d. Indirect cycle

31. ................ is a sequence of control words corresponding to the control sequence of a machine

instruction that constitute the micro routine for that instruction.

a. Micro program Counter b. Micro program Memory

c. Micro Routine

d. Control Word

32. At the beginning of the fetch cycle, the address of the next instruction is in the ................ .

a. Control Word b. Program counterc. Memory Buffer Register

d. Memory Address Register

33. In a hardwired implementation, the control unit is essentially a/an ............. circuit.

a. Combinatorial

b. Closedc. Open

d. Effective

34. Which of the following is not a mapping function?a. Indirect mapping

b. Set associative Mapping

c. Associative Mappingd. Direct Mapping

35. When a block is to be overwritten, the block that has not been referenced for the longest time

is overwritten. This is called .................. block.a. Random

b. FIFO

c. Least-recently-used

d. Least-frequently-used

36. Transferring data in blocks between the main memory and the ............... enables an

interleaved memory to operate at its maximum possible speed.a. Erasable memory

b. Volatile memory

c. Secondary memory


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d. Cache memory

37. ................ is a compromise that exhibits the strengths of both the direct and associativeapproaches while reducing their disadvantages.

a. Dissociative Mapping

b. Direct Mappingc. Set associative Mapping

d. Associative Mapping

38. With ................., the CPU issues a command to I/O module, and it does not wait until I/Ooperation gets completed but instead continues to execute other instructions.

a. Interrupt-driven I/O

b. Controller

c. Channel or I/O processord. Programmed I/O

39. A ............... causes the I/O module to obtain an item of data from the peripheral and place itin an internal buffer.

a. Control command

b. Test commandc. Write command

d. Read command

40. The Testbit instruction tests the state of one bit in the destination location, where the bit

position to be tested is indicated by the ............ operand.

a. Fourth

b. Thirdc. Second

d. First

41. Peripherals often use different data formats and ................ from the computer system to

which they are attached.

a. Data type b. Volume

c. Word lengths

d. Data lengths

42. Name the printer that uses impact technology.

a. Thermal Printer

b. Chain Printerc. Laser Printer

d. Ink-jet Printer


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43. ............... allow you to scan photographic slides, which are small and need higher scanning

resolutions than images and documents.

a. Flatbed scanners b. Drum scanners

c. Film scanners

d. Photo scanners

44. ................ depicts the distance between pixels.

a. Scale pitch

b. Point pitchc. Parallel pitch

d. Dot pitch

45. The peripheral increases the computer's capability to interact with the ........... .a. Processor

b. Userc. Hardwared. Software

46. ................ is read-only in nature because it consists of micro programs that are written andstored into it permanently.

a. Main Memory

b. Control memoryc. Cache Memory

d. Secondary Memory

47. The control signals happen to be fully encoded in the control word in ............ microcode.a. Cross

b. Parallel

c. Fully horizontald. Fully vertical

48. Once the control unit tracks the op-code of the current instruction from the IR, it sends it to

the address bus of that .............. .a. MPC

b. CU

c. RAM

d. ROM

49. The ............. technique of the CU determines which circuit to utilize for the current

instruction.a. Programming

b. Decoding

c. Communication


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d. Encoding

50. Electronic data communications between elements can be broadly classified into twocategories: single-ended and ............... .

a. Differential

b. Integratedc. Open-ended

d. Double-ended

Part B (Two marks questions) (25*2 = 50 marks)

51. In ................, a set of ................ simultaneously execute different instruction sequences on different

data sets.

a. SISD stream, processors b. SIMD stream, machine instructions

c. MIMD stream, processors

d. MISD stream, machine instructions

52. To achieve higher performance, superscalar processors have introduced intricate instruction issue

policies, involving advanced techniques, such as .............., .................., and speculative branch

processing.

a. Decoding, memory renaming

b. Decoding, register renaming

c. Shelving, memory renaming

d. Shelving, register renaming

53. The contention ratio in computer networking refers to the ratio of the probable .............. to the

............. .

a. Minimum demand, virtual band width

b. Minimum demand, real band width

c. Maximum demand, virtual band width

d. Maximum demand, real band width

54. Various types of operations that may be performed by the coprocessor are floating-point arithmetic,

signal processing, ..............., and ............... .

a. String processing, encryption

b. String processing, decryption

c. Data processing, encryption


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d. Data processing, decryption

55. Several techniques are used for SCSI bus termination. These are ............. termination, Low Voltage

Differential (LVD) termination, High Voltage Differential (HVD) termination, and ................ .

a. Forced imperfect, direct termination

b. Forced imperfect, direct termination

c. Forced perfect, active termination

d. Forced perfect, direct termination

56. A bus is ................ when data transfer on the bus depends upon the accessibility of the data and not on

............ signal.

a. Synchronous, clock

b. Synchronous, outputc. Asynchronous, clock

d. Asynchronous, output

57. Consider the following statements about RAID 0:

(i) Any drive failure destroys the array, and the likelihood of failure increases with no drives in the array.

(ii) A single drive failure destroys the entire array, because when data is written to a RAID 0 volume, the

data is broken into fragments called blocks.

State True or False.

a. (i) True, (ii) False

b. (i) True, (ii) True

c. (i) False, (ii) False

d. (i) False, (ii) True

58. ............ is identical to ............. but confines all parity data to a single drive.

a. RAID 2, RAID 3

b. RAID 3, RAID 4c. RAID 4, RAID 5

d. RAID 5, RAID 6

59. Consider the following statements about the operations of the control circuitry for a memory read

cycle:


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(i) The timing and control circuit sends a busy signal to prevent the access control box from accepting the

new requests until the current cycle starts.

(ii) The timing and control block then loads the row and column address into the memory chips by

activating RAS and CAS.


a. (i) True, (ii) True

b. (i) False, (ii) False

c. (i) False, (ii) True

d. (i) True, (ii) False

60. Consider the following statements about DRAM chips:

i. A DRAM memory cell uses multiple transistors and a capacitor to store a bit of data.

ii. In a DRAM cell, the ‘1’ and ‘0’ states correspond to the presence of a stored charge in a capacitor

controlled by the transistor switching circuit.



b. (i) True, (ii) False



61. When the instruction contains a/an ............... address, the actual address is read from the main

memory, any needed data is obtained from the main memory and thereafter positioned in the .............. .

a. Direct, program counter

b. Indirect, program counter

c. Indirect, data registers

d. Direct, data registers

62. Which of the following statements are true about the functions of flag registers?

i. Carry Flag (CF): As soon as there is an unsigned overflow, it is positioned to 1.

ii. Parity Flag (PF): As soon as there exists even number of 1 bits in the outcome, as well as to 0 at

the time there exists odd number of 1 bits, it is positioned to 1.



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63. Consider the following statements about numbers:

i. Floating point describes a method of representing whole numbers in a way that can support a

wide range of values.

ii. Numbers are, in general, represented approximately to a fixed number of significant digits and

scaled using an exponent.






64. Modern CPUs are typically .............. or .............. machines.

a. 2-operand, 3-operand

b. 4-operand, 5-operand

c. 3-operand, 4-operand

d. 1-operand, 2-operand

65. ............... refers to a set of CPU registers. These serve as a working memory, storing ............. results

during the computation process.

a. Internal memory, temporary b. Secondary memory, permanent

c. Internal memory, permanent

d. Secondary memory, temporary


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66. CPU contains one or more registers that may be referenced by ................. . If only ................. register

exists, reference to it may be implicit.

a. Instruction format, two

b. Instruction format, one

c. Machine instructions, two

d. Machine instructions, one

67. The instruction is divided into ............., corresponding to the constituent elements of the instruction.

This layout of the instruction is called ............... .

a. Operation codes, instruction format

b. Operation codes, mnemonics

c. Fields, instruction format

d. Fields, mnemonics

68. Consider the following statements about branching in the Microprogram:

i. When the End microinstruction is encountered, the PC is loaded with the address of the first CW

in the instruction set for the instruction fetch cycle.

ii. When a new instruction is loaded into the IR, PC is loaded with the starting address of the

microinstruction for that instruction.



b. (i) False, (ii) True

c. (i) True, (ii) False

d. (i) False, (ii) False

69. Fetch cycle occurs at the beginning of every instruction. Four main registers that are used in this cycle

are Memory Address Register, Memory Buffer Register, ............., and ................. .

a. Program Counter, Feedback Register b. Program Counter, Instruction Register

c. ax register, Instruction Register

d. ax register, Feedback Register


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70. When a ................ occurs, the Read or Write operation is performed in cache, the main memory is not

involved. In the case of a ..............., the required data is brought from the main memory into cache.

a. Cache miss, cache hit

b. Cache hit, cache miss

c. Cache hit, cache tag

d. Cache miss, cache tag

71. Consider the following statements about recovery from errors:

(i). Many computers include a parity check code in the secondary memory, which allows the detection of

errors in the stored data.

(ii) If an error occurs, the control application detects it and informs the CPU by raising an interrupt.




c. (i) False, (ii) True

d. (i) True, (ii) False

72. Consider the following statements about data buffering:

(i). Data coming from ROM is sent to an I/O module in a rapid burst.

(ii) The data is buffered in the I/O module and then sent to the peripheral device at its rate.



b. (i) False, (ii) True


d. (i) False, (ii) False

73. ................ are small, light, and consume less power than any other type of printers, making them

perfect for ........... and portable applications.

a. Laser printers, retail

b. Laser printers, commercial


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c. Thermal printers, retail

d. Thermal printers, commercial

74. Consider the following statements about visual display:

i. Multichrome monitors are increasingly becoming an obsolete technology as majority applications

today need colour screen.

ii. A graphics adapter board (also called video card) is required to connect a monitor to a projector.


a. (i) False, (ii) True


c. (i) True, (ii) Trued. (i) True, (ii) False

75. Consider the following statements about control memory:

i. Control memory is write-only in nature, because it consists of micro programs that are written

and stored into it permanently.

ii. It must be faster, because to run a machine instruction, several microinstructions have to be

fetched and executed.

State True or False

a. (i) False, (ii) True



d. (i) True, (ii) True


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Answer Keys (Part A & Part B)

Subject Code: BCA 2050 Book ID: B1642

Part - B Part - B

Q.No.

Ans. KeyUnit no./Page no.

Q.No.


Q.No.


1 D 14/328 26 B 3/57 51 C 13/324

2 D 14/336 27 B 3/73 52 D 14/341

3 A 14/332 28 C 3/59 53 D 12/281

4 C 12/283 29 D 3/73 54 A 12/285

5 B 12/285 30 A 5/107 55 C 10/240

6 C 12/283 31 C 5/136 56 C 10/231

7 D 10/242 32 B 5/139 57 D 8/191

8 D 10/236 33 D 5/133 58 C 8/192

9 D 10/238 34 A 7/173 59 C 6/157

10 B 8/196 35 C 7/176 60 C 6/151

11 A 8/186 36 D 7/168 61 C 4/94

12 D 8/190 37 C 7/172 62 A 4/92

13 C 6/146 38 A 9/209 63 D 2/30

14 B 6/158 39 D 9/211 64 A 2/46

15 B 6/145 40 D 9/214 65 A 1/15

16 D 4/76 41 C 9/202 66 D 3/54

17 B 4/88 42 B 11/262 67 C 3/54

18 B 4/93 43 C 11/254 68 C 5/134

19 D 2/44 44 D 11/259 69 B 5/107

20 C 2/31 45 B 11/250 70 B 7/165

21 A 2/32 46 B 13/300 71 B 9/221

22 B 1/3 47 D 5/115 72 B 9/203

23 D 1/5 48 D 13/312 73 C 11/267

24 C 1/12 49 B 13/299 74 B 11/261

25 A 1/5 50 A 10/240 75 A 13/300

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BCA 2050 Computer Organization Model Question Paper