BC66F36x2 Band Matching Parameters and Setup Considerations · 2020-06-16 · Packet Handler WOT WOR Auto-resend/ ACK ATR CLDO DVDD AVDD EP EXTLN EXTLP External Inductor VSSRF Fig

BC66F36x2 Band Matching Parameters and Setup Considerations

AN0550EN V1.00 1 / 15 June 16, 2020


D/N: AN0550EN

Introduction

Holtek’s bidirectional FSK/GFSK high-efficiency wireless transceiver Flash MCU SOC devices,

the BC66F3652 and BC66F3662, are suitable for Sub-1GHz unlicensed ISM Band (300MHz-

960MHz) applications. The devices have integrated a high power amplifier, a frequency synthesizer

and digital demodulation functions which will result in much simplified external circuitry. The radio

frequency characteristics comply with ETSI / FCC specifications.

The device’s integrated wireless transceiver circuit has an operating voltage of 1.9V~3.6V,

programmable transmission power with a maximum +10dBm output, high sensitivity reception

capability, maximum transmission rate of 250kbps and an ATR automatic transceiver (Auto

Transmit Receive) function. The internal high precision low-power oscillator and power-saving

mode auto wake-up transceiver functions are suitable for low-power battery and IoT product needs,

and can be widely used in wireless appliances such as for smart homes, security products, car alarms,

industrial and agricultural controllers, etc.

This application note will introduce the basic functions so that users who are using wireless

transceivers for the first time can understand their working principles and control methods and

quickly start to design related application products.

Operating Principles

The BC66F36x2 devices are wireless transceivers that can be used in each of the Sub-1GHz ISM

bands. Time-division duplex (TDD) method must be used for signal transmission and reception,

which means that only transmission or reception can be performed at a time. The integrated high-

precision local oscillators (LO) is required for both modes of operation. The LO is composed of a

voltage controlled oscillator (VCO) and a non-integer phase-locked loop (Fractional-N PLL).

When transmitting, the data will be modulated by the internal digital packet regulator first, then

pass through the Gaussian Filter and integral-differential modulator (ΣΔ Modulator), then after

frequency synthesis the signal will pass through the integrated power amplifier before being

transmitted on the external antenna.


AN0550EN V1.00 2 / 15 June 16, 2020

When receiving data, the signal is amplified using an integrated low-noise amplifier (LNA) then

adjusted to a lower intermediate frequency (IF) through a mixer. An intermediate frequency

composite band-pass filter and signal strength detector are used to process the signal and obtain the

data and output it through the digital packet demodulator.

The BC66F36x2 transceiver internal structure is shown below.

LNA

PA

DSM

RFIN

RFOUT

SDIOSCKCSN

GIO1~GIO4

ADC

Loop Filter

Control

BPF

Mixer

CP/PFD

MMD

XOXI

Synthesizer

Digital MODEM

CRC/FEC

Manchester

Whitening

Packet Handler

WOT

WOR

Auto-resend/ACK

ATR

CLDO

DVDDAVDD

EP

EXTLN EXTLP

External Inductor

VSSRF

Fig 1. Functional Internal Structure

For the BC66F36x2 devices to implement the transmission and reception of RF signals, the devices

need to first setup their internal control registers. These registers are used to setup functions such

as operating mode, operating frequency, modulation/demodulation, signal format, etc. To do this,

the BC66F3652 implements this through its SPI interface and the PC3-PC6 pins as shown in Figure

2. The BC66F3662 does this using its SPI interface and user-specified I/Os, as shown in Figure 3.

For detailed control methods, refer to the datasheet.

RFTransceiver

MCUI/O Pins RFIN

DVDDRF VDDRF

PC3

PA1

SDIO

IRQ

VSS

XI

XO

PA1/IRQ

VDD

VSS

BC66F3652

RFOUT

EXTLN EXTLP

PC4 GIO2

PC5 SCK

PC6 CSN

GIOx

Fig 2. BC66F3652 Internal Wireless Transceiver Connections


AN0550EN V1.00 3 / 15 June 16, 2020

RFTransceiver

MCUI/O Pins RFIN

DVDDRF VDDRF

PE2

SDIO

GIO2

VSS

XI

XO

PE2/GIO2

VDD

VSS

BC66F3662

RFOUT

SCKCSN

GIOx

EXTLN

EXTLP

Fig 3. BC66F3662 Internal Wireless Transceiver Connections

The following figure shows the overall design architecture which includes an antenna, matching

circuit, external oscillation inductor, crystal oscillator and voltage stabilising capacitors.

BC66F36x2

VDD

VDD

VSS

RFIN

RFOUTRF Matching

EXTLP

EXTLN

VSSRF

XO

XI

VDDRFDVDDRF

CLDO

VDD

VDD

I/O

Fig 4. BC66F36x2 System Block Diagram

Functional Description

Before implementing wireless data transmission, it is necessary to first select the modulation

method, transmission frequency and data rate. The frequency synthesiser and modulation working

method will be introduced in two sections in this application note. There are two main wireless

transmission modes in the wireless transceiver. These are the direct mode, where the data to be

transmitted and received is executed on GIO1 ~ GIO4 and the other is the FIFO Mode, where data

access is executed through an internal FIFO register.


AN0550EN V1.00 4 / 15 June 16, 2020

Transceiver Frequency

The transceiver frequency is generated by a non-integer frequency synthesizer (Fraction-N Delta-

sigma Frequency Synthesizer). By setting the registers D_N[6: 0] and D_K[19: 0], various

frequencies below 1GHz can be generated. The main structure is as follows.

CP/PFD Loop Filter

Band Selection

fXTAL

DSM

fRFVCO

MMDBAND_SEL[1:0]

D_N[6:0]

D_K[19:0]

IF Offset

From modulator

Fig 5. Frequency Synthesizer Structure

To setup D_N and D_K use the following equation.

𝐷𝐷_𝑁𝑁[6: 0] = 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 �𝑓𝑓𝑅𝑅𝑅𝑅

𝑓𝑓𝑋𝑋𝑋𝑋𝑋𝑋𝑋𝑋/(𝑋𝑋𝑋𝑋𝐷𝐷𝑋𝑋𝑋𝑋2 + 1)�

𝐷𝐷𝐾𝐾[19:0] = 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 ��𝑓𝑓𝑅𝑅𝑅𝑅

𝑓𝑓𝑋𝑋𝑋𝑋𝑋𝑋𝑋𝑋/(𝑋𝑋𝑋𝑋𝐷𝐷𝑋𝑋𝑋𝑋2 + 1)− 𝐷𝐷_𝑁𝑁[6: 0]� × 220�

Note: Floor is the downward rounding function.

XODIV2 – refer to the XO2.3 register in the BC3602 Datasheet for more details.

Example:

Default is XO = 16MHz and RF frequency = 433.92MHz

433.92MHz/16MHz = 27.12

DN = 27 → DEC2HEX(27) = 1B

→ DN[6:0] = 001_1011

DK = 0.12 × 220 = 125829 → DEC2HEX(125829) = 1EB85

→ DK[19:0] = 0001_1110_1011_1000_0101

In the receive mode, the frequency synthesizer generates a local intermediate frequency (LO-IF).

The RXIFOS [11: 0] register should be used to control the IF offset. If a data rate equal to or greater

than 200Kbps is used, the IF should be set to 300kHz, otherwise the IF should be set to 200kHz.

The following formula can be used to calculate the RXIFOS fill value.

𝑅𝑅𝑋𝑋𝑋𝑋𝐹𝐹𝑋𝑋𝑅𝑅[11: 0] = 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 ��𝑓𝑓𝐼𝐼𝑅𝑅

𝑓𝑓𝑋𝑋𝑋𝑋𝑋𝑋𝑋𝑋/(𝑋𝑋𝑋𝑋𝐷𝐷𝑋𝑋𝑋𝑋2 + 1)� × 217�

In the transmission mode, the modulator uses the data input to generate a frequency offset.


AN0550EN V1.00 5 / 15 June 16, 2020

Modulator

The BC66F36x2 supports the GFSK modulation method. During modulation, the data is filtered by

an integrated frequency character rate (BT) = 0.5 Gaussian filter. It is then modulated according to the

required frequency deviation (Frequency Deviation: fDEV). The frequency offset is controlled by the

FSCALE [11: 0] register. When determining the frequency offset, the Modulation Index (h) should be

considered. When the data rate (fs) ≤ 10Kbps, h = 8 is recommended and when the data rate ≥

50Kbps, h = 0.75, If the data rate is within the above range (10K <fs <50K), it is recommended to

keep the frequency deviation above 20K. If it is applied to the data rate ≥ 100Kbps, then FSCALE

must be multiplied by a scaling factor (Scaling Factor). Because parameter setting is more complicated

here, general common data rate parameter values are provided here.

Data Rate: fS (BPS) 250K 125K 50K 10K 2K Frequency Deviation: fDEV(Hz) 93.75K 46.875K 18.75K 40K 8K SFRATIO[1:0]=2'b 0h 0h 0h 1h 3h FSCALE[11:0]=12'h 444h 119h 04Ch 0A4h 020h CF_B12[9:0]=10'h 285h 01Dh 000h 000h 000h CF_B13[9:0]=10'h 08Ah 346h 000h 000h 000h CF_A12[9:0]=10'h 012h 022h 000h 310h 302h CF_A13[9:0]=10'h 32Bh 331h 000h 000h 000h CF_B22[9:0]=10'h 114h 386h 000h 000h 000h CF_B23[9:0]=10'h 021h 012h 000h 000h 000h CF_A22[9:0]=10'h 078h 008h 000h 000h 000h CF_A23[9:0]=10'h 028h 008h 000h 000h 000h

Table 1. Commonly Used Frequency Offset Setup Table

The Bank 2 internal values are set according to the following table

Addr. Name Frequency Band 433MHz 868MHz

26h RSV1 02h/C2h (125Kbps/250Kbps:C2h) 27h RSV2 66h/33h (125Kbps/250Kbps:33h) 28h RSV3 AAh 29h RSV4 00h 2Dh RSV5 16h 2Eh RSV6 64h 74h 2Fh RSV7 44h/54h (≧100Kbps:54h) 30h RSV8 00h 31h RSV9 64h 34h RSV10 BCh 9Ch 3Ah RSV11 94h

Table 2. Bank 2 Band Parameter Setup Values

Transmit and Receive Data Packet Format

During wireless transmission, the transmission data packet will be composed of a specified format

with different encoding methods, which can reduce errors and increase the chance of successful

signal transmission. The device uses a common packet format as shown in the figure below. It

contains four fields: Preamble, SYNCWORD, Trailer and data, located in different data fields.

There are a variety of coding formats to choose from, but the functions in the data field are only

effective in a FIFO Mode. The following describes each field and coding format.


AN0550EN V1.00 6 / 15 June 16, 2020

TX: 1~256 bytesRX: 1/2/4 bytes

Preamble SYNCWORD

TX: 4/6/8 bytesRX: 4/6/8 bytes

Trailer Header

1~2 bytes(optional)

PLEN

1 byte(optional)

DATA CRC

2 bytes

CRC calculation (optional)FEC encode/decode (optional)

Whitening (optional)

Manchester encode/decode (optional)

Max. 255 bytes

PID Address 0 Address 1

2 bits 6 bits 8 bits (optional)

4 bits(optional)

Fig 6. Data Packet Format

Preamble

The initial part of the signal string is a repeated 1010 ... or 0101 ... signal, which is called a preamble.

This part of the signal will show the digital signal data rate, which the receiver can use for correction.

In the transmission mode, TXPMLEN can be set to transmit several preamble signal bytes. In the

reception mode, RXPMLEN is used to receive at least several reception bytes. The preamble signal

will be either 1010 ... or 0101... and will be related to the first bit of the SYNCWORD. If the first

bit of the SYNCWORD is 1, then the preamble signal will be 0101 otherwise it will be 1010.....

PKT1: Packet Control Register 1

Bit 7 6 5 4 3 2 1 0

Name TXPMLEN[7:0]

R/W R/W

Reset 0 0 0 0 0 0 0 1

SYNCWORD

Following on from the preamble signal is the SYNCWORD signal. The SYNCWORD is composed

of 4-8 bytes of data. It can be setup by SYNCLEN to contain several bytes. The receiving and sending

end synchronisation characters must be the same. To set the synchronisation character, use the SPI

shortcut command, Write SYNCWORD command (0x10), and note that data must be in a BCH

encoding format.


Bit 7 6 5 4 3 2 1 0

Name PID[1:0] TRAILER_EN WHTFMT SYNCLEN[1:0] RXPMLEN[1:0]

R/W R/W R/W R/W R/W R/W

Reset 0 0 1 0 0 1 1 0

Trailer

The trailer is a fixed 4-bit signal in front of the data and used as a separator. This signal is determined

by the last bit of the sync character. If the last bit of SYNCWORD is 1, then the trailer will be 0101,

otherwise it will be 1010.


AN0550EN V1.00 7 / 15 June 16, 2020

The two synch character field types are shown below.

Preamble MSB SYNCWORD LSB Trailer

0101…01 0 … 0 1010

1010…10 1 … 1 0101

Fig 7. Preamble and SYNCWORD Signal Changes

Header

The header data field contains two data fields, the packet identification code (PID) and the packet

address. The packet identification code is used to identify the packet when the automatic

transmission and reception (ATR) function is used. If the address is different, the device will not

receive data into the FIFO. The header data field is controlled by PLH_EN and the packet address

is determined by PLHA and PLHEA. In addition, PLHLEN can be used to determine whether to

use 6 or 14-bit address numbers.


Bit 7 6 5 4 3 2 1 0

Name MCH_EN FEC_EN CRC_EN CRCFMT PLLEN_EN PLHAC_EN PLHLEN PLH_EN

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 1 0 0 0 0 0


Bit 7 6 5 4 3 2 1 0

Name — — PLHA[5:0]

R/W — — R/W

Reset 0 0 0 0 0 0 0 0


Bit 7 6 5 4 3 2 1 0

Name PLHEA[7:0]

R/W R/W

Reset 0 0 0 0 0 0 0 0

PLEN - Payload Length

The PLEN data field is used to describe how many bytes of data there are so that the receiving end

can know how much data will be received into the FIFO. The PLEN data field can use PLLEN_EN

to control the enable and disable function. After PLEN is enabled, TXDLEN will be automatically

put into this data field when transmitting data. When receiving data, it will determine how many

bits are received according to this data field. If PLEN is off, the amount of data sent and received

will be determined according to the TXDLEN/RXDLEN settings.


Bit 7 6 5 4 3 2 1 0

Name TXDLEN[7:0]

R/W R/W

Reset 0 1 0 0 0 0 0 0


AN0550EN V1.00 8 / 15 June 16, 2020


Bit 7 6 5 4 3 2 1 0

Name RXDLEN[7:0]

R/W R/W

Reset 0 1 0 0 0 0 0 0

DATA

The data field contains the data that the user wishes to send out or receive into the FIFO. To write

data into or read out from the FIFO, use the SPI shortcut command TX FIFO write and RX FIFO

read command (0x11 / 0x91).

Cyclic Redundancy Check

The CRC data field is sent out after the data and is calculated from the data contents. When data is

received, the CRC is calculated again and then compared with the received CRC value. If it is not

the same, RXCRCF will be automatically set to 1 and an interrupt signal can be generated. The

CRC data field can use CRC_EN to control the enable and disable function and CRCFMT can be

used to set different calculation formulas as follows.

CRCFMT = 0：CCITT-16-CRC G(X) = X16 + X12+ X2 + 1 CRCFMT = 1：IBC-16-CRC G(X) = X16+ X15 + X2 + 1

FEC - Forward Error Correction

The FEC encoding function will encode the data to be transmitted with a (7, 4) Hamming Code and

then transmit it. Because it uses 4 bit data to add 4 additional check codes, the encoded data will be

7/4 times bigger. After receiving the FEC encoded data, the receiver has an opportunity to repair

the received data errors. The FEC code can use FEC_EN to control enable/disable function.

Whitening

The white noise coding function adds white noise coding to the outgoing data, and then transmits

the data. After the data is coded with white noise, its anti-interference ability can be increased. The

device uses a PN7 encoding method. To use this function, a noise seed (whitening Seed) is also

required as a noise source. WHTSD must also be set as the noise seed. Note that the noise seed

cannot be 0, otherwise it will have no function. The white noise coding function is controlled by

WHT_EN.


Bit 7 6 5 4 3 2 1 0

Name WHT_EN WHTSD[6:0]

R/W R/W R/W

Reset 0 0 1 1 0 1 1 0

Manchester Coding

The Manchester encoding function will transmit the data in a Manchester encoded format, which

can make the sending end and the receiving end signals easier to synchronise. Using Manchester

encoding, the data length will be twice as long as the original. Refer to the following figure as an

example. Manchester encoding can use MCH_EN to control the enable and disable function


AN0550EN V1.00 9 / 15 June 16, 2020

Clock

1 0 1 0 0 1 1 1 0 0 1

Data

Manchester(IEEE 802.3)

Fig 8. Manchester Code Example

Direct Mode

The device will automatically load default values after power on after which it will enter the Deep

Sleep Mode. To use the Direct Mode to send or receive data, use the following procedure.

Step 1. Setup Parameters: Use the SPI interface to setup the internal control registers. For example,

the frequency (D_N, D_K), modulation parameter (FSCALE), data rate (DTR), etc.

Step 2. Setup the synchronisation characters: Program the TXPMLEN/RXPMLEN registers to determine

the preamble signal length to be transmitted or received. This is implemented using the SPI shortcut

command, Write SYNCWORD (0x10) to set the synchronisation character.

Step 3. Setup the GIO pins: Use the SPI interface to set the GIOxS internal registers. For the setup

values, refer to the BC66F36x2 datasheet. In most cases, TX/RX will bet setup as data

output/input, GIO2 as the interrupt output and GIO3 as the transmit data bit clock. GIO4

will be the received data bit clock. (GIO1S = 0b010, GIO2S = 0b101, GIO3S = 0b1000,

GIO4S = 0b1001)

Step 4. Wake-up the transceiver: Use the SPI command Light Sleep Command(0x0C) to make the

device enter the Light Sleep Mode

Step 5. Wait for the crystal to stabilize then check whether XCLK_RDY is = 1

Step 6. Setup the Direct Mode: Set DIR_EN to 1

Step 7. Start the transmit or receive mode: first set RTX_SEL (0: receive, 1: transmit), and start the

frequency synthesiser (SX_EN = 1) and automatic calibration function (ACAL_EN). After

the automatic calibration process has completed (about 300µs), then start the transmit and

receive function (RTX_EN = 1).

Step 8. Output/read data: Finally, the GIOx (determined by the setup value) can be used to send or

receive data. Here it should be noted that after sending or receiving the preamble,

synchronisation characters and trailer, the correct data can be determined according to the

data bit clock, TBCLK/RBCLK.

The Direct Mode state switching process is shown in the following figure. Here the Idle Mode can make

the device use the internal low-frequency oscillator which will effectively reduce the wake-up time.


AN0550EN V1.00 10 / 15 June 16, 2020

Power Down

Power On

Deep Sleep

Light Sleep

Standby

TX RX

Idle CalibrationsLight Sleep

Deep Sleep

Idle

Deep Sleep

Idle

OM[2:0]=000b OM[2:0]=000b

OM[2]=1

OM[1:0]=00bOM[1:0]=01b (RX)OM[1:0]=11b (TX)(wait~35μs)

Auto (calibration completed)

Calibration enabled

OM[2]=1

Fig 9. Direct Mode State Diagram

The Direct Mode requires the following timing control.

RF Pin

SPI Interface

Operating Mode Light Sleep Standby TX Mode Light Sleep

Next Command

Preamble+SYNC+1010b+Payload

Transmitting TimeRF Setting Time

OM[1:0]=11b

OM[2]=1b

OM[2:0]=000b

…

…

TXD

TBCLK

Fig 10. TX Timing in Direct Mode

RF Pin

SPI Interface

Operating Mode Light Sleep Standby RX Mode Light Sleep

Preamble+SYNC+1010b+Payload

Receiving TimeRF Setting Time

SYNC matched

Payload

…

RXD

RBCLK

Next CommandOM[1:0]=01b

OM[2]=1b

OM[2:0]=000b

Waiting Time

Fig 11. RX Timing in Direct Mode


AN0550EN V1.00 11 / 15 June 16, 2020

FIFO Mode

After power on the default values will be loaded automatically after which it will enter the Deep

Sleep Mode. If the FIFO Mode is to be used then execute the following steps.

Step 1. Setup parameters: Use the SPI interface to program the internal control registers. For example,

frequency (D_N, D_K), modulation parameter (FSCALE), data rate (DTR), etc.

Step 2. Setup the synchronisation characters: Program the TXPMLEN and RXPMLEN registers to setup

the length of the preamble signal to be sent or received. Use the shortcut SPI shortcut command

Write SYNCWORD Command (0x10).

Step 3. Setup the data format: Program the PKT1-PKT9 registers.

Step 4. Setup the FIFO Mode: Set DIR_EN to 0.

Step 5. Reset the FIFO index to zero: Use the SPI shortcut command TX/RX FIFO Address Pointer Reset

Command (0x09 / 0x89) and then set TXFFSA to 0.

Step 6. Write data to be transmitted into the FIFO: Use the SPI command TX FIFO Write Command

(0x11) to write the data to be transmitted into the FIFO. If data is to be received do not execute

this step.

Step 7. Enable the transmit/receive mode: use the SPI shortcut command TX/RX Mode (0x0E /

0x8E) to enable the mode.

Step 8. Wait for data transmit/receive complete: determine whether T / RXCMPIF is 1.

Step 9. Read the FIFO data: Use the SPI command RX FIFO Read Command (0x91) to read the

received data from the FIFO. If data is to be transmitted do not execute this step.

After enabling transmit/receive (Step 7) the complete state switching flow is shown in the

accompanying diagram. The Idle Mode can use the internal low-frequency oscillator, which will

reduce the wake-up time.


AN0550EN V1.00 12 / 15 June 16, 2020

Power Down

Power On

Deep Sleep(<1μA)

Light Sleep(0.65mA)

Standby(5.5mA)

TX RX(13.5~14.5mA)

Idle(<2μA)

CalibrationsLight Sleep

Deep Sleep

Idle

Deep Sleep

Idle

Auto (TX completed)/Light Sleep

Auto (RX completed)/Light Sleep

TX/(Auto) RX/(Auto)

Light Sleep Standby/RX/TX(~35μs)

Auto (calibration completed)

Calibration enabled

Fig 12. FIFO Mode State Diagram

The FIFO Mode timing control is shown below.

RF Pin

SPI Interface

Operating Mode Light Sleep Standby TX Mode Light Sleep

TX Next CommandStrobe Command

Preamble+ID+Payload

Transmitting TimeRF Setting Time Fig 13. TX FIFO Mode Timing

RF Pin

SPI Interface

Operating Mode Light Sleep Standby RX Mode Light Sleep

RX Next CommandStrobe Command

Preamble+ID+Payload

Receiving TimeRF Setting TimeWaiting Time

Fig 14. RX FIFO Mode Timing

RF Pin

SPI Interface

Operating Mode Standby→TX/RX IDLE

TX/RX

Preamble+ID+Payload

Timer Expire

LightSleep

IDLE

IDLE

LightSleep

TX/RXLightSleep

LightSleep

LightSleep Standby→TX/RX

Preamble+ID+Payload

IDLELightSleep

IDLE LightSleep

Timer Expire Timer Expire

1ms 1ms

Fig 15. Periodical TX/RX FIFO Mode Timing

The FIFO Mode is divided into Block FIFO Mode, Extern FIFO Mode and Infinite FIFO Mode.

For other modes of operation, refer to the AN0542EN Application Note.


AN0550EN V1.00 13 / 15 June 16, 2020

Application Circuits

Fig 16. BC66F3652 Application Circuit

Fig 17. BC66F3662 Application Circuit


AN0550EN V1.00 14 / 15 June 16, 2020

RF Input/Output Matching Circuit Guidelines When receiving high-frequency signals, in addition to the antenna, an impedance matching circuit

needs to be added before the signal is input to the device. Good impedance matching will reduce

the amount of noise thereby improving the receiving sensitivity. When adjusting the impedance

matching, it is necessary to use a network analyser to make measurements. Select high-Q capacitors

and inductors, which will effectively improve reception sensitivity.

Antenna

RFOUT

VDD

L6

C5

L2L1

C8C6 C7

L3RFIN

C10

C9C4

L4

L5

Fig 18. Input/Output Matching Circuit

For the application note PCB Layout the following table gives the recommended component values.

433MHz BC66F3652 BC66F3662 Unit C4 N.C. N.C. C5 100 100 pF C6 5 9 pF C7 15 18 pF C8 NC 12 pF C9 12 N.C. pF C10 68. 68 pF L1 18 15 nH L2 15 15 nH L3 0R 0R Ω L4 68 68 nH L5 22 22 nH L6 82 82 nH

Table 3. RF impedance matching Recommended Values

Note: If the PCB Layout is changed then the impedance matching component values will require

adjustment.

Conclusion

This application note has introduced the working principles of the Holtek BC66F36x2 wireless

transceivers. It has shown how they are controlled using the SPI interface where commands are issued

to setup the required frequency and different modes, such as entering the high frequency output/input

mode. It has also introduced the required output/input (RFOUT/RFIN) matching circuits.


AN0550EN V1.00 15 / 15 June 16, 2020

Reference Material

Consult the BC66F3652 and BC66F3662 datasheet.

Consult the AN542EN application note.

For more information consult the Holtek website www.holtek.com.

Revision and Modification Information

Date Author Issue Release and Modification 2019.12.30 何信智 (Ho,Walers) First version

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Documents

BC66F36x2 Band Matching Parameters and Setup Considerations · 2020-06-16 · Packet Handler WOT WOR Auto-resend/ ACK ATR CLDO DVDD AVDD EP EXTLN EXTLP External Inductor VSSRF Fig