Basics of SMPS Modeling

Buck/boost converter control system design

The buck converter is shown in Figure 1. It has capacitor C and inductor L in the output circuit.

ESR is the capacitor equivalent series resistance and R is inductor resistance.

The objective is to control the output voltage Vo of the buck converter under load, line and

command variations by controlling the duty ratio D (Ton/Tswitching period). The efficacy of the

control system can be measured by looking at the system transient response when the system is

subjected to these three types of variations.

Buck converter topology is shown in fig. In the most basic form it consists of a diode, a mosfet ,

a inductor and a output capacitor. The output voltage is desired to be kept constant under

transient load.

This section discusses control system design method for a buck circuit. Later specific model

details pertaining to ac/dc ref design (ZVT, multiphase buck , synchronous buck) and UPS Ref

design (Push pull and inverter section) are discussed

The basic capacitor and inductor eqns are given by (ignoring second order effects of parasitics

like capacitor ESR, inductor DCR)

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Vo = Ic/sC. (1)

IL = VL/sL (2)

Basic power converter eqns averaged over many switching cycles with D being the diode turn on

duty ratio being,

D.Vin – Vo = VL (3)

Where s is laplace variable. 1/s is integration

Then at point A (capacitor diode and load connection) by current summation

IC = IL – Io (4)

The goal is to control the output voltage Vo to be equal to desired voltage Vo*. From eqn 1 it is

evident that to control Vo we need to manipulate Ic. Changing Ic (independent variable ) will

change Vo ( dependent variable).

Voltage mode control

In voltage mode control no current feedback is used in the control system design. Instead only

the capacitor voltage Vo is used. This reduces cost as no current sensor and related high

bandwidth signal conditioning is needed. However, the drawbacks are poor system response /

poor line regulation and difficult to design system. (explaination)

Combining eqn 1,2,3 and 4

We obtain (s2LC + 1 ).Vo = Vx – sLIo (refer appendix A)

Where Vx is voltage applied to the L-C circuit. For a simple buck converter Vx = D.Vin

This form of eqn is inherently oscillatory because of the s2LC + 1 term which has intrinsically

imaginary roots. Therefore it is very difficult to control it directly using standard PID type of

control with positive coefficients (Kp,Ki,Kd).



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Suppose a loop is closed on Vo such that

Vx = (Vo* - Vo).

G where G is a standard PID controller, then at constant load sL.Ioà0

(s2LC + 1 ).Vo = G(Vo* - Vo)

Or

Block diagram

Vo/Vo* = G/ (s2LC + sKd + (Kp + 1) + Ki/s)

where G is sKd + Kp + Ki/s

At medium frequency of excitation the contribution of Ki/s can be neglected, then

Consider the quadratic eqn s2LC + sKd + (Kp + 1), if (Kp + 1) become large then the roots of

the denominator becomes imaginary.

Based on the system (values of Kd , L, C) , even a value of 1 for Kp + 1, (Kp= 0) may cause

imaginary roots. Since sKd is differentiation of the output voltage, it can cause noise



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amplification. So it cannot be increased beyond a point to compensate for the large value of

Kp+1.

Output voltage decoupling

The term 1 is caused because of -Vo in eqn 3 . Since we know that if we apply Vx then Vo will

get subtracted to get VL which is what controls the inductor current. Therefore, if Vo is added a

priori to controller output

i.e. Vx = Vo + G(Vo* - Vo), then the actual voltage applied to the L-C circuit will be G(Vo* -

Vo) as predicted by the PID controller.

Now if the calculation is done then the following eqn is obtained

Vo/Vo* = G/ (s2LC + sKd + Kp + Ki/s)

Bandwidth

The denominator (characteristic eqn) should have 3 roots known as 3 poles or the 3 bandwidths

f1> f2 >f3 (units of Hz) of the controller. These should be chosen based on your system specs.

f1,f2,f3 should be well separated with a factor of 3 between them. This ensures any parameter

variation (L,C) due to manufacturing tolerances or inductor saturation will not effect the stability

of the system .

f3 determines the settling time i.e time the system takes to settle within 98% of Vo* for a step

change in Load. It should be chosen such that 4./2πf3 < settling time specification. (appendix)

(diagram /snapshot)



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f2 determines the ability of the controller to track changes in Vo* . If Vo* varies then Vo will be

able to track Vo* variations up to frequency f2 Hz.

f1 is present only to make the system non oscillatory/resonant at frequencies > f2 .

Since the controller has a D term, it may be desirable to filter high frequency ripple content on

the output voltage feedback signal with low pass filter. The cutoff frequency should be less than

the ripple frequency (typically switching frequency). This is all derived from fundamentals of

quadratic equations.

Determining gains

The gains Kp, Ki and Kd can be determined once f1, f2 and f3 have been chosen. The

denominator/characteristic eqn can be treated as a cubic equation. Since s = -2πf1 , -2πf2 and -

2πf3 which are the roots of characteristic eqn should make it 0, by susbstituting for s in turn with

the roots and setting the right hand side 0 , 3 linear equations in Kp, Ki and Kd are obtained.

These 3 can be solved using standard methods like to obtain values for Kp, Ki and Kd.

Modulation inverse (duty ratio generation)

The DSC can only generate PWM signal. The controller output is Vx. The code has to convert

Vx into duty ratio or a parameter value 0<=D<=1. Based on the topology of the power converter,

the relation between parameter D and voltage applied to L-C circuit can be found. Usually it will

be a relation involving input voltage, output voltage and duty ratio.

For e.g. for a simple buck converter

D.Vin = Vx

If Vin is measured, D can be obtained. Vin can also be considered as a constant and buried with

the gains. By measuring Vin line regulation (output change to changing line voltage) can be

improved tremendously. While implementing digitally a CPU intensive divide function is

needed, the division can be performed every once in a while ~ 1ms, as the input line voltage Vin

is not expected to change fast due to source capacitance.

Once that relation has been obtained, The Vx value can be converted to D. This will be discussed

in detail for each of the modules.



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Disturbance/Load rejection

The transfer function Io(s)/Vo(s) (with Vo*(s) = 0) is called as dynamic stiffness/disturbance

rejection. It tells us for a unit amplitude distortion in Vo what is the amount of load needed as a

function of frequency. We want our system to be as stiff as possible so that the output does not

change under load. In the above e.g. it is (s2LC + sKd + Kp + Ki/s)/sL . The typical magnitude

plot on log – log scale is given in fig.

It is typically a U shaped plot.

At high frequency Capacitance C (system inertia) dominates, at lower frequency <f1 Kd, at

lower frequencies < f2 Kp and at frequencies < f3 Ki dominates provided f1,f2,f3 are well

separated .

This has to be analyzed for designing any real world system based on the specs on Vo dip under

changing load.

While doing digital implementation, f3 should not be more than 1/6th to 1/7th of the control loop

frequency for stability reasons. It can be proven that if this is not the case then at steady state the

Drive duty will tend to oscillate causing noise. (Appendix)



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Current mode control

Current mode control is preferable when current sensors and signal conditioning hardware are

available. It controls the inductor current independently and simplifies the system tuning

process. The measured inductor current is used as a feedback signal to implement a high

bandwidth inner P current loop. The inductor described by Equation 4 acts as a pure integrator

when the voltage is applied across its terminals. Therefore, a P gain (Ra) is

adequate. The gain Ra has dimensions of resistance. The value of Ra can be predicted analytically

or from the system characteristic equation. The feedback

system emulates a series resistance. Since the bandwidth of a R-L circuit is R/L rad/s, higher

value of Ra implies higher current loop bandwidth.

What was being achieved by D term in PID control in voltage mode control is being achieved by

current feedback. The steps pertaining to output voltage decoupling and modulation inverse still

remain valid. The discussion pertaining to bandwidth remains valid with the crucial difference

that, an inner current loop is closed. The current reference IL* is generated using the outer

voltage loop.



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Physical inductor system

Vx = Vo + sL.IL

Inner current loop implementation with output voltage decoupling. Vx is generated by the drive

.All other calculations happen in software.

Vx = Ra.(IL* - IL) + Vo

The above eqns leads to

IL = IL*.Ra / (Ra + sL)

Physical capacitor system

IL – Io = Ic

Ic = sCVo

Outer PI voltage loop

IL* = (Vo* - Vo).(Kp + Ki/s)

Combining the above 4 eqns the following eqn is obtained

The new expressions are as follows

Vo/Vo* = (Kp.Ra + Ki.Ra/s)/ (s2LC + sC Ra + Kp.Ra + Ki.Ra/s)



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Block diagram

The denominator denotes the characteristic equation and its roots correspond to the 3 bandwidths

namely current loop, voltage loop and integrated voltage.

Ra, Kp.Ra and Ki.Ra (unknown coefficients of powers of s) can be found for 3 desired values of

f1,f2 and f3 by similar method to section on bandwidth. Once these are known , Kp , Ki, Ra can

be determined. Kp will have dimensions of conductance ( ohm-1) and Ki will have dimensions

of (ohm-1 sec -1)

The equation for disturbance rejection can be found to be

Io(s) / Vo(s) = (s2LC + sC Ra + Kp.Ra + Ki.Ra/s)/(sL+Ra)

Peak current mode control



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In peak current mode control the inductor current is limited to a current reference (generated by

outer PI loop) on a cycle by cycle basis using hardware/comparator circuit. From a control

system standpoint the current loop can be assumed to be ideal. The formulation and derivation

of the transfer functions can be done by taking the average current mode control with a very high

value of Ra. The bandwidth for voltage loop is chosen to be considerably lower than the

switching frequency so intra–switching cycle variations in current are not visible to the

controller. (explain) The current variations are so fast (at switching frequency) that the voltage

due to presence of output capacitance cannot change.

In doing the analysis it can be assumed that Raà (the current loop is very fast)

So the new equations become

Vo/Vo* = (Kp + Ki/s)/ ( sC + Kp + Ki/s)

Io(s) / Vo(s) = ( sC + Kp + Ki/s)

The characteristic equation is only 2nd order and hence there are only 2 roots to be found. The 2

roots refer to the voltage loop and integrated voltage loop bandwidths.

For peak current mode control no modulation inverse and output decoupling is needed as

current reference is directly being set instead of setting the duty ratio.

Application for different topologies

From a control system perspective many converters can be modeled as a buck converter.

Zero voltage transition, Push Pull, Multiphase buck, Synchronous buck, Full bridge

inverter. These are the various blocks that are used in the reference designs from microchip. The

essential design process for the control system remains the same. The following section

describes the key differences and considerations for the design process.

Zero voltage transition converters

In zero voltage transition converters from a control system perspective the key difference is how

the duty ratio gets applied to the LC circuit. A variable voltage gets applied to the L-C by

varying the phase of the drive given to the 2 top MOSFET switches. The duty ratio to each of the



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individual switches is fixed to 50%. If same signal is applied to both top switches in phase then

the voltage applied is 0. If they are separated by 180 degrees then voltage applied is +Vdc and –

Vdc and the output voltage will be Vdc if there is a 1:1 turns ratio in the transformer. All other

voltages can be generated by linearly varying the phase.

Therefore a parameter φ is defined such

Vo = Vin.( φ )/π where φ is the angle in radians of the phase difference between the top 2

switches in the H bridge drive.

This equation is used to generate φ in the modulation inverse section from controller output to be

loaded in the duty.

While doing the design all quantities have to be referred to either the primary or secondary side

with appropriate changes to L and C , voltages and current values using energy equivalence

relations. Refer standard text on transformers.

Multiphase buck

In this topologoies multiple paralleled buck converters with common input and output and

current is shared between the converters. This can be modeled as a single buck converter from a

control perspective. The output capacitance of the buck converters will be equal to the output

capacitor bank. The effective inductance will be 1/n th of the individual branch inductances. This

is because the inductances act in parallel to the total output current.

The inductance values will remain the same. The rest of the control system design is done as

discussed previously

Synchronous buck

From a control system standpoint the design process is identical to designing control system for a

buck converter.

Push pull converter

In a push pull converter the transformer is energized and reverse energized using 2 separate

primary coils. The push pull converter can be modeled as a buck converter if all

values/quantities (voltages, currents, capacitance and inductances) are referred to either the



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primary or secondary. Ignoring second order effects due to parasitics and assuming everything as

ideal, if D is the duty given to one of the mosfets, then the voltage applied across the LC circuit

will be given by

2.D.Vin = Vx (appendix)

This equation is used to calculate the duty cycle from the controller output Vx.

Full bridge sine wave inverter

A full bridge sine wave inverter is used to convert a DC voltage to a sinewave. The sinewave can

be generated using many different switching methods. However the average case model still

remains the same. There are 2 legs A and B. L-C circuit appears between A and B. The goal is to

generate a sinewave across the capacitor. The sine wave shape and amplitude should be as close

to desired sinewave shape under changing load and line conditions. (ckt diagram)

If D is the duty applied to top switch of leg A, then 1-D is applied to top switch of leg B. The top

and bottom switches in each leg are PWMed in the complementary mode of operation. The

voltage applied across the L-C circuit is therefore

Vx = (2.D - 1)Vin

This can be used in modulation inverse section.

A sine wave inverter is expected to support currents of inductive capacitive or rectifier loads. At

the minimum the sine wave inverter should support loads of 50-60 Hz frequencies with arbitrary

phase (-90 to 90) without significant change to sine wave shape and amplitude voltage. Inductive

loads tend to cause a dip in the amplitude of the sine wave while capacitive loads tend to increase

the output voltage. It is very important to study the disturbance rejection properties of the

system @ fundamental frequency. Due to choice of low value of capacitance and limited

switching frequencies which limit the achievable bandwidth of voltage loop the disturbance

rejection can be poor.

If this is the case then there will be a significant dip/rise in the voltage at higher loads which is

not desirable.



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To overcome this the following steps can be taken based on cost/complexity considerations

1. Increase the capacitance value in the L-C filter.

2. Increase switching frequency, control loop frequency and the associated bandwidths

3. Directly or indirectly measure the load current and use that information to add iL*. The effect

of load will be negated to the extent of accuracy of load current measurement. If your load

measurement is 90% accurate, 90% of the dipping/rising due to load is removed thus improving

your system disturbance rejection by a factor of 10.

4. Estimate the load using some form of open/closed loop observer based on a parametric model

of the system. use the estimate for decoupling load and improving disturbance rejection. Please

refer to literature on observers for detailed information. The only disadvantage is complexity of

resulting code.

(Maybe addressed if there is a requirement)

Boost converter

( ckt Diagram)

The essential equations in a boost converter are given below.

Vo = Ic/sC. (1)

IL = VL/sL (2)

Basic power converter eqns averaged over many switching cycles with D being the diode turn on

duty ratio being,

Vin – DVo = VL (3)

DIL = ID (4)



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Where s is laplace variable. 1/s is integration

Then at point A (capacitor diode and load connection) by current summation

IC = ID – Io (5)

Except for eqn 3 ,4 the rest of the eqations are similar to the physical equations for buck

converters.

From a control system perspective many converters can be modeled as a boost converter. E.g DC

–DC ref design, PFC section in AC-DC ref design and interleaved PFC

These are the various blocks that are used in the reference designs from microchip. The essential

design process for the control system remains the same. The following section describes the key

differences and considerations for the design process for the particular designs

DC-DC converter ref design

In this design a front end boost circuit boost input 36-60V to 110 V and a fixed duty resonant

converter converts it to 12V. Only the boost circuit is controllable however the feedback is taken

from the 12V level to correct for transformer losses etc.

The output capacitance of resonant converter gets reflected on the output of the boost. This can

be found using standard transformer energy equivalence circuits.

The system operates in peak current mode control. Therefore equations under section on PCM

can be used to calculate the gains from chosen bandwidths.

Since inductor current is being measured and used for cycle by cycle peak current mode control,

it does not reflect the physical nature of the system. In peak current mode control the voltage

error with a PI gain sets the current reference. Since the output is a capacitor the current

reference being set should reflect desired capacitor current. With constant/slowly changing load

Id* = Ic* + Io , the reference should reflect the diode current. However since inductor current is

being measured Id* needs to be converted to IL* . This is done using power flow conservation in

the switches IL* = Id*. Vo /Vin.



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The DSpic performs the Vo/Vin calculations. The factor 1/Vin is not likely to change at the

control loop frequency and can be computed at a slower update rate.

PFC design

In a good quality grid, the supply voltage will be sinusoidal. If we maintain the current drawn

from the grid in phase sinusoidal with voltage, the grid will see only a resistive load and grid

losses will reduce due to reduced current drawn. Both the power factor and distortion factor will

be close to 1. The THD (total harmonic distortion) will be close to 0. The goal of a PFC system

is to make the end consumer system look like a resistive load to the grid. The PFC is typically a

boost circuit. Though PFC can be performed using other topologies as well, our discussion will

be limited to boost system operating in continuous conduction mode. The input to the boost is a

rectified sine wave (time varying input) as opposed to a regular DC-DC converter. In grids with

low power quality, the rectified sine wave may also be distorted. The goal of the PFC circuit is 3

fold.



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1. Maintain the wave shape of the input current as close to the input voltage.(distortion factor).

2. Ensure that the input current and input voltage wave are in phase (power factor).

3. Maintain boost output voltage (usually 400V) under changing load conditions and wide input

voltage (typical range 85V – 265V RMS for the sine wave input to the rectifier).

The primary aim is to control the inductor current to track a wave which is proportional to the

rectified voltage Vin(t) .

Suppose inductor current IL*(t) needs to flow through the inductor at a certain time in the

voltage cycle. We need to control the inductor current IL to track a changing IL* which is in

phase with the rectified voltage and hence consequently changing with time. (How IL* is

generated will be discussed later)

Assuming the rectified voltage has a frequency of ~100-120Hz, IL* will also have a same

frequency. Therefore for reliable command tracking the bandwidth required for current should be

at least 10 times the frequency of IL*. Then changes in IL* will be slow enough for the high

bandwidth current loop (fast, low time constant) to track.

Assuming a switching frequency of the boost circuit to be ~80 KHz, control loop bandwidth for

current can be safely chosen around 1000 – 2000 Hz. The voltage loop bandwidth is chosen to

be 10 Hz so the fundamental rectified sinewave 100-120 Hz which is the current does not get

distorted due to fast acting outer loop. The zero bandwidth is chosen to be 1/5th to 1/4th of the

voltage loop bandwidth i.e. 2Hz.

Since the voltage and current loop bandwidths are well separated it suffices to use approximate

relations (from characteristic eqn) for their calculations.

2πfw = Ra/L 21

2πfv = Kp/C

2πfv = Ki/Kp



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To achieve that from basic boost converter eqn the turn on duty ratio for the diode in the boost

circuit is given by

(Vin – VL*)/Vo = D 22

This step is analogous to performing output voltage decoupling and modulation inverse

described in buck converter section.

This step automatically takes care of voltage feedforward. Since the voltage loop bandwidth is

slow, to correct for input voltage change voltage feedforward is used. However if D is generated

using Vin and Vo then feedforward is not needed.

There is a maximum value of (1-D) the turn on duty ratio for MOSFET that for safety reasons

and normal operation is limited to about 90%. Which means the minimum value fo D is limited

to 10%. In actual implementation 1-D is used to drive the PFC boost MOSFET.

In a typical PFC circuit the output voltage is a slow varying quantity due to bulk capacitor and

can be assumed to be constant or to save processor MIPS, the fraction 1/Vo can be calculated

every once in a while for e.g. 1 ms, where as the control takes place every 10 us (100KHz) .

While doing digital system proper scaling needs to be taken care of. Again all equations

described here are in real physical units.

Generation of IL*

IL* is a rectified sine wave that is used as a command to control the inductor current . IL* should

have the following properties

1. IL*(t) is proportional to Vin(t) or |sin(θ)| . Suppose we have an average value of <IL*> Then

to get the instantaneous desired inductor current IL*(t) we need to multiply it with |sin(θ)| .π/2 .

This is because the average value of |sin(θ)| over 1 half cycle is 2/π .

<IL*(t)> = <ILpk*| sin(θ)|> = ILpk*.2/π

ILpk* = <IL*(t)> .2/πTherefore IL*(t) = <IL*(t)> .2/π . | sin(θ)|



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2. ID*(t) should reflect error in output voltage (Vo*- Vo) so corrective action can be performed.

ID*(t) is the manipulated variable for output voltage control.

3. Since IL will be varying at 100 -150 Hz to follow the rectified sinewave input, the corrective

action due to output voltage error generated from loading of output, should be much slower

otherwise, the shape of IL will get distorted. Therefore to maintain shape the bandwidth for

voltage loop is chosen to be 1/10 of rectified sine wave frequency. fv is chosen to be 10-15 Hz.

Combining 1,2,3,4,5

IL*(t) = G.(Vo*-Vo).|sin(θ)| . π /2 23

Where G is gain. As discussed previously in section (eqn 9- eqn10) G needs to be of the form PI

with 2 terms Xa and Xsa.

PFC Notes

1. The zero frequency is chosen to be 1/5 th of fv ~ 2-3Hz. The gains Xa and Xsa are calculated

using eqn 7a and 11. The dynamic performance should ideally be determined by G. The other

factors are present to condition the control system and take into account the boost topology and

changes in input voltage. The other factors are slowly varying compared to 100-150Hz funda

mental frequency and may be assumed to be constant for 1 cycle.

2. |sin(θ)|.π/2 can be generated in software for good grids where Vin is rectified sinusoidal.

Otherwise |sin(θ)|.π/2 needs to be replaced by. Vin(t)/Vavg so that the current still follows the

voltage inspite of distortion in input voltage.

3. It should be noted that from the output capacitor perspective, the gain G was chosen based on

our choice of bandwidth provided ID can be manipulated instantaneously. ID averaged over 1

cycle is now being manipulated due to sinusoidal nature of IL.

4. Due to practical limits on D, >10% ,there are flat regions in the current wave shape when the

voltage is near zero. It essentially means that when the input Vin(t) is near 0,i.e. θ~0 or π



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radians, with maximum turn on time for MOSFET being clamped, it is impossible to boost

voltage to Vo with continuous conduction operation. E.g. If Vin(t) is 20 V and Vo is 400V, i.e.

boosting 20 times, then diode cannot be on for more than 1/20 = 5% of time in continuous

conduction mode. Since we have clamped our duty ratio to 10 %, the result is non ideal wave

shape in that region of operation.

5. Because the bandwidth of Vo is small, Vo takes a long time to correct and system to stabilize.

To minimize the change in Vo under changing loads C is made large. If the load can be

measured using a separate current sensor then its effects could be decoupled. This is known as

load feed forward or disturbance decoupling. So instead of load causing a dip and then the PI

controller taking a corrective action, the action is taken apriori. With this method the output

capacitor size can be reduced significantly.

6. A careful analysis will yield that the voltage loop bandwidth is also a function of duty ratio. In

fact it is equal to fv.D2 Hz where D is the diode duty ratio. So as the duty changes over one 100

Hz rectified sinewave cycle the bandwidth also changes. It is maximum at the peak of the

sinewave and minimum near the zero crossings.

7.At low frequency loads < 10Hz the value of |Io/Vo| ~ X will be small . For a 1000W watt

system it will be 1/30. So for every A of output load amplitude at say 5 Hz frequency the output

will dip by 30V. This may or may not be acceptable. At steady state and high frequency load the

problem is far less severe.

So to overcome this load feedforward may be necessary. This may be achieved using one of the

• Directly or indirectly measure the load current and use that information to modify iL*

using power flow equations. Estimate the load using some form of open/closed loop

observer based on a parametric model of the system. use the estimate for decoupling load

and improving disturbance rejection. Please refer to literature on observers for detailed

information. The only disadvantage is complexity of resulting code.

• IL* (contribution from load) = Io^.2Vo/Vinpk . sinθ

This allows pre-emptive action for varying loads of low frequency. The effect of load w

will be negated to the extent of accuracy of load current measurement. If your load



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measurement is 90% accurate, 90% of the dipping/rising due to load is removed thus

improving your system disturbance rejection by a factor of 10.

8.

Interleaved PFC system

In the interleaved PFC system there are 2 boost PFC circuits paralleled (common input and

common output) and being driven by PWM which are 180 degrees out of phase.

The above analysis holds for interleaved PFC system as well, the only difference being IL*

calculated above represents the total desired input current.

The individual boost circuits are now given IL*/2 as the reference. There are 2 parallel current

loops (1 for each boost circuit) running in the processor with IL1 and IL2 being the 2 inductor

current feedbacks.

Digital control implementation

• This is done using zero order hold or latch c2d transform on PID controller. Voltage

decoupling are implemented as is. Zero order hold implies that the value of D is being

held for 1 sampling period. So the digital system latches the value for 1 sampling cycle.

• Essentially Kp remains as Kp , Ki/s becomes Ki.Ts.z-1/(1-z-1) , Kd becomes Kd.Ts.z-

1/(1-z-1)

• Zero order hold (latch) with appropriate sampling time for driving the system are inserted

in the simulink model

• ADC and PWM quatizers and saturation blocks are implemented in simulink.

General notes

• While implementation in digital with a control loop frequency Fs, the maximum

bandwidth should be limited to 1/7 of the control loop frequency. The control loop

frequency itself is limited to the switching frequency. Any control loop frequency higher



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than switching frequency will result in wastage of mips as same PWM duty ratio cannot

be reliably updated in the middle of switching cycle.

• The 98% settling time (time for output to reflect 98% of total output change for a step

input) specification can be used to determine the bandwidths to be chosen. The settling

time is dictated by the zero bandwidth of PI controller. Settling time can be equated to

4./2πfz where fz is the zero frequency. This is because e-4t/τ ~ 0.02 << 1 . which is to

say after 4 time constants, the transient has decayed enough compared to the value at t

=0.

(graph)

• The smaller the bandwidth compared to control loop frequency the closer the digital

approximation of the original analog system. It can be proved that the actual bandwidth

in a digital approximation of analog control will be reduced by about 30% for analog

bandwidth that was chosen to be 1/7 of the control loop frequency. This may or maynot

be significant depending on the system

Digital implementation challenges

• In digital implementation the integral gain Ki translates to Ki.Ts .If the value of Ts is

small, which occurs when the control loop frequency is high then Ki.Ts may become very

small and due to finite fixed point processor representation in MCU its contribution

Ki.TS.e to control system can end up getting truncated to 0. This will lead to steady state

errors. It may be desirable to have a different control loop frequency for outer loops. This

will ensure that Ts is large enough to produce a finite contribution every cycle. This case

appears in PFC applications where current loop sampling occurs at close to 10000 Hz.



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The voltage loop is tuned to a value less than 10-20 Hz resulting in small value of Ki. To

avoid truncation of Ki.Ts.e , Ts should be chosen to be high enough. This implies a

smaller control loop frequency.

• In Converters which involve transformers, the modeling has to be performed by referring

all quantities like voltages, currents incutances and capacitances should be refered to

wither the primary or secondary side. While implementing in the MCU , the scaling

factors need to be taken care of appropriately while taking measurements. For e.g. in a

12 V output with 10:1 turn ratio , if the control loop design has been performed using

primary side, and feedback is from 12 V , then some software logic is needed to ensure

that the 12 V level measured in ADC refers to 120 V.

• In simulation it might be advisable to ensure the uni directionality of devices like diodes

etc. Also capacitor voltages and inductor currents should be initialized to approximate

steady state values to increase the speed of simulation.

Appendix

Fix schematics



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