BasicZrouteFlow

PrerequisitesforRou4ngLibraryrequirementsZroutegetsallofthedesignruleinforma4onfromthetechnologyfile;therefore,youmustensurethatalldesignrulesaredefinedinthetechnologyfilebeforeyoustartrou4ng.Designrequirements

•  Beforeyouperformrou4ng,yourdesignmustmeetthefollowingcondi4ons:•  PowerandgroundnetshavebeenroutedaCerdesignplanningandbefore

placement.•  Clocktreesynthesisandop4miza4onhavebeenperformed.•  Es4matedconges4onisacceptable.•  Es4mated4mingisacceptable(about0nsofslack).•  Es4matedmaximumcapacitanceandtransi4onhavenoviola4ons.

CheckingRoutabilityACerplacementiscompleted,youcanusethecheck_zrt_routabilitycommand(orchooseRoute>CheckRoutabilityintheGUI)tocheckwhetheryourdesignisreadyfordetailrou4ng.Bydefault,thiscommandchecksfor•  BlockedstandardcellportsAstandardcellportisconsideredblockedifnoneofitsphysicalpinsisaccessible.•  Blockedtop-levelormacrocellportsAtop-levelormacrocellportisconsideredblockedifnoneofitsphysicalpinsisaccessible.•  Out-of-boundarypinsThischeckverifiesthatallpinsarewithinthedesignboundary.•  Minimumgridviola4onsThischeckverifiesthatallpins,includingthosewithinlibrarycells,areontheminimumgrid,asdefinedbythegridResolu4onaVributeinthetechnologyfile.

Rou4ngCorridorsArou4ngcorridorrestrictsZrouteglobalrou4ngforspecificnetstotheregiondefinedbyasetofconnectedrectangles.Inaddi4ontospecifyingtheregioninwhichtherou4ngoccurs,youcanalsospecifytheminimumandmaximumrou4nglayersforeachoftherectanglesthatcomprisetherou4ngcorridor.Rou4ngcorridorsareintendedtobeusedtoroutecri4calnetsbeforesignalrou4ng.Forexample,Figureshowsarou4ngcorridornamedcorridor_1,whichismadeupofsixrectangles.Thisrou4ngcorridorisassociatedwiththenetsshowninyellow.ThefigureontheleCshowsthenetsbeforerou4ng,whilethefigureontherightshowsthenetsroutedwithintherou4ngcorridor.

GlobalRou4ngTheglobalrouterdividesadesignintoglobalrou4ngcells.Bydefault,thewidthofaglobalrou4ngcellisthesameastheheightofastandardcellandisalignedwiththestandardcellrows.Foreachglobalrou4ngcell,therou4ngcapacityiscalculatedaccordingtotheblockages,pins,androu4ngtracksinsidethecell.Althoughthenetsarenotassignedtotheactualwiretracksduringglobalrou4ng,thenumberofnetsassignedtoeachglobalrou4ngcellisnoted.Thetoolcalculatesthedemandforwiretracksineachglobalrou4ngcellandreportstheoverflows,whicharethenumberofwiretracksthatares4llneededaCerthetoolassignsnetstotheavailablewiretracksinaglobalrou4ngcell.Globalrou4ngisdoneintwophases:•Theini4alrou4ngphase(phase0),inwhichthetoolroutestheunconnectednetsandcalculatestheoverflowforeachglobalrou4ngcell•Thererou4ngphases,inwhichthetooltriestoreduceconges4onbyrippingupandrerou4ngnetsaroundglobalrou4ngcellswithoverflows

GlobalRou4ng

Beforeproceedingtodetailrou4ng,displaytheconges4onmapintheGUI,andchecktheoverflowdistribu4on.Theconges4onreportandmaphelpyoutoiden4fycongestedareas.

TrackAssignmentThemaintaskoftrackassignmentistoassignrou4ngtracksforeachglobalroute.Duringtrackassignment,Zrouteperformsthefollowingtasks:•Assignstracksinhorizontalpar44ons.•Assignstracksinver4calpar44ons.•Reroutesoverlappingwires.ACertrackassignmentfinishes,allnetsareroutedbutnotverycarefully.Therearemanyviola4ons,par4cularlywheretherou4ngconnectstopins.Detailrou4ngworkstocorrectthoseviola4ons.

TrackAssignment

Attheendoftrackassignment,Zroutereportsasummaryofthewirelengthandviacount.ACertrackassignment,youcandisplayaconges4onreportandmapthatarebasedonthetrackassignmentresults.

DetailRou4ngThedetailrouterusesthegeneralpathwayssuggestedbyglobalrou4ngandtrackassignmenttoroutethenets,andthenitdividesthedesignintopar44onsandlooksforDRCviola4onsineachpar44on.Whenthedetailrouterfindsaviola4on,itripsupthewireandreroutesittofixtheviola4on.Duringdetailrou4ng,Zrouteconcurrentlyaddressesrou4ngdesignrulesandantennarulesandop4mizesviacountandwirelength

DetailRou4ng

ACerdetailrou4ng,youcandisplayaconges4onreportandmapthatarebasedonthedetailrou4ngresults.

AnalyzingConges4on

Inthedefaultconges4onreport,•“Hrou4ng”referstoresultsforhorizontalroutesonlyand“Vrou4ng”referstoresultsforver4calroutesonly.•TheOverflowvalueisthetotalnumberofwiresinthedesignthatdonothaveacorrespondingtrackavailable.•TheMaxvaluecorrespondstothehighestnumberofoveru4lizedwiresinasingleglobalrou4ngcell.•TheGRCsvalueisthetotalnumberofovercongestedglobalrou4ngcellsinthedesign.

Conges4onMap

Conges4onMapIfthedesignshowscongestedareas,zoomintothecongestedareatoseetheconges4onvalueontheglobalrou4ngcell.Forexample,inFigure6-9,theredhighlightontheedgeoftheglobalrou4ngcellshows18/9.Thismeansthereare9wiretracksavailable,but18tracksareneeded.

ChipFinishing

TapCellsTapcellsareaspecialnonlogiccellwithwellandsubstrate4es.Thesecellsaretypicallyusedwhenmostorallofthestandardcellsinthelibrarycontainnosubstrateorwelltaps.Generally,thedesignrulesspecifythemaximumdistanceallowedbetweeneverytransistorinastandardcellandawellorthesubstrate4es.YoucaninserttapcellsinyourdesignbeforeoraCerplacement:•Youcaninserttapcellarraysbeforeplacementtoensurethattheplacementcomplieswiththemaximumdiffusion-to-taplimit.•YoucaninserttapcellsaCerplacementtofixmaximumdiffusion-to-tapviola4ons.

AntennaViola4onsInchipmanufacturing,gateoxidecanbeeasilydamagedbyelectrosta4cdischarge.Thesta4cchargethatiscollectedonwiresduringthemul4levelmetalliza4onprocesscandamagethedeviceorleadtoatotalchipfailure.Thephenomenonofanelectrosta4cchargebeingdischargedintothedeviceisreferredtoaseitherantennaorcharge-collec4ngantennaproblems.Topreventantennaproblems,thetoolverifiesthatforeachinputpinthemetalantennaareadividedbythegateareaislessthanthemaximumantennara4ogivenbythefoundry:(antenna-area)/(gate-area)<(max-antenna-ra4o)Theantennaflowconsistsofthefollowingsteps:1.Definetheantennarules2.Specifytheantennaproper4esofthepinsandports3.Analyzeandfixtheantennaviola4ons

FillerCellsFillercellsfillgapsinthedesigntoensurethatallpowernetsareconnectedandthespacingrequirementsaremet.•  Beforerou4ng,youcan

-  Insertstandard-cellfillers-  Insertendcapcells

•  ACerrou4ng,youcan-  Insertwellfillers-  Insertpadfillers

FillerCellsYoucanfillemptyspacesinthestandard-cellrowswithinstancesofreferencefillercellstomakesureallpowernetsareconnected.Onemethodofimprovingthestabilityofthepowersupplyistoadddecouplingcapacitorsasfillercells.

MetalFillACerrou4ng,youcanfilltheemptyspacesinthedesignwithmetalwirestomeetthemetaldensityrulesrequiredbymostfabrica4onprocesses.Beforeinser4ngmetalfill,thedesignshouldbeclosetomee4ng4mingandhaveonlyaveryfewornoDRCviola4ons.

AnICValidatorlicenseisrequiredtorunthesignoff_metal_fillcommand.

RTLSynthesisFlow

P&RFlow

ChipLayout

TimingDrivenPlacement

finished

Thetroublewithaplace-then-routestrategyisthataCerthelayoutiscompleted,theparasi4crou4ngcapacitanceisextractedandthe4minganalysisisdonetoes4mate4ming.The4mingisnotknownun4lthephysicallayoutiscomplete.If4mingproblemsarefound,thecyclehastoberepeatedwithsomekindofconstraintplacedontheproblema4cpaths.

Cellsoncri4calpathsaregivenprioritytominimizewiredelay.

MixedSignalFlow