BASIC VLSI DESIGNPrinciples and Applications

Douglas A. Pucknell

Kamran EshraghianDepartment of Electrical and Electronic EngineeringThe University of Adelaide

and Directors of Integrated Silicon Design Pty LtdAdelaide, South Australia

lechnische Hochschule DarmstadtFACHBEREICH INFORMATfK

B I 8 L I O T H E KInviantnr.Mr . •Z?.7 / T~~ , r

Sachgebiete»

Standorh :

Prentice-Hall of Australia Pty Ltd

Contents

FiguresTablesPrefaceAcknowledgments

VIII

xiii

xiv

xvii

Chapter 1

Chapter 2

Chapter 3

A Review of Microelectronics and an Introduction to nMOSTechnology

1.1 Introduction to Integrated Circuit Technology1.2 The Integrated Circuit (IC) Era1.3 Metal-Oxide-Semiconductor (MOS) Technology and VLSI1.4 Basic nMOS Transistors1.5 Enhancement Mode Transistor Action1.6 Depletion Mode Transistor Action1'7 nMOS Fabrication1.8 Summary of an nMOS Process ,

Basic Electrical Properties of nMOS Circuits

2.1

2.22.32.42.52.62.7

2.92.10

Drain to Source Current 1^ versus Voltage V^ Relationships2.1.1 The nonsaturated region2.1.2 The saturated regionAspects of Threshold Voltage Vt

Transistor Transconductance gm ~Figure of Merit (0o

The Pass TransistorThe nMOS InverterDetermination of Pull-up to Pull-down Ratio (zp.u./zp.d.) for anInverter Driven by another InverterPull-up to Pull-down Ratio for an Inverter Driven through One orMore Pass TransistorsAlternative Forms of Pull-upnMOS Circuit Model

Exercise 1

nMOS Circuit Design Processes

3.1 nMOS Layers3.2 Stick Diagrams3.3 nMOS Design Rules and Layout3.4 Contact Cuts

3.4.1 Double metal nMOS process rules3.5 General Observations on Design Rules3.6 Layout Diagrams

1144789

13

1415161719202121

23

25283131

32323335394242

in

iv Contents

Exercise 2 43Tutorial 1 45

Chapter 4 Basic Circuit Concepts

4.1 Sheet Resistance Rs 464.2 Sheet Resistance Concept Applied to nMOS Transistors and

Inverters 474.3 Layer Capacitances * 494.4 Standard Unit of Capacitance nCg 504.5 Some Capacitance Calculations 514.6 The Delay Unit x 534.7 Inverter Delays 544.8 Super Buffers 554.9 Driving Large Capacitive Loads 564.10 Propagation Delays in Cascaded Pass Transistors 584.11 Wiring Capacitances 594.12 Choice of Layers ' 60Exercise 3 62

Chapter 5 Subsystem Design and Layout

5.1 Some Architectural Issues 645.2 Switch Logic 665.3 Gate Logic 68

5.3.1 The inverter 685.3.2 Two input Nand gate 695.3.3 Two input Nor gate 73

5.4 Examples of Structured Design (Combinational Logic) 735.4.1 A parity generator 735.4.2 Bus arbitration logic for n line bus 765.4.3 Multiplexers (data selectors) 805.4.4 The red-green (polysilicon-diffusion) function block 835.4.5 A general logic function block 86

5.5 Some Clocked Sequential Circuits - 865.5.1 Two-phase clocking 865.5.2 Charge storage 87

. 5.5.3 A dynamic register element 895.5.4 A dynamic shift register 895.5.5 A ratioless dynamic shift register 90

5.6 Other System Considerations 935.6.1 The precharged bus concept 935.6.2 Current limitations for VDD and GND(V5s) rails 95

, Tutorial 2 96e

Chapter 6 Scaling of nMOS Circuits

6.1 Scaling Factor a 996.2 Some Functional Limitations to Scaling 100

I 6.3 Scaling of Wires and Interconnections 1056.4 Some Aspects of Fabrication 106

Chapter 7 PLAs and Finite State Machines

7.1 Some Thoughts on Combinational Logic 108

: Contents v

7.2 Some Alternatives to Simple Combinational Logic 1087.2.1 Read only memory (ROM) or programmable read only

memory (PROM) realizations of combinational logic 1107.2.2 Multiplexer-based realization of combinational logic 110

7.3 The Programmable Logic Array (PLA) . 1107.4 Finite State Machines 116

7.4.1 A PLA-based finite state machine design example 118Specification __ 118Procedure . 118Some cautionary remarks 121PLA realization of the example 123

Exercise 4 123Tutorial 3 125

Chapter 8 Aspects of System Design .

8.1 Some General Considerations 1278.1.1 Some problems 128

8.2 An Illustration of Design Processes 1288.2.1 The general arrangement of a 4-bit arithmetic processor 1288.2.2 The design of a 4-bit shifter 130

8.3 Summary of Design Processes 134

Chapter 9 Further Consideration and Illustration of the Design Process

9.1 Some Observations on the Design Process 1389:2 Regularity 1389.3 Design of an ALU Subsystem , 139

9.3.1 Design of a 4-bit adder 140Adder element requirements 141

v A standard adder element ' 142Standard cells required for adder element 143Adder element bounding box 145

9.3.2 Implementing ALU functions with an adder 148Exercise 5 154Tutorial 4 154

Chapter 10 Memory and Registers and Aspects of System Timing

10.1 System Timing Considerations 15510.2 Some Commonly Used Storage/Memory Elements 156

10.2.1. The dynamic shift register stage 15610.2.2 A modified lower power dynamic register element 15710.2.3 A three-transistor dynamic RAM cell 15910.2.4 A one-transistor dynamic memory cell 160

'p 10.2.5 A pseudo-static RAM/register cell 162.10.2.6 A JK Flip-Flop circuit 168

Logic gate implementations 171Switch logic and inverter implementation 171Comparison of implementations 171

10.2.7 A D Flip-Flop circuit 17310.3 Forming Arrays of Memory Cells 173

10.3.1 Selection of cells or groups of cells 17410.3.2 Building up the floorplan for a 4 X 4-bit register array 17410.3.3 Selection and control of the 4 X 4-bit register array 17610.3.4 Random access memory (RAM) arrays 184

vi Contents

IAppendixes

Exercise 6 188Tutorial5 188

Chapter 11 Practical Realities and Ground Rules

11.1 Some Thoughts on Performance 18911.2 Further Thoughts on Floorplans/Layout 19011.3 Floorplan Layout of the 4-bit Processor 194

11.3.1 Some realities * 19811.4 Input/Output (I/O) Pads 19811.5 "Real Estate" 20111.6 Further Thoughts on System Delays 205

11.6.1 Buses 20511.6.2 Control paths, selectors, and decoders 20511.6.3 Use of an asymmetric two-phase clock 20811.6.4 More nasty realities 208

11.7 Ground Rules for Successful Design 209

Chapter 12 The Real World of VLSI Design

12.1 Design Styles and Philosophy 22012.2 The Interface with the Fabrication House 222

12.2.1 CIF (Caltech. Intermediate Form) Code 22212.3 CAD Tools for Design and Simulation 225

12.3.1 A basic textual entry layout language 226Design process using BELLE 226Design examples using BELLE 227

12.3.2 A symbolic textual entry layout language and virtualgrid-based design 232The ABCD language 233Brief notes on ABCD 233

12.3.3 Graphical entry layout 23712.4 Design Verification Prior to Fabrication 248

12.4.1 Design rule checkers (DRC) 24812.4.2 Circuit extractors - 24812.4.3 Simulators 249

Channel length modulation 249Velocity saturation 250

12.5 Test and Testability 25012.5.1 System partitioning 25012.5.2 Layout and testability 25112.5.3 Reset/initialization 25112.5.4 Design for testability 25112.5.5 Notes on test and testability 252

Ad hoc testability 252Structured testability 252Self-test circuitry . 253Built-in logic block observation (BILBO) 254

12.6 VLSI Design — The Final Ingredients 256

A1 BELLE Definitions 257A2 Notes on PASCAL 262A3 Parameterized Design Using BELLE 265

Contents v "

A4 Symbolic Design Description Language — ABCD 267B HMOS, Native Transistors, and Super Buffers 281C Color Diagrams (Stick and Layout) for Examples from the Text and

Appendix B 285

Bibliography for General Reading 303

Index 305