Baseband Processing for

Cellular CommunicationLIANG LIU, DEPT. OF ELECTRICAL AND INFORMATION TECHNOLOGY

Our Research (2009-2016)

2

802.11g

DVB

FTN

UPD LTE/LTE-A 5G

ST 28nm FDSOI

R

SROM

FIFOMAC

Input buffer

Coefficient

ROM

MAC

MAC

Multi-tasking

Radio

Infineon

65nm CMOS

DFE Rx

Analog Decoding

Sign-bit

MIMO

ST 65nm

CMOS

Matching Pursuit

Channel Est.

Multi-mode MIMO

Detector

Adaptive CE & QRD

ST 65nm CMOS

Array Processor

R R

R R

R

M

M M

M

Massive MIMO (OFDM-based TDD)

baseband processing

3

Channel

Encoding

Interle

aving

Symbol

Mapping

OFDM

Modulation

Resampling

Filtering

Channel

Encoding

Interle

aving OFDM

ModulationResampling

Filtering

1

K

...

...

Analog

TX

Analog

TX

1

M

...

...

Channel

Decoding

Deinte

rleav

Symbol

Demap

Channel

Decoding

Deinte

rleav

Symbol

Demap OFDM

Demod.Digital

Front-end

1

K

...

...

Analog

RX

...

OFDM

Demod.Digital

Front-end

Analog

RX

Symbol

Mapping

1

M

1

M

MIMO

Precoding

Channel

Estimation

+

MIMO

Detection

Reciprocity

Calibration

Memory

Memory

BU

S (

Rou

ter w

ith

Bu

ffer)

BU

S (

Rou

ter w

ith

Bu

ffer)

Design challenges

4

High computation count: 190×109 multiplication/s for ZF-based MIMO

processing

Low processing latency: 285μs RX-TX turnaround time for moderate mobility

Large data storage: 9.8MB memory for channel matrix

Complicated data shuffling: 11GB/s information exchange for 16-bit wordlength

128×16 massive MIMO system with 20MHz

OFDM processing

5

Channel

Encoding

Interle

aving

Symbol

Mapping

OFDM

Modulation

Resampling

Filtering

Channel

Encoding

Interle

aving OFDM

ModulationResampling

Filtering

1

K

...

...

Analog

TX

Analog

TX

1

M

...

...

Channel

Decoding

Deinte

rleav

Symbol

Demap

Channel

Decoding

Deinte

rleav

Symbol

Demap OFDM

Demod.Digital

Front-end

1

K

...

...

Analog

RX

...

OFDM

Demod.Digital

Front-end

Analog

RX

Symbol

Mapping

1

M

1

M

MIMO

Precoding

Channel

Estimation

+

MIMO

Detection

Reciprocity

Calibration

Memory

Memory

BU

S (

Rou

ter w

ith

Bu

ffer)

BU

S (

Rou

ter w

ith

Bu

ffer)

Mojtaba Mahdavi

Low-latency and area-efficient FFT/IFFT

processor for Massive MIMO

Design Challenges

High complexity ~ M

Low latency ~ Rx-Tx path

6

OFDM processing in Massive MIMO

Design Challenges

High complexity ~ M

Low latency ~ Rx-Tx path

Design Strategy: Utilize the guard-band (zeros) in OFDM

Reduce latency

Enable Extensive hardware sharing: OFDM (de)modulation/Multiple antennas

7

600 Samples 423 424 600 Samples1

2048 Samples

OFDM processing in Massive MIMO

8

IFFT/FFT architecture (pipeline)

Antenna 1 Antenna 1 Antenna 1

Antenna 1 Antenna 1

2048 Samples 2048 Samples 2048 Samples

Latency=2048

IFFT Input

IFFT Output

Mem 1

XkR2BF

Stage1Xin

Mode

2

Mem i-1

R2BFStage i-1

Mem i

R2BFStage i

Mem n-1

R2BFStage n-1

Mem n

R2BFStage n

Antenna 1 Antenna 1 Antenna 1

Antenna 1 Antenna 1

1200 Samples

2048 Samples 2048 Samples 2048 Samples

848 Samples 1200 Samples 848 Samples 1200 Samples 848 Samples

2048 Samples 2048 Samples

Latency=1200

IFFT Input

IFFT Output

9

IFFT/FFT architecture (modified)

0

Xk

Xk+1

0

R2BFStage n

R2BFStage n-1

R2BFStage i

R2BFStage i-1

R2BFStage1

Xin

Mode

2

Extra Cells

Multi-user MIMO detection

10

Channel

Encoding

Interle

aving

Symbol

Mapping

OFDM

Modulation

Resampling

Filtering

Channel

Encoding

Interle

aving OFDM

ModulationResampling

Filtering

1

K

...

...

Analog

TX

Analog

TX

1

M

...

...

Channel

Decoding

Deinte

rleav

Symbol

Demap

Channel

Decoding

Deinte

rleav

Symbol

Demap OFDM

Demod.Digital

Front-end

1

K

...

...

Analog

RX

...

OFDM

Demod.Digital

Front-end

Analog

RX

Symbol

Mapping

1

M

1

M

MIMO

Precoding

Channel

Estimation

+

MIMO

Detection

Reciprocity

Calibration

Memory

Memory

BU

S (

Rou

ter w

ith

Bu

ffer)

BU

S (

Rou

ter w

ith

Bu

ffer)

Hemanth

Prabhu

Massive MIMO detector with flexible

performance-complexity tradeoff

Wei Tang

(University of Michigan)

Downlink precoding

11

Channel

Encoding

Interle

aving

Symbol

Mapping

OFDM

Modulation

Resampling

Filtering

Channel

Encoding

Interle

aving OFDM

ModulationResampling

Filtering

1

K

...

...

Analog

TX

Analog

TX

1

M

...

...

Channel

Decoding

Deinte

rleav

Symbol

Demap

Channel

Decoding

Deinte

rleav

Symbol

Demap OFDM

Demod.Digital

Front-end

1

K

...

...

Analog

RX

...

OFDM

Demod.Digital

Front-end

Analog

RX

Symbol

Mapping

1

M

1

M

MIMO

Precoding

Channel

Estimation

+

MIMO

Detection

Reciprocity

Calibration

Memory

Memory

BU

S (

Rou

ter w

ith

Bu

ffer)

BU

S (

Rou

ter w

ith

Bu

ffer)

Hemanth Prabhu

Low PAPR massive MIMO precoding using

antenna reservation and modified QRD

Enable low-cost analog components

12How can we reduce the requirement on amplifier dynamic range?

Keep these as

inexpensive

as possible

Reducing PA dynamic range with

antenna reservation (concept)

13

Size

M1

Pro

cod

er

Size

M2

Pro

cod

er

Digital front-end

14

Channel

Encoding

Interle

aving

Symbol

Mapping

OFDM

Modulation

Resampling

Filtering

Channel

Encoding

Interle

aving OFDM

ModulationResampling

Filtering

1

K

...

...

Analog

TX

Analog

TX

1

M

...

...

Channel

Decoding

Deinte

rleav

Symbol

Demap

Channel

Decoding

Deinte

rleav

Symbol

Demap OFDM

Demod.Digital

Front-end

1

K

...

...

Analog

RX

...

OFDM

Demod.Digital

Front-end

Analog

RX

Symbol

Mapping

1

M

1

M

MIMO

Precoding

Channel

Estimation

+

MIMO

Detection

Reciprocity

Calibration

Memory

Memory

BU

S (

Rou

ter w

ith

Bu

ffer)

BU

S (

Rou

ter w

ith

Bu

ffer)

Hemanth Prabhu

Pre-compensating I/Q imbalance for

massive MIMO

Model of IQ imbalance

15

Assumingperfect receiver (Rx) chain

1. How dose IQ imbalance affect massive MIMO system?

2. Can we mitigate IQ imbalance in an efficient way?

Compensating IQ-imbalance

16

Item Value

Process ST 28nm

Power 0.61mW

Latency 2clk @

200MHz

Gate count 24k

Large diagonal elements.

Can be efficiently

implemented as a Jacobi

iterative solver

One instance per antenna

Compensating IQ-imbalance

17

Simulated IQ imbalance with mean value

6% amplitude and 6 degree phase imbalance

(random on antennas)

Memory subsystem

18

Channel

Encoding

Interle

aving

Symbol

Mapping

OFDM

Modulation

Resampling

Filtering

Channel

Encoding

Interle

aving OFDM

ModulationResampling

Filtering

1

K

...

...

Analog

TX

Analog

TX

1

M

...

...

Channel

Decoding

Deinte

rleav

Symbol

Demap

Channel

Decoding

Deinte

rleav

Symbol

Demap OFDM

Demod.Digital

Front-end

1

K

...

...

Analog

RX

...

OFDM

Demod.Digital

Front-end

Analog

RX

Symbol

Mapping

1

M

1

M

MIMO

Precoding

Channel

Estimation

+

MIMO

Detection

Reciprocity

Calibration

Memory

Memory

BU

S (

Rou

ter w

ith

Bu

ffer)

BU

S (

Rou

ter w

ith

Bu

ffer)

Yangxurui Liu

Parallel memory for massive MIMO with

data compression technique

Memory subsystem in Massive MIMO

High capacity and throughput

Channel matrix 128×16 in

massive MIMO v.s. 4×4 in LTE-A

Multiple access patterns

Column wise：HHH

Row wise: Hy

Diagonal wise: HHH+αI

Adjustable operand matrix size

19

HH

H/HH

H+αI/(HH

H+αI)-1

(K×K)

Conflict-free parallel memory scheme

20

Permutation Network

Memory

Bank01 2 15

Inverse-Permutation Network

read

Permutation

Pattern Generate

Unit

write

2048x32

Address

Generate Unit

Control Logic

v2v0 v1 v15

row

column

diagonal

116 2 3 4 5 6 7 8 9

116 2 3 4 5 6 714 15

116 2 3 4 512 13 14 15116 2 310 11 12 13 14 15

1168 9 10 11 12 13 14 156 7 8 9 10 11 12 13 14 154 5 6 7 8 9 10 11 12 132 3 4 5 6 7 8 9 10 11

1 1623456789234567891011456789101112136789101112131415

1 16 891011121314151 1623 101112131415

1 162345 121314151 16234567 1415

116 2 3 4 5 6 7 8 9116 2 3 4 5 6 714 15

116 2 3 4 512 13 14 15

8index of target

memory module

Case study: hardware implementation of

a 16-bank architecture

Capacity 128kB: 15 subcarriers of 128×16 MIMO system

Row/Column/Diagonal (16 elements) access in one clock cycle

0.28 mm2 in ST 28nm technique

64 GB/s Throughput@1 GHz Frequency

Power consumption

197mW @write

246mW @fetch

21

What can be done to reduce the memory area?

Exploiting the sparsity in massive

MIMO channel

22

Distribution of angle of arrival signals at base station

(Real measured result with linear array of 128 antenna elements)

LOS scenario NLOS scenario

FFT-based channel data compression

23

NLOSLOS

Data shuffling network

24

Channel

Encoding

Interle

aving

Symbol

Mapping

OFDM

Modulation

Resampling

Filtering

Channel

Encoding

Interle

aving OFDM

ModulationResampling

Filtering

1

K

...

...

Analog

TX

Analog

TX

1

M

...

...

Channel

Decoding

Deinte

rleav

Symbol

Demap

Channel

Decoding

Deinte

rleav

Symbol

Demap OFDM

Demod.Digital

Front-end

1

K

...

...

Analog

RX

...

OFDM

Demod.Digital

Front-end

Analog

RX

Symbol

Mapping

1

M

1

M

MIMO

Precoding

Channel

Estimation

+

MIMO

Detection

Reciprocity

Calibration

Memory

Memory

BU

S (

Rou

ter w

ith

Bu

ffer)

BU

S (

Rou

ter w

ith

Bu

ffer)

Dimitar

Nikolov

Steffen

Malkowsky

Data shuffling network with dedicated

time scheduling

Data shuffling in Massive MIMO

(uplink example)

25

18161 2 3 4

0

600

1,200

UE index

RLC index

Su

bca

rrie

rs

1641281 2 3 4

0

600

1,200

BS antennas

# of RLC

Sub

carr

iers

8.5GB/s1GB/s

Data shuffling network (uplink example)

26

M-in K-out

Router

...

N-in M-out

Router

...

N-in M-out

Router

...

...

N-in M-out

Router

M-in K-out

Router

...

...

......

...

...

M-in 1-out

Router

M-in 1-out

Router

...M-in 1-out

Router

...

...

...

......

OFDM MIMO UE Dec

…

ROUTETABLE

z-1

…

CHECKROUTE

SUCCESS

INCRE-MENT

ADDRESS

Nin

route success?

Mou

t

Conclusions

• Critical design challenge for massive MIMO baseband processor

• Low-latency FFT/IFFT

• Adaptive MIMO detection and low-complexity precoder

• Parallel memory with data compression

• DSP enables low-cost hardware

• Possible to have an integrated baseband processor

27

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