Low-Power and Area-Efficient Carry Select Adder Using Modified BEC-1 Converter

L.Mugilvannan1 S.Ramasamy

2

1 mugilvannan.4@gmail.com M.E APPLIED ELECTRONICS RMK Engineering college chennai

2 srs.ece@rmk.ac.in Department of ECE RMK Engineering college chennai

Abstract -Carry Select Adder (CSLA) is one of the fastest adders

used in many data-processing processors to perform fast

arithmetic functions. From the structure of the CSLA, it is clear

that there is scope for reducing the area and power consumption

in the CSLA. This work uses a simple and efficient transistor-

level modification in BEC-1 converter to significantly reduce the

area and power of the CSLA. Based on this modification 16-b

square-root CSLA (SQRT CSLA) architecture have been

developed and compared with the SQRT CSLA architecture

using ordinary BEC-1 converter. The proposed design has

reduced area and power as compared with the SQRT CSLA

using ordinary BEC-1 converter with only a slight increase in the

delay. This work evaluates the performance of the proposed

designs in terms of delay, area, and power by hand with logical

effort and through Cadence Virtuoso. The results analysis shows

that the proposed CSLA structure is better than the SQRT CSLA

with ordinary BEC-1 converter.

Keywords-; (Binary to Excess-1 converter,Low power,Area

Efficient,CSLA)

I. INTRODUCTION

Design of area- and power-efficient high-speed data path logic

systems are one of the most substantial areas of research in VLSI

system design. In digital adders, the speed of addition is limited by

the time required to propagate a carry through the adder. The sum for

each bit position in an elementary adder is generated sequentially

only after theprevious bit position has been summed and a carry

propagated into the next position.

The CSLA is used in many computational systems to alleviate the

problem of carry propagation delay by independently generating

multiple carries and then select a carry to generate the sum .However,

the CSLA is not area efficient because it uses multiple pairs of Ripple

Carry Adders (RCA) to generate partial sum and carry by considering

carry input cin = 0 andcin = 1, then the final sum and carry are

selected by the multiplexers (mux).The power and Area of the Carry

select Adder can be reduced by using BEC-1 converter instead of

Ripple Carry Adder(RCA).

The basic idea of this work is to use transistor level modified Binary

to Excess-1 Converter (BEC) instead of Ordinary BEC(gate level)

with cin = 1 in the CSLA to achieve lower area and power

consumption . The main advantage of this transistor level modified

BEC-1 comes from the lesser number of MOS transistor than the

Ordinary BEC-1.

II.BEC

As stated above the main idea of this work is to use transistor level

modified BEC instead of the ordinary BEC with cin=1 in order to

reduce the area and power consumption of the CSLA. To replace the

n-bit ordinay BEC, an n-bit transistor level modified BEC is

required.The function table of a 3-b BEC are shown in Table I.

TABLE-I

FUNCTION TABLE OF THE 3-B BEC

INPUT[0:3]

OUTPUT[0:3]

000 001

001 010

010 011

011 100

100 101

101 110

110 111

111 000

Fig. 1 illustrates how the basic function of the CSLA is obtained by

using the 4-bit BEC together with the mux. One input of the 8:4 mux

gets as it input (B3, B2, B1, and B0) and another input of the mux is

the BEC output. This produces the two possible partial results in

parallel and the mux is used to select either the BEC output or the

direct inputs according to the control signal Cin. The importance of

the BEC logic stems from the large silicon area reduction when the

CSLA with large number of bits are designed.

III. 16-B SQRT CSLA USING ORDINARY BINARY TO EXCESS-

1 CONVERTER

The structure of the 16-b SQRT CSLA using ordinay BEC for RCA

with cin=1 to optimize the area and power is shown in Fig. 2 We

again split the structure into five groups. The Power and area

estimation of each group ordinary BEC and Mux are shown in Fig.3

.

IEEE - 31661

4th ICCCNT 2013 July 4-6, 2013, Tiruchengode, India

Fig. 1. 4-b- BEC With 8:4 MUX

Fig. 2. 16-b SQRT CSLA. The parallel RCA with Cin = 1is

replaced with BEC.

1) The Fig. 3 has transistor level design of 3-b BEC and 6:3

Mux.The ordinary 3-b BEC is used in CSLA for reducing the power

and area of the adder.The total number of PMOS and NMOS

transistor in the 3-b BEC and MUX are 42 and 42

Fig. 3 Transistor level design of ordinary 3-b BEC and 6:3

Mux

Similarly the ordinary 4-b BEC and 8:4 Mux,5-b BEC and 10:5

Mux ,6-b BEC and 12:6 Mux has been designed in transistor level .

The Table-II shows the number of Mos transistors required for

various bits of BEC and MUX.

TABLE-II

TOTAL MOS TRANSISTORS OF ORDINARY BEC AND MUX

IV. 16-B SQRT CSLA USING TRANSISTOR LEVEL MODIFIED

BINARY TO EXCESS-1 CONVERTER

The structure of the proposed 16-b SQRT CSLA is same as Fig.2.In

that Structure the BEC and MUX circuits has been modified at

transistor level to optimize the area and power.The Power and area

estimation of each group modified BEC and Mux are shown in Fig.4

1) The Fig. 4 has transistor level design of 3-b BEC and 6:3

Mux.The Transistor level modified 3-b BEC is used in CSLA for

reducing the power and area of the adder.The total number of PMOS

and NMOS transistor in the 3-b BEC and MUX are 34 and 34

Fig. 4 Transistor level Modified design of 3-b BEC and 6:3 Mux

Similarly the transistor level modified 4-b BEC and 8:4 Mux,5-b

BEC and 10:5 Mux ,6-b BEC and 12:6 Mux has been designed.The

Table-III shows the number of Mos transistors required for various

bits of Modified BEC and MUX.

Groups No of PMOS

Transistors

No of NMOS

Transistors

Total no of

MOS

Transistors

Group2(3-b

BEC and

6:3 mux)

42 42 84

Group3(4-b

BEC and

8:4 mux)

59 59 118

Group4(5-b

BEC and

10:5 mux)

76 76 152

Group5(6-b

BEC and

12:6 mux)

93 93 186

Total no of

MOS

Transistor

270 270 540

IEEE - 31661

4th ICCCNT 2013 July 4-6, 2013, Tiruchengode, India

TABLE-III

TOTAL MOS TRANSISTORS OF MODIFIED 3-B BEC

Groups No of PMOS

Transistors

No of NMOS

Transistors

Total no of

MOS

Transistors

Group2(3-b

BEC and 6:3

mux)

34 34 68

Group3(4-b

BEC and 8:4

mux)

48 48 96

Group4(5-b

BEC and

10:5 mux)

62 62 124

Group5(6-b

BEC and

12:6 mux)

76 76 152

Total no of

MOS

Transistor

220 220 440

Comparing Tables II and III, it is clear that the proposed Transistor

Level modified BEC and MUX Circuits saves 100 MOS Transistors

than the Ordinary BEC and MUX, with only increases in delays.

V. IMPLEMENTATION RESULTS

The design proposed in this paper has been developed using Cadence

Virtuoso using typical libraries of gpdk 0.18 um technology.The

Current flowing through the circuit can be measured for the input

combination .Then the power can be calculated using the current and

the voltage required for the the circuit.The similar design flow is

followed for both the ordinary BEC-MUX and modified BEC-MUX.

Table IV exhibits the implementations results of both the BEC-MUX

structures in terms of delay, area and power. The area indicates the no

of MOS transistors used and the total power indicates the maximum

power in the circuit. The Delay can be measured in terms of the

maximum time taken by the circuit to produce the all outputs for the

given inputs.

TABLE-IV

Area(No of

MOS

transistors)

Peak

current

(uA)

Power

(mw)

3-b BEC

and MUX

Regular

84 561.269 1.0102

Modified

68 485.186 0.8733

4-b BEC

and MUX

Regular

118 737.533 1.3275

Modified

96 623.868 1.1229

5-b BEC

and MUX

Regular

152 900.154 1.6202

Modified

124 765.430 1.3777

6-b BEC

and MUX

Regular

186 1.05962 1.9073

Modified

152 905.330 1.6295

The reduction in power consumption of modified 3-b BEC-MUX is

13.55%,4-b BEC-MUX is15.41%, 5-b BEC-MUX is 14.97%, and 6-

b BEC-MUX is 14.57. The delay overhead for the 3,4,5 and 6-b

BEC-MUX circuit is 31.06%.

VI.PROCESS VARIATION ANALYSIS

The process Vatiation analysis of 3-b BEC & MUX,4-b BEC &

MUX ,5-b BEC & MUX,6-b BEC & MUX has been done by using

virtuoso analog design environment.The Virtuoso Analog Design

Environment is used for transient analysis of 3-b BEC and MUX,4-

b BEC and MUX,5-b BEC and MUX ,6-b BEC and MUX with the

period of 200ns.

The parametric analysis of both modified and ordinary 3-b BEC and

MUX using Virtuoso Analog Design Environment with

temperature range between -60 to 120 and voltage range between

1.35 to 2.25 has been done.The parametric analysis waveform of

ordinary 3-b BEC and MUX using Virtuoso Analog Design

Environment with temperature range between -60 to 120 and

voltage range between 1.35 to 2.25 as shown in the FIG 5.The same

criteria is used for all the BEC and MUX circuits for process

analysis.

Fig. 5. Parametric analysis waveform of ordinary 3-b bec and mux

The Process variation results is used to analysis the delay information

of the BEC and MUX circuits.The process variation comparison table

between ordinary 3-b BEC & MUX and modified 3-b BEC & MUX

as shown in the TABLE-V.

Similarly the process variation result is also obtained for 4-b BEC &

MUX,5-b BEC & MUX and 6-b BEC & MUX.In the Table-V the

delay can be measured with temperature range between -60 to 120

and voltage range between 1.35 to 2.25.

IEEE - 31661

4th ICCCNT 2013 July 4-6, 2013, Tiruchengode, India

TABLE-V PROCESS VARIATION RESULT FOR 3-B BEC

Process

variation

NN FF FS SS SF

Delay(ns)

Delay(ns)

Delay(ns)

Delay(ns)

Delay(ns)

ORD

3-b

BEC

MOD

3-b

BEC

ORD

3-b

BEC

MOD

3-b

BEC

ORD

3-b

BEC

MOD

3-b

BEC

ORD

3-b

BEC

MOD

3-b

BEC

ORD

3-b

BEC

MOD

3-b

BEC

TE

MP

=-

60

°c

1.35 1.04 1.77 0.88 0.90 0.98 1.15 1.29 0 1.10 0

1.515 0.93 0.97 0.81 0.79 0.87 0.86 1.09 3.02 1.00 1.32

1.8 0.86 0.85 0.79 0.74 0.81 0.76 0.98 1.06 0.92 0.95

2.025 0.83 0.78 0.78 0.72 0.77 0.71 0.90 0.91 0.88 0.88

2.25 0.81 0.75 0.76 0.69 0.74 0.68 0.88 0.83 0.87 0.81

TE

MP

=

-1

5°c

1.35 1.08 1.47 0.92 0.91 1.03 1.11 1.34 0 1.16 0

1.515 0.97 0.98 0.85 0.82 0.91 0.87 1.14 1.98 1.03 1.33

1.8 0.90 0.87 0.82 0.77 0.84 0.79 1.01 1.08 0.96 1.00

2.025 0.86 0.81 0.80 0.74 0.78 0.74 0.94 0.93 0.91 0.91

2.25 0.83 0.77 0.79 0.72 0.76 0.70 0.90 0.86 0.88 0.85

TE

MP

=

30

°c

1.35 1.12 1.38 0.94 0.94 1.06 1.11 1.38 0 1.19 0

1.515 1.01 1.02 0.88 0.85 0.94 0.90 1.17 1.76 1.07 1.36

1.8 0.93 0.90 0.83 0.79 0.86 0.81 1.07 1.11 1.00 1.05

2.025 0.88 0.83 0.82 0.75 0.83 0.76 0.99 0.97 0.95 0.94

2.25 0.86 0.79 0.80 0.74 0.80 0.74 0.94 0.89 0.92 0.88

TE

MP

= 7

5°c

1.35 1.15 1.37 0.98 0.97 1.09 1.11 1.41 0 1.24 0

1.515 1.04 1.05 0.91 0.87 0.97 0.92 1.22 1.71 1.09 1.40

1.8 0.96 0.94 0.86 0.83 0.89 0.84 1.09 1.15 1.03 1.09

2.025 0.91 0.88 0.84 0.79 0.85 0.78 1.02 1.01 0.98 0.99

2.25 0.89 0.81 0.83 0.76 0.82 0.75 0.96 0.93 0.94 0.92

TE

MP

= 1

20

°c

1.35 1.18 1.37 1.01 1.00 1.10 1.13 1.45 0 1.27 0

1.515 1.06 1.08 0.94 0.90 0.99 0.96 1.26 1.70 1.14 1.47

1.8 0.99 0.97 0.89 0.86 0.91 0.86 1.14 1.20 1.07 1.11

2.025 0.94 0.90 0.87 0.82 0.88 0.82 1.04 1.05 1.01 1.02

2.25 0.90 0.85 0.85 0.77 0.85 0.77 1.01 0.95 0.98 0.96

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VII. CONCLUSION

A simple approach is proposed in this paper to reduce the area and

power of BEC-MUX architecture. The reduced number of transistors

of this work offers the great advantage in the reduction of area and

also the total power. The compared results show that the modified

BEC-MUX has a random variation in delay but the power of the

modified BEC-MUX are significantly reduced by 14.70%.The BEC-

MUX circuit should be a part of the CSLA.The transistor level

modified BEC-MUX circuit can be used in CSLA instead of ordinary

BEC-MUX circuit the greater power consumption can be achieved.

The modified BEC-MUX architecture is therefore, low area, low

power, simple and efficient for VLSI hardware implementation.

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