Barry's American system-307 Nano Motherboard Architecture ......The Visual Model Super Sonic 307 Motherboard 1-A General View overall view of the product and demonstrates a Industrial

Barry's American system-307 Nano Motherboard Architecture Design 5th Generation

by

Barry L. Crouse

Introduction

I have made improvements on the SS-285 Motherboard Design (copyrighted). I have finished the final roll out of this project. Most of the hardware components are now Nano based. This means using superconductivity material such as graphene and deploying carbon nano tubes for the purpose of using nano bits and bytes. The updates include the following hardware that use BIOS, CPU, CMOS, Memory chips, Time scale(fractional time), menu screens, Network adapters, controllers. They now have the capability of using nanobits and Nano bytes with micro time scales. the conversion . The voltage and terminator blocks now use platinum base contacts boiling point for platinum is 3200 degrees Fahrenheit.

a). CPU's have two regular processors and two shadow copies updatedb). Nano CPU Crypt generator is Independent and has Direct memory access to memory

b). Memory is now Nano based and has a boot menu screen configuration in n bits c). Boot menu screens updated see Version 1.5. d). Nano Cryptographic Energy Model introduced 1800 – 2100 series four dimensional

object model. e). Built in Certificate is now Nano based with Direct Nano Memory Access. f). System fan now has nano based password control features. g). Crypt Model 1800 -2100 now has the ability to process 281 trillion cycles/ 6 paths.

h). Crypt Model 1800 – 2100 has a address registry final product design. I). Boot menu screens password control on NanoBios and Hardware Components. J). Major Hardware Components now are nano Based with Direct memory access. K). Adapters and connectors now have a Independent and dependent paths of choice. L). Battery is now nano Based represented by √1 , √0 compressed bits.

M). ROM Chip is Now Nano Based with direct memory access. N). Password Encryption updated to allow for 8796 masked nano Characters

O). Video slot and fan now use strictly carbon nano tubes with the crypt 1800-2100 modelp). Voltage Regulator is platinum base contacts and uses thicker wires 16384 bits per wire total 16384 bits 8 wires for a total of 131072.

1). The Visual Model Super Sonic 307 Motherboard 1-A General View overall view of the product and demonstrates a Industrial Design because of it’s unique characteristics. The detailed features that are within the Design accompanies in views 1-a through 11-A with detailed specs. The features of this design comes with CPU's. 1 and 2 are the main core of processing 3 and 4 are secured boots shadow copies of 1 and 2 . CPU 1 for instance can load the 131072 Architecture and CPU 2 can load the 65536 with shadow copies stored for both. The BIOS has been updated to version 1.5 and also reflects the structure of the CPU Architecture and Design in nano bits converted to characters utilizing the Crypt Model 1800-2100 masked. I have created a boot screen menu with this design and customization features. Version 1.5 . CMOS is now strictly nano based. The Nano CPU's can use up to 131072 nano bit architecture also upgrades the SS-285 copyrighted design as well. The self crypt CPU generator is independent from the general CPU and has direct memory access. I have updated the Nano password length up to 35184 nano characters masking one character with four characters producing 8796 nano characters. Major components that are either adapters

and connectors now have the ability to use either direct memory access or utilize the CPU regular processing Independent means free from CPU processing dependent also hardware devices can be configured to utilize CPU resources if desired.

2). New Cryptographic Energy Model Design-Crypt 1800-2100 model. The model employs afour dimensional object and employs Nano based material to process nano bits and nano bytes. This comes with dynamic bit data strings, linear and dual curvature elliptic circles in dimensional spaces with non singular elliptic and multiple events shelled within a shell principle. The design has been upgraded in this version to process over 281 trillion cycles, 3 external circular- 1st dimension, 6 paths toaccess the Internal cube 2nd dimension. The main idea here is that most hardware components can nowhave a Individual Password Independent from the main motherboard or you can just have one password; User's choice, The Hardware components also have direct memory access bypassing CPU's including the Crypt Generator. This Cryptographic model for the most part has been completed.

3). I have created a nano based cryptographic switch and password security to access it

4). Built in Hardware Certificate now includes the Crypt 1800-2100 Model in nano's Shadow copy and direct memory access .

5). The NanoBios screen time scale is represented in nano time ¼/ magnetic spin or fractional time also it is listed under the updated address register.

6). The Address Registry has been updated to 23 spaces with a structured address scheme on and off switch control and a private key creating a dual security method. Asymmetrical in

the first even and symmetrical in the second event.

Please note this completes the Nano Motherboard project for the year 2020.

Table of Contents

1). Visual Design and Components for SS-307 Nano Motherboard

2). System Software Interface for SS-307 Nano Motherboard

3). Cryptographic 1800 -2100 Energy Model Design

4). Final Update Nano Motherboard Architecture Design

Visual Design and Components of Nano Motherboard

Chapter 1

Model SS-307 Nano CPU Motherboard- Design 1-A General View

External Hard Drive Controllers 1-3 nano CPU CMOS Voltage Regulator Rom 4/5 pin BIOS 2-4 Nano CPU CMOS BIOS Buffer Chip Optical lens Fiber Optic wire nano battery Nano

24*2 dual Video Public Private Network Public Private Memory Nano Crypt CPU Fan slot adapters Sound adapters 5 slots CPU Generator Platinum Internal Network Switch

Internal hard drive Connectors External Device Connectors Nano CPU 1-3, 2-4 Terminator Block

Model Super Sonic 307 Nanotube memory General View 2-A 6 7 9 1 5 2

8 4

1). Fitting to hold Memory Chips2). Carbon Nanotubes3). Fiber Optic hexagon ¼ magnetic spin4). Carbon nanotubes 5). Sub level address switch refer to crypt model chapter ¼/ magnetic spin6-8). Carbon Nanotube9). Platinum metal contacts for switch

3

Model Super Sonic 307 Nano CPU and Topology Design General Side View 3-A

1-3

2-4

3

41). CPU 1 Processor – 3 secured boot Graphene 131072 nanobits2). CPU 2 Processor - 4 secured boot Graphene 131072 nanobits3). Carbon nanotubes4). Platinum contacts

Model Super Sonic 307 Nano CPU and Topology Design General Front View 4-A

CPU 1-3

1

2

4

CPU 2-4

3

1). CPU 1 nano regular - 3 nano secured boot Graphene 131072 nanobits2). CPU 2 nano regular -4 nano secured boot Graphene 131072 nanobits3). Carbon nanotube4). Platinum Contacts

Model SS-307 131072 nanobit CPU 5-A

4

1

2

3

4

1). Graphene Nano based material 52). Node Points for paths and controlling Atoms3). Nano CPU 1-3 Nano Regular , 2-4 Secured boot Fitting4). 131072 nanobit CPU5). Platinum contacts

Model Super Sonic 307 5th generation Industrial Video /Fan Idea 6- A General View

14

12 13

4 3 2 1 5 6

9

10 7 8 1). Public Video Area Crypt 1800-2100 model2). Private Video Area Crypt 1800-2100 Model3). Shared Video Area Crypt 1800-2100 Model4). Reserved Video Area Crypt 1800-2100 Model5). Video Data Bride 4 slots6). Public Data String carbon nano tube7). Platinum video fitting8). Shared Data String carbon nano Tube9). Private Data String Carbon nano Tube10). Reserved Area Carbon Nano Tube11). Node Points (End to End point connection)12). Crypt 1800-2100 Model Nano energy regeneration 13). Carbon Nano tube 14). Graphene nano Material

Model Super Sonic 307 5th Generation Industrial Video slot specs Idea 7-A General View

3 2 4 1

7

8 6 5

1 Public Data String Crypt 1800-2100 Model 2 Private Data String Crypt 1800-2100 Model3 Shared Carbon Nano Tube Crypt Model 1800 - 2100

4 Reserved Carbon Nano Tube Crypt Model 1800 -2100 5 Public Video Slot 6 Private Video Slot 7 Shared Video Slot 8 Graphehe Based Video Fan

Model Super Sonic 307 5th Generation Industrial Idea 8-A General View

Voltage Regulator 8 wire Check

4 3

5 1

2

6

1). Overall view of chip2). 8 thicker wires inside chip to check flow of voltage a). 16384 bits per wire total 131072 bits3). Node Point check testing wires for on and off conditions4). Terminator Block Platinum metal contacts5). Platinum metal contact for 8 wires6). Platinum metal contact

Model Super Sonic 307 Industrial BIOS Idea 9-A General View

4/5 Pins BIOS

1 2 3 4

5 6 7

1). Carbon Nano tube CPU 1 2). Carbon Nano tube CPU 23). Carbon nano tube CPU 3 Copy of CPU 1 secured boot4). Carbon Nano tube CPU 4 Copy of CPU 2 secured boot6). BIOS Pin Clearing areas of spaces7). Platinum metal contact

Model Super Sonic 307 5th generation Industrial ROM Chip Idea 10-A General View

Nanobit Model Built in Certificate ROM Chip

1

2

1). Nano CPU 1 Certificate 131072 n bits2). Nano Shadow Copy of Certificate

Model Super Sonic 307 5th Generation Industrial Rom Chip specs Idea 11-A General View

Barry's Scientific Based Products Encrypted -Crypt 1800-2100 Model

This Certificate is used to check for authenticated Hardware updates it is built into the motherboard via ROM Chip to access the Certificate 131072 bits.

System Software Interface for SS-307 nano Motherboard

Chapter 2

Barry's Scientific Based Products Ver 1.5

Nano Main Menu Screen 1-A

Nano Date xxxx /xxxx / xxxx Time xxxx :xxxx :xxxx

Month Date Year nano Hours Minutes seconds

1). Nano CPU 1 10). Nano SS-307 Password (8 to 8796 masked Characters)

2). Nano CPU 2

3). Nano CPU 3 secured boot Copy of nano CPU 1

4). Nano CPU 4 secured boot Copy of Nano CPU 2

5). Nano Memory Configuration 2-A

6). Nano battery Configuration 3-A

7). Nano BIOS Configuration 4-A

8). Nano Hardware configuration 5-A

9). System Fan Password control

Barry's Scientific Based Products Version 1.5

Nano memory Configuration Menu Screen 2-A

Date xxxx / xxxx / xxxx Time xxxx :xxxx :xxxx

Month Date Year Nano Hours Minutes seconds

1). 8192 n bits Memory Null Space (0 Characters)

2). 12288 n bits Memory address representation (8 Characters)


4). 32768 n bits Memory address representation (549 Character)

5). 65536 n bits Memory address representation (total 4398/2 = character 2199 masked)

6). 131072 N Bits Memory Address representation ( total 35184/4 = 8796 masked)


Nano Battery Configuration Menu Screen 3-A







5). 65536 n bits memory address representation (4398/2 =2199 masked characters)

6). 131072 n bits memory address representation (35184/4 = 8796 masked characters)

7). Nano Battery

a). Regular CPU Processing

b). Nano Direct Memory Address Processing


Nano BIOS Configuration Menu Screen 4-A







5). 65536 n bits Memory address representation (4398/2= 2199 masked characters)

6). 131072 n bits Memory address representation (35184/4= 8796 masked characters)

7). BIOS 1

a). Password Control “y or n” b). Regular Processing “y or n” c). Direct memory Addressing “y or n”

8). 5) BIOS 2

a). Password Control “y or n” b). Regular Processing “y or n”

c). Direct memory Addressing “y or n”


Nano Hardware Configuration Menu Screen 5-A







5). 65536 n bits Memory address representation (4398/2 = 2199 masked characters)

6). 131072 n bits Memory Address representation (35184/4 = 8796 masked characters)

7). Rom Chip


c). Direct memory Addressing “y or n” d). Shadow Copy “y or n”

8). Internal Hard Drive Controllers


c). Direct memory Addressing “y or n”

9). Network Adapters

a). Password Control “y or n” b). Public IP Address “y or n”

c). Private IP Address Addressing “y or n”d). Direct memory addressing “y or n”

10). CPU Crypt Generator


c). Direct Memory Addressing “y or n”

11). Public Private Sound Adapters

a). Password Control “y or n” b). Public IP Address “y or n”

c). Private IP Address Addressing “y or n” d). Direct memory addressing “y or n”

12). External Device Connectors


13). Internal Network Switch


14). External Hard Drive Controllers



Nano System Fan password Configuration Menu Screen 6-A



1). 8192 n bits Video password (no password)

2). 12288 n bits Memory ( 8 Characters)

3). 16384 n bits Memory ( 68 Characters)

4). 32768 n bits memory (549 Characters)

5). 65536 n bits Memory (4398/2 = 2199 masked characters)

6). 131072 n bits Memory (35184/4= 8796 masked characters)

Technical Description and Details of BIOS Screens

I would now like to over the screens. The nano BIOS screens have been updated version 1.5. CPU 1,3 and 2,4 have regular and secured boot with the amount of nano bits for the user to select. This allows for 2 different Operating systems with the BIOS hardware configuration.

The secured CPU 3 and 4 are copies of CPU 1 and 2. The built in nano Certificate is specifically configured for the system and now has direct memory access. Memory configuration allows for backward compatibility and for the ability of character flow control example 12288 = 8 characters while 131072 allows for 35184/4 masked characters total 8796 characters on a micro scale. Hardware components that use nano bits come with a Independent password with the thought that one size does not fit all. This is used to enhance security for nano based hardware components. Version 1.5 allows for a basic BIOS password but also allows for different passwords on each hardware device that use Nano bits. The following now has Direct Memory address Independent from CPU Processing and is present on version 1.5 Nano BIOS

1). Battery represented in nano bits compressed √1 and √o off and on2). ROM Chip3). Internal hard drive controllers4). Network Adapters5). CPU Crypt Generator6). CPU Fan7). Video slot8). Public Private Network adapters9). Public Private sound adapters10). External Device connectors11). External Hard Drive Controllers

Cryptographic 1800 -2100 Energy Model Design

Chapter 3

Crypt 1800 -2100 Using 4D Object and Space Time

8 9 3 4 1

6

5

12 2 10 11

7

1). 1st dimension Cube x = 2). 2nd Dimension Cube 3). Graphene nano bits 4). 1st external cube circle = 16384 n bits = 16384/.125 = 131072 nanobytes5). 2nd external cube circle = 16384 n bits = 16384/.125 = 131072 nanobytes6). Paths for Nano Bytes taken 7). Nano Bit Packet8). 2nd Internal Cube Circle Path convergence √x * x(4th power)9). 2nd Internal Cube Alternate Path non dependent √x * x(2nd power)10). 2nd Internal Cube Alternate Path Dependent √x * x(2nd power)11). nano packet final formation 12). 3rd External Circle = 32768 n bits = 262144 = nanobytes

Nano Cryptographic 1800-2100 Energy Model Design Method and Process

I will now present a updated Cryptographic Energy Design based on Dynamic Heat and Asymmetrical Energy principles and applications. I will be discussing the method and process of this model

As you can see the new Cryptographic model has been updated , I have redesigned the Cryptographic Energy Model using NanoBits and nanobytes but it utilizes four dimensional space time with the circular spaces assigned to the External Cubes and Internal Cubes. The assignment of variables for the circular object is external cube variable is x (2 x and 4x). The Internal cube with the convergence circle where the paths converged is assigned 4 paths thereby uses the 4th power in Mathematics the Internal Independent and dependent cubes use √x and x(2nd power) and has no convergence paths so it is assigned the 2nd power with nano packets formed at the Internal cubes final path. The 3rd External cube can take on two different forms because it has a path to both Independent and dependent path to represent this quark you would have to use 3rd internal = √x * x(2nd power). If you are looking at the screen it is on the left side one internal cube that can either use either Independent or dependent paths. two events 1 outcome. I have added more Internal circles creating a total of four within the 2nd dimension. The design has within the Internal cube circles Independent and dependent paths. This demonstrates Dynamic energy along with Asymmetry principles This allows for compression and expansion in the same event on one time line also controlling the atomic energy flow. In this instance using the number √65536 I can compress this and receive a perfect square of 256 and if I exponentiate this to the 2nd power 256 * 256 = 65536. In another observation, If I use a + b = c I havea balanced equation 65536 + 65536 = 131072 c = 131072 so 131072 = 131072 this establishes a balanced equation on the surface but if I compress and expand in the same event c I received the following:√131072 = 362.038671968 √131072 = 362.038671968 * 362.038671968 = 131072.000000353 non perfect square 1st instance so a + b not equal to c this implies a discreet mathematical difference using multiple events on one time line. This opens the door to dimensional and discreet mathematics that were never brought to bear fruit in the past . Please understand this shows and supports the ideas discussed in this paragraph Dynamic and Asymmetrical energy Because the 3rd External Cube uses 32768 I will compress this

√32768 = 181.019335984 √32768 = 181.019335984 * 181.019335984 = 32768.000000088 non perfect square 2nd instance

131072.000000353 non perfect square 1st instance 32768.000000088 non perfect square 2nd instance

I have three external circular cubes. The assignment is x= 16384/.125=131072, 2x=16384/.125= 131072 , 3x = 32768/.125 = 262144 linear based with 6 paths in Nanobytes. Please note the geometric shape provides many ways to reach the Internal Cube called paths. I may also use these multiple paths to create additional assignment of nanobits and nanobytes. If you notice I can establish equality in this instance x=2x

The 1st External curvature uses a prime number of 2017 nanobits= 2017/.125=16136 nanobytesand the 2nd uses 2063/.125 = 16504 nanobytes. The 3rd External cube uses 2099 /.125=16792 for a total of 49432 nanobytes . Depending on the number of cycles used examples 43 , 47, 53 I can set up the following table

X= 43 * 16136 = 693848 nanobytes 2x 47 * 16504 = 775688 nanobytes3x 53 * 16792 = 889976 nanobytes

Total = 693848 + 775688 + 889976 = 2359512 nanobytes.

1st External Curvature Dimension total = X1 = 2359512 = nanobytes1st External Linear Path =X2 = 3145728 =nanobytes (3145728/6=524288) linear solution 1st External Cube total = X3 = 7234704 nano bytes2nd Internal Linear Path Independent = X4 = 16384 nanobytes √x * x(2nd power)= 163842nd Internal Linear Path Dependent = x5 = 16384 nanobytes √x * x(2nd power) = 163842nd Internal Linear Path Both Independent/Dependent = x6 = 32768 nanobytes √32768 * x(2nd power) 32768= 32768.000000044X7=

2nd Internal Curvature Convergence = X7 = 3288334336.025692537 nanobytes stays Internal √(x4 + x5 + x6 ) * x(4th power) see procedure below:

√(16384 + 16384 + 32768) = √65536 = 256 4th powerFinal Internal Curvature nanobyte packet formation X7= 4294967296

The nanopacket formation 2nd Internal final packet formation is as follows ( 3145728+ 7234704+ )4294967296 = 4305347728 nanobytes The nano packet is formed when it reaches the final curvatures using only 1 path to control the atomic and nanobit structure. Please also note the following:

1). I have two external curvatures in the 1st dimension2). I have 4 Internal curvatures 2nd dimension3). The Internal paths are the following: a). Independent b). Dependent c). Convergence d). Final Packet Formation

I have Just deployed a nanobyte Cryptographic Energy Model and the hardware components ofthis design employ both nanobits and nanobytes using the crypt model 1800 -2100 I must now create a screen that allows the user as to which model to use this also allows for backward compatibility. The screen should load up at boot time for configuration. If you notice the nanobit CPU is set up for 131072nbits, I have used 65536 nanobits so I have 65536 nanobits for password security. To make this work,

I will convert 8 billion nanobits to equal 1 character. This is achieved by taking 65536 nanobits and exponentiate it to the 3rd power (65536)3rd power. this gives us 2.814749767×10¹ or ⁴281,474,976,700,000. I can now create 35184.3720875 or 35184 characters for the switch below. I can now divide by 4 = 8796 characters this is used for nanobit protection and masking the nano bit character representation for additional security purposes. Please note the amount of cycles needed using 65536 nanobits is 2.814749767×10¹ The sub shelled Elliptic based curvatures allow for ⁴multiple events within the CPU and will allow for better I/O control rather than setting up a singular elliptic curve thus I can now process over 281 trillion cycles because I have miniature elliptic circles sub shelled within the CPU and with memory addressing to permit this. I can now set up a special character instead of using the standard 255 characters that a regular system would not recognize such asbelow:

1 0 A1E9 A021 B1F3 B035 C147 C079 D17K D038 E167 E025 F1H7 F06U G125 G079

H136 H097 I1ZU I025 J15T J07D K1Y4 K08E L17H L04F

M19O M03J N111 N034

O121 O047 P131 P073 Q141 Q027

R151 R037 S161 S037 T171 T038 U181 U039 V191 V040 V1A1 V050 W1B1 W050

The switch is basically encrypted on a micro scale and to access you must have the four characters for the on = “1” and “0” = off . This is programmed on the application level using if than else statements and or tables and arrays to text the hardware switch. I would also like to add that the following:

1). Address space regarding the Date field can now be expanded from two to now 4 characters for insuring a secured BIOS boot screen by employing the switch above on and off. This allows a degree ofencryption for two characters.

2). I have created a sub level switch that can now be considered to have a address registry similar to Assembler commands are loaded from addresses on a sub binary code level total 23 address spaces.The list of commands and Devices will expand as this project is updated. The coding scheme if you will notice has become a little more structured example the open command has A1EP the first characters uses the alphabet system the second character uses a 1 meaning “on” if it was A021 the 0 character means it is off. I needed to add a little structure to the address scheme.

On Off Commands/Application

A1E9 A021 Open B1F3 B035 Save C147 C079 Save As D17K D038 Print E167 E025 Copy F1H7 F06U Nano Hours G125 G079 Nano Minutes

H136 H097 Nano Seconds I1ZU I025 Nano battery J15T J07D Nano ROM Chip K1Y4 K08E Internal Hard Drive L17H L04F Network Adapter M19O M03J CPU Crypt generator N121 N034 CPU Fan

O131 O047 Video Slot P141 P073 Public Private Sound Adapters Q151 Q027 External Device connectors

R161 R037 External Hard Drive Controller S171 S037 Read T181 T038 Write U191 U039 Print V1A1 V040 Delete W1B1 W050 Private Key

Final Update Nano Motherboard Architecture Design

Chapter 4

I have complete the Nano based Mother Board and Software Interface. The original intent was to apply for a one year patent but this did not work out. The updates include both hardware and software. This design has the capability to process over 281 trillion cycles using data blocks of 65536 n bits with 6 linear paths. The NanoBios Software is now represented using Micro Time Scales(fractional time) and is reflected in the NanoBios Boot screen Menus. I have updated the Security by creating passwords in nano bits with 35184 which is masked with 17592 Nano Characters that use Nano based Hardware Components. This design now has the ability to use 22 address spaces creating a registry that also has been updated. The Crypt Model 1800 -2100 now has 4 methods to allow for processing and also has been updated. The major Hardware Components now have nano based direct memory access and can now be controlled through a sub level switch coupled with the Crypt Model 1800 – 2100 model.

This project the SS-307 has reached the final phase four copyrights and final update for this architecture. The CPU's have the capability to utilize 131072 =binary 2 17th Power nanobits architecture. The Cryptographic Model 1800- 2100 series has been completed. The Architecture now has the ability to process 281 trillion plus using 65536 blocks of data. I would like to note that by using the 131072 CPU architecture coupled with the Cryptographic Model 1800 – 2100 Energy Model it reached over 281 trillion cycles. The reason why this occurred is the principles of Dynamic and Asymmetrical energy principles. One of the main core principles of this design is utilizing Micro Time scales and is reflected in the NanoBios. The ability to process this large amount ofdata lies in the fact of being able to sub shell within a shell in multiple events on one time line. This design now has the ability to create a secured boot by having shadow copies. The CPU crypt Generator nano based is a important component of this design because it is now independent of the Regular CPU'sfreeing the CPU from bottlenecks and system throughput. The voltage regulator has 8 wires that are thicker and checks for 16384 nano bits per wire total 131072. The design now has 23 address spaces that have a more structured scheme and better control of on and off switches.

This design model produced 281 trillion cycles with blocks of 65536 as compared to regular Silicon based PC that produce 4096 blocks of data. This system produced 23 fields of address spaces that are Nano based and with direct memory address also time is now fractional on this system making this a advanced system design. The next phase will have to produce more address spaces expanding theregister and utilize bigger blocks of data. One of the key components is the ability to mask characters inpassword if using the 131072 bit architecture you could produce 35184/4 characters with 8796 used as representation.

Example of Masking 2 = ACD7

For the final Piece of this and added additional security I will add a private key for the purpose of unlocking the address how this is achieved is by setting up a matrix for the 23 address spaces and the key is accessed by using the address space assigned to it within the registry.

The Matrix for the key is based on Random generation using the 8796/4 password protection scheme. Remember each character in the registry is masked by 4 characters creating a encryption mechanism and the key decrypts the address space please see example below:

the Address space is represented by 4 characters thus four characters * four characters = 16. The matrix is set up by having a builtin key in the address registry. I now have 23 addresses in the matrix. This has a double password feature one in the BIOS memory representation and now a private key to unlock the Address registry. The BIOS allows you to set the password strengththus I have created a Dynamic Asymmetrical Key in the first event and the second event is symmetrical.

4

Private Key 8796/4 address space 23

23

Private Key 8796/4 address space 23

Example: The first event I choose to use the 65536 memory representation masking two characters per 1 and than I decide to use my private key to unlock the registry using the 8796/4 character representation. I have created in a nutshell a two event key that is Dynamic Asymmetrical andthan to unlock it Symmetrical two events and one time line. This completes this project and it has been exciting to present new ideas and concepts that can be done.

If you wish to view more work, Please visit my website below

Email [email protected]

My you tube Channel with short videos link below please like and subscribe

www.youtube.com/barrysscientificbasedproducts

www.barryssciencebaseproducts.com

07/23/2020

Barry L. Crouse

mailto:[email protected]

http://www.barryssciencebaseproducts.com/

http://www.youtube.com/barrysscientificbasedproducts

Documents

Barry's American system-307 Nano Motherboard Architecture ......The Visual Model Super Sonic 307 Motherboard 1-A General View overall view of the product and demonstrates a Industrial