Automatic Residue Removal for High NA Extreme IlluminationJames Moon, Byoung-Sub Nam, Joo-Hong Jeong, Dong-Ho Kong, Byung-Ho Nam, and Dong Gyu Yim, Memory Research & Development Division, Hynix Semiconductor Inc., San 136-1 Ami-ri, Bubal-eub, Icheon-si, Kyungki-do, 467-701, Korea

ABSTRACTAn epidemic for smaller node has been that, as the device architecture shrinks, lithography process requires high Numerical Aperture (NA), and extreme illumination system. This, in turn, creates many lithography problems such as low lithography process margin (Depth of Focus, Exposure Latitude), unstable Critical Dimension (CD) uniformity and restricted guideline for device design rule and so on. Especially for high NA, extreme illumination such as immersion illumination systems, above all the related problems, restricted design rule due to forbidden pitch is critical and crucial issue. This forbid-den pitch is composed of numerous optical effects but majority of these forbidden pitch compose of photo resist residue and these residue must be removed to relieve some room for already tight design rule.

In this study, we propose automated algorithm to remove photo resist residue due to high NA and extreme illumination condition. This algorithm automatically self assembles assist patterns based on the original design layout, therefore insuring the safety and simplicity of the generated assist pattern to the original design and removes any resist residue created by extreme illumination condition. Also

Continues on page 3.

PHOTOMASKPHOTOMASKBACUS—The international technical group of SPIE dedicated to the advancement of photomask technology.

INDUSTRY BRIEFSFor new developments in technology—see page 8

FEBRUARY 2008VOLUME 24, ISSUE 2

CALENDARFor a list of meetings—see page 9

N • E • W • S

TAKE A LOOK INSIDE:

Figure A1. Scum defect created by extreme illumination condition.

Page 2 Volume 24, Issue 2

N • E • W • S

Linewidth Roughness: Here’s the SolutionDouglas J. Resnick, Molecular Imprints

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6) nor techniques such as double patterning are likely to be suffi cient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly chal-lenging for electron and photon based NGL technologies, where fast chemically amplifi ed resists are used to defi ne the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits.

Linewidth roughness, the stochastic variations in width that occur along the length of a resist line – arises from a variety of sources, including exposure shot noise, diffusion of acid catalyst species, nanoscale phase separation, and the fi nite molecular dimensions of the resist components, etc. These phenomena are intrinsically problematic in the processing of positive tone chemically amplifi ed photoresists. The problem is particularly onerous to manufacturing because tuning the photolithography process for improved LWR performance generally worsens the process throughput. Recent data generated by the EUV community describes the problem in great detail. For the 32nm node, the target for LWR is 1.7nm, 3σ. Champion data for EUV resist is closer to 4nm, but as the resist sensitivity decreases to 10 mJ/cm2, the typical LWR is closer to 8 or 9 nm. The results are not surprising, since sensitivity and LWR are related by shot noise statistics (i.e. the number of photons or acid molecules available to defi ne the line edge).

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22nm and 16nm nodes. The low viscosity Drop-on-Demand™ approach, using Step and Flash® imprint lithography, is the only imprint technology that has been shown to be an effective method for both replicating nanometer-scale structures from a template (imprint mask) and addressing overlay. The resist issues described above are avoided in imprint lithography because the factors that control the LWR of an imprinted resist pattern are separate from the manufacturing process. Imprint lithography is a high fi delity replication process, so factors such as resolution and LWR are determined by the ability to create a master template having the required dimensions. The imprint process itself adds no additional LWR to the patterning process and thus the burden of minimizing any roughness falls to the template fabrication process. Fortunately, the template fabrication process is not subject to the same throughput constraints as the wafer lithography process, and it is ap-propriate to employ electron-beam lithography with less sensitive non-chemically amplifi ed resist materials that are capable of improved resolution with minimal linewidth variation. It is interesting to note that the use of non-chemically amplifi ed resists still allows a template to be written faster than a comparable 4X photomask. A recent study has shown that the LWR is nominally the same on both templates and imprinted wafers. In addition, no increase in LWR was observed after trans-ferring the imprinted images into oxide. Champion LWR data of 1.7nm has been reported, and line edge roughness as small as 1.0nm has also been observed. Typical LWR values at both 32nm and 22nm are between 2 and 3nm.

Although it is very likely that resist performance will continue to improve, over-coming the physical restrictions that control the statistics along a line edge may not be possible. A better approach is to develop a process that avoids stochastic variations. In other words, develop an exposure source that delivers enough pho-tons (for the case of EUV), or electrons (for either imprint masks or for direct write lithography). This has already been accomplished for imprint lithography, not just in the laboratory but in IC manufacturers’ development facilities as well.

EditorialBACUS News is published monthly by SPIE for BACUS, the international technical group of SPIE dedicated to the advancement of photomask technology. Circulation 2600.

Managing Editor/Graphics Linda DeLano

Advertising Sue Siegfried

BACUS Technical Group Manager Pat Wight

■ 2008 BACUS Steering Committee ■

President Brian J. Grenon, Grenon Consulting

Vice-President John Whittey, Vistec Semiconductor Systems, Inc.

Secretary Warren Montgomery, CNSE

Quarterly Meeting Chair Robert (Bob) Naber, Cadence Design Systems, Inc.

2008 Annual Photomask Chairs Hiroichi Kawahira, Sony Atsugi Technology Ctr. (Japan)

Larry S. Zurbrick, Agilent Technologies, Inc.

International Chair

Wilhelm Maurer, Infi neon Technologies AG (Germany)

Education Chair Wolfgang Staud, B2W Consulting

Newsletter Editors Artur Balasinski, Cypress Semiconductor Corp.

Warren Montgomery, CNSE

SponsorshipsSusan Siegfried, SPIE Sponsorship Consultant

Members at Large Frank E. Abboud, Intel Corp.

Michael D. Archuletta, RAVE LLC Uwe Behringer, UBC Microelectronics (Germany)Ute Buttgereit, Carl Zeiss SMS GmbH (Germany)

Chris Constantine, Oerlikon USA Inc.Thomas Faure, IBM Corp.

Gregory K. Hearn, SCIOPT EnterprisesGregg A. Inderhees, KLA-Tencor Corp.Kurt Kimmel, IBM Microelectronics Div.Paul Leuhrmann, ASML (Netherlands)

Mark Mason, Texas Instrument Inc.John A. Nykaza, Toppan Photomask, Inc.Christopher J. Progler, Photronics, Inc.

Douglas J. Resnick, Molecular Imprints, Inc.J. Tracy Weed, Synopsys, Inc.

P.O. Box 10, Bellingham, WA 98227-0010 USATel: +1 360 676 3290 or +1 888 504 8171

Fax: +1 360 647 1445SPIE.org

customerservice@spie.org

©2008

All rights reserved.

N • E • W • S

Volume 24, Issue 2 Page 3

N • E • W • S

Continues on page 4.

Continued from cover.

we tested our automated algorithm on full chip FLASH memory device and showed the residue removal effect by using commercial verifi cation tools as well as on actual test wafer.

IntroductionIn keeping up with the promise made by the Moore’s law, semicon-ductor industry is evolving like never before. Especially for lithography world, shrinkage of device size is revolutionizing lithography technol-ogy in a way that no one has ever expected. Introduction of Immer-sion, Double patterning, EUV are all product of this evolution and promises exciting result that enable us to keep up with the Moore’s Law. But with this advantages came many lithography problems such as low lithography process margin (DOF, EL), unstable CD uniformity and restricted guideline for device design rule and so on. Especially for high NA extreme illumination such as immersion illumination

systems, above all the related problems, restricted design rule due to forbidden pitch is critical and crucial issue. This forbidden pitch is composed of numerous optical effects, but majority of these forbid-den pitch compose of photo resist residue and these residue must be removed to relieve some room for already tight design rule.

In this paper, we demonstrated a simple automated algorithm to remove any photo resist residue do to such extreme illumination con-dition. First, we will describe the background for such scum residue problem. Second, automated algorithm for removing scum removal generation will be thoroughly described. This algorithm automatically self assembles assist patterns based on the original design layout, therefore insuring the safety and simplicity of the generated assist pattern to the original design and removes any resist residue created by extreme illumination condition.

Figure A2. Scum defect area on “Space size versus duty”. (High lighted area: scum generated region.)

Figure A3. Rule check results for possible scum residue generation area.

Figure A4. Wafer inspection result for rule check scum generation points. (Resist step.)

Page 4 Volume 24, Issue 2

N • E • W • S

Figure B1. Automatic scattering space generation algorithm for scum residue removal.

Continued from page 3.

Third, the simulation result of the proposed method will be dis-cussed. Also, wafer experimental result of automated scum removal method will be discussed for full chip Flash device. Finally conclusion will be made to summarize the automated scum removing method for modern day devices and further work will be discussed.

BackgroundAs shown on fi gure A1, scum residue can have devastating wafer output when left untreated. Especially for Poly or Bit-line layers, such

scum defect may introduce unwanted circuitry result. Even if this scum defect has no infl uence on device performance, scum defect maybe a problem for defect inspection1 since this defect cannot be distinguished by other serious wafer defects. Therefore, predicting exactly where this defect may occur is very important.

As shown on fi gure A2, scum residue occurs more serious at certain sizes of the design layout. Also scum residue shows stronger effect at defocused condition as to best focus condition. Considering focus and exposure latitude margin for the experimental condition, scum

Figure B2. Detailed procedure of the algorithm.

Volume 24, Issue 2 Page 5

N • E • W • S

Continues on page 6.

generation region is highlighted on “Size versus Duty” table on fi gure A2. Analyzing fi gure A2, sizes of the scum residue area resides on design rule for actual device. Inspection on the design layout for scum residue area detected circuits shown on fi gure A3. Circuits shown on fi gure A3 all showed possibility for scum residue generation and actual wafer result shown on fi gure A4 confi rms this result. Also as shown on fi gure A4, optical simulation can also accurately detect scum residue on full chip level.

Now, knowing where and how scum residue takes place, method to remove scum residue must be considered. Best way to avoid such problem would be removing any design size that may cause scum residue at design stage. But certain design cannot be altered for device performance reason and for this case, circuitry shown on fi gure A3 cannot be altered. Other way to remove scum residue can be altering illumination condition. But this method shows constraints since illumination condition is fi xed by cell or smallest feature to defi ne on the design layout. Therefore introducing scattering space on only the region with scum residue is possible method to remove scum residue without changing the design layout or altering the illumination condition. Next chapter shows automatically self assembles assist patterns based on the original design layout, therefore insuring the safety and simplicity of the generated assist pattern to the original design and removes any resist residue created by extreme illumina-tion condition.

AlgorithmSimilar to our previous coding method to generate Self Assembled Dummy,2 the proposed automatic self assembles assist patterns generation method requires the use of Boolean and other simple coding structure to safely generate illumination condition based scattering space at scum generation region. It requires no optical

simulation but fundamental process feed back is necessary to set the sizes required for the scattering space generation. The fl ow chart of the simple algorithm required to generate scattering space is shown on Figure B1. As shown on Figure B1, scattering space generation requires only original design data. In the fi rst step of the fl ow chart (PAD Extraction), the design size that creates scum residue as previ-ously shown in fi gure A2 is selected on full chip layout. After the PAD Extraction, extracted pads are shrunk to A and A+B size respectively. A size refers to location of the scattering space and B refers to the size of the scattering space. Shrunken PAD1 (A) and PAD (A+B) is then BOOLEAN NOT to create scattering space (BOOLEAN NOT1). Then created scattering space and Original Design is BOOLEAN NOT to actually create the scattering space on the original layout (BOOLEAN NOT2). More detailed description of the algorithm for dipole illumina-tion is shown through fi gure B2.1) As shown on fi gure B2, only the design size with scum residue

possibility is selected. (PIC2)2) Selected fi gure from PIC2 is then shrunk by A nm both X and Y

direction. (PIC3)3) 2) is then shrunk B nm for only x direction (right/ left). (PIC4)4) Figure from PIC3 is BOOLEAN NOT on PIC4 to create scattering

space fi gure. (PIC5)5) Scattering space fi gure created from PIC5 is then BOOLEAN NOT

on Original Layout to create actual scattering space. (PIC6)As shown from the process on fi gure B2, the algorithm only requires

the original layout and created scattering space is created from original layout. This ensures the safety of the created scattering space for the layout on full chip level. Also depending on the illumination condition

Figure C1. Simulation result for scum points with and without automated scattering space.

Continued from page 5.

Page 6 Volume 24, Issue 2

N • E • W • S

size A (location of the scattering space) and B (size of the scattering space) can be tuned to any illumination condition, ensuring accuracy of the created scattering space to scum removal rate. The fi gures for B2 is an example for dipole illumination, where x and y direction pattern have different illumination characteristics. For symmetry il-luminations such as annular or cross-pole, scattering space can be created for both x and y direction concurrently.

SimulationsThe experiment of removing scum residue with proposed method was tested on POLY layer of sub 60nm technology devices for applicability. The proposed algorithm was in-house coded on simple layout handling tool. The main focus of the simulation was to verify the scum residual removal on Poly layer with the automati-cally generated scattering space on full chip level. Dipole was used as the illumination source. The process condition for the generated layer used 0.93NA, x directional dipole with ArF as the illumination source. First DB handling perspective of the proposed method was investigated. The main focus was on data size, created polygon and

run time of the generated code. Second, full-chip applicability of the SAD generation was investigated. The main focus was to verify any errors or process weak point created by proposed method for full-chip level. The verifi cation was performed using model based verifi cation tool and number of scum residue defect was inspected for various defocus and energy level.

The data size after the scattering space generation showed hardly any increase in data size prior to the generation which was within our data handling range. The created polygon number accounted twice the size of scum residue rule check result. This result showed that generated scattering space was properly and correctly placed on original design since it takes 2 scattering space to remove 1 scum residue. Also, it only took 5 minutes to generate the scattering space on full-chip. This clearly is an advantage over manual scattering space generation which takes several days and several hours using conventional dummy generation automation tools.

With data base handling out of the way, Model based simulation verifi cation was done on “Automatic Scattering space generated

Figure C2. Number of scum residue detected for full chip with and without automated scattering space (At various energy and focus).

Figure D1. Wafer results for automated scattering space generated layout at various focus.

Volume 24, Issue 2 Page 7

N • E • W • S

OPC data” and “Only OPC data” for verifi cation of fullchip mask. Simulation showed that, as shown on fi gure C1, for scum detected points 1, 2 and 3, data with scattering space was free from scum residue opposed to data without scattering space. Also, as shown on fi gure C2 where numbers represents number of detected scum residue for various focus and energy, scum residue defect numbers grew for under-dose defocused environment as expected. But “Auto-matic Scattering space generated OPC data” was almost scum free for process window as to “Only OPC data”. This simulation results clearly shows that automated scattering space method is effective in removing any unwanted scum residue for various illumination condi-tion and also no scattering space induced error was detected during the model based verifi cation. This clearly indicates the safety of the propose scattering space generation method.

Wafer ResultsAutomated scattering space generation algorithm was tested on sub 60nm FLASH device for wafer inspection. As previously stated, process condition was 0.93NA, x directional dipole with ArF as the illumination source. As shown on fi gure D1, previous scum points showed no scum residue at best focus or any of the defocus area.

Also, scum was free for energy level of at least 15% under optimal energy level as shown on fi gure D2. Figure D3 shows scum weak point at worst optical condition (under 12.5% optimal energy/++ defocus). No scum residue was found for this condition as well. Also, mechanical defect review system3 (KLA / NGR / Etc) showed no scum residue formation at any of the process window (15% Eop/±0.1um focus) as shown on fi gure D4.

ConclusionIn this paper, we have developed new method of automatically generating scattering space for scum residue removal with respect to illumination condition. First, we were able to predict where scum residue takes place and removed scum residue defect without changing the original design or altering illumination condition. The new method’s algorithm and examples have been explained and test on sub 60nm technology has been shown. The new method showed un-comparable result compared to conventional method. No data

base handling problem was shown and verifi cation with MBV showed very strong process margin enhancement characteristic compared to conventional method. Simulation result showed signifi cant scum removal using proposed method for various focus and energy level.

Also test wafer results from sub 60nm technology also proved this simulation result. Further work will be done to fi ne tune this algorithm for better focus and energy margin.

References1. Hyunjo Yang et al, “OPC Accuracy Enhancement through

Systematic OPC Calibration and Verifi cation Methodology for sub-100nm Node”, Proc. SPIE 2005.

2. James Moon et al, “Self Assembled Dummy Patterns for Lithography Process Margin Enhancement”, Proc. SPIE 2007.

3. Jungchan Kim et al, “OPC and Design Verifi cation for DFM using Die-to-Database Inspection”, Proc. SPIE 2007.

Figure D2. Wafer results for automated scattering space generated layout at various exposure energy.

Figure D3. Wafer results for automated scattering space generated layout at worst energy/focus condition.

Figure D4. Mechanical scum residue review result.

Page 8 Volume 24, Issue 2

N • E • W • S

Industry Briefs

Sponsorship OpportunitiesSign up now for the best Photomask 2008 sponsorship opportunities. Contact:

Sue SiegfriedTel: +1 510 728 2105ssiegfried@spie.org

N • E • W • S

To receive email announcements for these meetings, send an email message to patw@spie.org; in the body of the message include the words subscribe info-bacus.

Advertise in the BACUS News!

The BACUS Newsletter is the premier publication serving the photomask industry. For information on how to advertise, contact:

Sue SiegfriedTel: +1 510 728 2105ssiegfried@spie.org

BACUS Technical Meetings

BACUS holds technical meetings in the Bay Area approximately every quarter, from 8:30 to 11:30 am. If you are interested in presenting a paper at this meeting, contact Robert (Bob) Naber, Cadence Design Systems, Inc., Tel: 510 814 0972; Email: naber@cadence.com

BACUS Corporate Members

Aprio Technologies, Inc.ASML US, Inc.Brion Technologies, Inc.Coherent, Inc.Corning Inc.Gudeng Precision Industrial Co., Ltd.Hamatech USA Inc.Inko Industrial Corp.JEOL USA Inc.KLA-Tencor Corp.Lasertec USA Inc.Micronic Laser Systems ABRSoft Design Group, Inc.Synopsys, Inc.Toppan Photomasks, Inc.

■ Laterally Resolved Phase Measurements at 45nm Using Photomask Phase Metrology

Solid State Technology, January 2008

As the lithography moves toward 32 nm, attenuated and alternating phase shift masks (PSMs) need more precise control of the phase shift across pitch and target sizes, affected by numerical aperture (NA), mask pitch, 3D effects, and polarization. The new optical metrology tool, Phame, enables the industry to perform in-die phase measurements including CPL (chromeless phase lithography) masks down to 120nm half-pitch at the mask. Phame measures the scanner equivalent phase and amplitude in the image plane for each coherent source point. Phase shift extraction requires symmetry of the diffraction spectrum. For an altPSM using on-axis illumination, the -1st and 1st diffraction order is captured in the scanner and ideal two-beam interference occurs. The diffraction spectrum lies perfectly symmetrical in the pupil. To achieve the same printing information with an attPSM or CPL mask using the same scanner NA, off-axis illumination is required, where the 0th diffraction order is shifted in the pupil with respect to the optical axis. For each source point, the electrical fi eld is determined in the phase metrology tool. The zero diffraction orders of each source point are algorithmically shifted in such a way that they fall together in the optical axis of a fi ctive pupil and the resulting electrical fi elds are coherently merged. By applying this procedure, a symmetric diffraction spectrum of the mask is obtained and at the same time, the original mask side NA is enlarged by the off-axis angle. The symmetric diffraction spectrum that is generated by this procedure is now propagated into the image plane and a high-resolution phase and intensity images are obtained. The off-axis high-resolution phase shift is sensitive to the diffraction spectrum and mask phase errors. It can be used for design verifi cation, defect analysis, and process control. The new phase metrology system can measure large reference features with high reproducibility. The phase shift result of 178° for on-axis and 180° for off-axis corresponds to the expected phase difference of 2.3° due to off-axis angle and the light path difference caused by the angled geometry. Additionally, excellent reproducibility values <0.15Æ (3Û) were reported for both measurements.

■ Groups Collaborate on EUV Lithography Advances

John Walko, EE Times Europe

Belgian research group IMEC (Leuven) and the College of Nanoscale Science and Engineering (CNSE) of the University at Albany in Albany, New York, will collaborate on extreme ultraviolet lithography to accelerate the introduction of EUVL into manufacturing. The fi rst set of collaborative experiments will be carried out at CNSE’s Albany NanoTech Complex, with future joint studies to be conducted at CNSE and IMEC. The majority of activities will focus on the advanced imaging capabilities of the EUVL system, with additional effort devoted to the understanding of new materials and various aspects of equipment technology. The goal is to demonstrate the practical feasibility of EUVL and build confi dence in the technology for the 32-nm half pitch device node and below. Luc Van den hove, Executive Vice President and Chief Operating Offi cer at IMEC, commented: “EUV lithography is a promising solution to further scale CMOS beyond the 32-nm but still major challenges need to be overcome. Since EUV is still in a development phase, the alpha demo tools have to be upgraded occasionally. The accord reached between the participants is a “win-win” situation for all involved in the program. In mid 2006, a minor war of statements ensued between the CNSE and IMEC about which facility received the world’s fi rst full-fi eld R&D EUV tool from ASML.

Volume 24, Issue 2 Page 9

N • E • W • S

2008

SPIE Advanced Lithography

24-29 FebruarySan Jose McEnery Convention CenterSan Jose, California USAspie.org/al

Photomask Japan

16-18 April Hotel Pacifi co YokohamaYokohama, Japanwww.photomask-japan.org

Photomask Technology

6-10 October Monterey, California USAspie.org/photomask

C a l e n d a r

About the BACUS GroupFounded in 1980 by a group of chrome blank users wanting a single voice to interact with suppliers, BACUS has grown to become the largest and most widely known forum for the exchange of technical information of interest to photomask and reticle makers. BACUS joined SPIE in January of 1991 to expand the exchange of information with mask makers around the world.The group sponsors an informative monthly meeting and newsletter, BACUS News. The BACUS annual Photomask Tech-nology Symposium covers photomask technology, photomask processes, lithography, materials and resists, phase shift masks, inspection and repair, metrology, and quality and manufacturing management.

Join the premier professional organization for mask makers and mask users!

Corporate Membership Benefi ts include:■ One Voting Member in the SPIE General Membership

■ Subscription to BACUS News (monthly)

■ One online SPIE Journal Subscription

■ Exhibit Space discount of 8% at either the Photomask or Advanced Lithography Symposium

■ Listed as a Corporate Member in the BACUS Monthly Newsletterspie.org/bacushome

Individual Membership Benefi ts include:■ Subscription to BACUS News (monthly)

■ Subscription to Microlithography World(quarterly)

■ Quarterly technical meetings in the Bay Area

■ Reduced registration rates at BACUS Photomask Technology annual meeting

■ Eligibility to hold offi ce on BACUS Steering Committee

spie.org/bacushome

You are invited to submit events of interest for this calendar. Please send to lindad@spie.

org; alternatively, email or fax to SPIE.

SPIE is an international society advancing an interdiciplinary approach to the science and application of light.

International HeadquartersP.O. Box 10, Bellingham, WA 98227-0010 USATel: +1 888 504 8171 or +1 360 676 3290Fax: +1 360 647 1445customerservice@spie.org • SPIE.org

Shipping Address1000 20th St., Bellingham, WA 98225-6705 USA

2 Alexandra Gate, Ffordd Pengam, Cardiff, CF24 2SA, UKTel: +44 29 20 89 4747Fax: +44 29 20 89 4750spieeurope@spieeurope.org • www.spieeurope.org

❈

❈

❈