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External Use
Applied Reflexion® LK Prime™
CMP System Enabling High-Volume Manufacturing of
Advanced 3D Microchips
July 7, 2014
External Use
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Transistors Transitioning from Planar to 3D
Images Source: Public announcements and conference publications
Planar Logic 3D FinFET 2D NAND 3D NAND
Chemical Mechanical Planarization (CMP) controls device performance
More complex sequence demands higher productivity
Comprehensive capabilities needed to meet requirements
Nanometer-level uniformity required
Up to 10 additional CMP steps
Planarization and process stability
required for extremely long polish
Up to 5 additional CMP steps
External Use
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On-Wafer Performance
► Improved uniformity
► Fewer defects
Flexibility
► Application-specific processes
Extendibility
► Multi-generation capabilities
Productivity
► More wafers, less fab space
Better on-wafer results enable new device architectures
CMP: Key Enabler of 3D Device Fabrication
External Use
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Sets new performance
and productivity
benchmarks for
fabricating FinFET and
3D NAND devices.
Applied Reflexion® LK Prime™ CMP System
Comprehensive CMP solution for next-generation devices
External Use
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Titan Edge™ polishing head improves removal
uniformity
Enhanced FullVision™ process control
New pre-cleaning module reduces defectivity
Real-time process control for new materials
14 processing stations (polishing + cleaning)
Optimized wafer handling
Enabling Technology for 3D Devices
Flexible, extendible CMP for advanced architectures
External Use
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Improved Productivity and Flexibility
Distributed processing improves stability and polish precision
Sequential processing enables multi-step applications
Parallel processing improves productivity
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The Platform for the Future
Designed to enable 3D device architectures
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Silicon
Oxide
Silicon
Multi-step polishing stabilizes removal rate and profile
Smoother Topography
Single Step Multi-Step
Oxide
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Silicon
Oxide
Silicon
Multi-step polishing stabilizes removal rate and profile
Smoother Topography
Single Step Multi-Step
Oxide
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Oxide
Silicon
Oxide
Silicon
Multi-step polishing stabilizes removal rate and profile
Smoother Topography
Single Step Multi-Step
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Oxide
Silicon
Oxide
Silicon
Multi-step polishing stabilizes removal rate and profile
Smoother Topography
Single Step Multi-Step
External Use
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Oxide
Silicon
Oxide
Silicon
Multi-step polishing stabilizes removal rate and profile
Smoother Topography
Single Step Multi-Step
External Use
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Oxide
Silicon
Oxide
Silicon
No Residue Minimal Dishing
Multi-step polishing stabilizes removal rate and profile
Residue Dishing
Smoother Topography
Single Step Multi-Step
External Use
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Oxide
Silicon
Oxide
Silicon
Smoother Topography
No Residue Minimal Dishing Residue Dishing
Multi-step polishing stabilizes removal rate and profile
Single Step Multi-Step
External Use
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Within-Wafer Poly FinFET Uniformity
LK Prime enables nanometer-scale process control
29
13
7
0
5
10
15
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25
30
Single-Step No ProcessControl
Single-Step ProcessControl
Multi-Step ProcessControl with LK Prime
Wit
hin
-Wafe
r R
an
ge (
nm
)
External Use
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Wafer-to-Wafer Metal Gate Uniformity
7
5
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0
1
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7
8
Baseline Capability Better Edge Control Feed-Forward ProcessControl With LK Prime
LK Prime enables nanometer-scale process control
Wafe
r-to
-Wafe
r R
an
ge (
nm
)
External Use
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Best On-Wafer Performance − Polish heads
− In-situ process control
− Chemical buff
Highest Throughput Density − 14 processing stations
− Up to 2x higher throughput
Flexible and Extendible
− Batch, parallel, and sequential
processing
− Multi-generation capabilities
Comprehensive CMP for 3D devices
Applied Reflexion LK Prime CMP System
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