AW-Basic Operational Charakteristics and Parameters

7/30/2019 AW-Basic Operational Charakteristics and Parameters

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by Agung Wibowo, Dr. Eng.


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Noise is unwanted voltage that is induced in electrical circuits andpresent a threat to the proper operation of the circuit.

The noise immunity is the ability to tolerate a certain amount ofunwanted voltage fluctuation on its inputs without changing itsoutput state.

Example :

If noise voltage causes the input of a 5 V CMOSgate to drop below 3.5 V in HIGH state, theinput is in the unacceptable region andoperation is unpredictable . Thus, the gate mayinterpret the fluctuation below 3.5 V as a LOW

level.Similarly, if noise causes a gate input to goabove 1.5 V in the LOW state , uncertaincondition is created.


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A measure of a circuits noise immunity is calledthe noise margin, which is expressed in volt.

There are two value of noise margin specified for agiven logic circuit :

The HIGH-level noise margin (VNH)

The LOW-level noise margin (VNL)

VNH is the difference between the lowest possibleHIGH output from a driving gate (VOH(min)) and thelowest possible HIGH input that the load gate cantolerate (VIH(min)).VNH = VOH(min) VIH(min)

VNL is the difference between the maximum

possible LOW input that a gate can tolerate(VIL(max)) and the maximum possible LOW output ofdriving gate (VOL(max))

VNL = VIL(max) VOL(max)


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VNH = ?

VNL = ?


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HIGH

HIGH

HIGH

HIGH

LOW

1.1 v0.4 v

VNH = VOH(min) VIH(min)

VNL = VIL(max) VOL(max)

LOW

HIGH

LOW

HIGH

HIGH

0.75 v

2.4 v


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A logic gate draws current from the dc voltage

source. When the gate is in HIGH output state, an amount of

current designated by ICCH is drawn,

In LOW output state, a different amount of current,ICCL, is drawn.

The power dissipation in a static (non changing)HIGH output state is :

PD = VCC x ICCH The power dissipation when the gate is pulsed, its

output switch back and forth between HIGH andLOW, the amount of supply current varies betweenICCH and ICCL.

The average power dissipation depend on the dutycycle and usually specified for a duty of 50%.

For 50% duty cycle :ICC = (ICCH + ICCL)/2 The average power dissipation is :

PD = VCC x ICC


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When signal passes (propagates) through a logicgate, it always experiences a time delay.

There are two propagation delay time specifiedfor logic gates :

tPHL , the time between a designated point oninput pulse and the corresponding on theoutput pulse when the output is changing fromHIGH to LOW.

tPLH, the time between a designated point oninput pulse and the corresponding on theoutput pulse when the output is changing fromLOW to HIGH.


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When the output of a logic is connected to one or more inputs of other gates,a load on the driving gate is created.

There is a limit to the number ofload gate inputs that a given gate can drive.This limit is called the fan-out of the gate.


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Metal-oxide semiconductor field effecttransistor (MOSFETs) are active switchingelements in CMOS circuits

This devices differ greatly in construction andinternal operation from bipolar junctionstransistor used in bipolar (TTL) circuits, butswitching action is basically the same : they

function ideally as open and closed switchesdepending on the inputs.

When the gate voltage of an n-channelMOSFET is more positive than the source, theMOSFET is ON (saturation).

When the gateto- source voltage is zero, theMOSFET is off (cutoff).

The p-channel MOSFET operates withopposite voltage polarities.


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Complementary MOS (CMOS) logic usesthe MOSFET in complementary pairs asits basic element.

When a HIGH is applied to the input,the p-channel MOSFET Q1 is OFF andthe n-channel MOSFET Q2 is ON

This condition connect the output toground through the onresistance ofQ2, resulting in a LOW output.

When a LOW is applied to the input, Q1is ON and Q2 is OFF

This condition connect the output to +VDD (dc supply voltage) through the onresistance of Q1, resulting in a HIGHoutput.


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The bipolar junction transistor (BJT) is the activeswitching element used in all TTL circuit.

The basic switching operation is as follows:

When the base is approximation. 0.7 V morepositive than the emitter and when sufficientcurrent is provided into base, the transistorturn on and goes into saturation. In saturation,the transistor ideally act like a closed switch

between collector and the emitter.

When the base less than 0.7 V more positivethan the emitter, the transistor turns off andbecome an open switch between the collectorand the emitter.

Summarize :

a HIGH on the base turns the transistor ON andmake it a closed switch .

A LOW on the base turns the transistor OFF andmake it an open switch.

In TTL some BJTs have multiple emitter.


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Transistor Q1 is the input couplingtransistor, and D1 is the input clampdiode.

Transistor Q2 is called a phasesplitter and combination of Q3 and Q4forms the output circuit often referredto as a totem-pole arrangement.


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When the input is HIGH, the base-emitter junctionof Q1 is reverse-biased, and the base collectorjunction is forward-biased. This condition permitscurrent through R1 and the basecollector junctionof Q1into the base Q2, thus driving Q2 intosaturation (on). Q3 is turn on by Q2, and itscollector voltage, which is the output, is nearground potential. Therefore the output is LOW. Atthe same time, the collector of Q2 is at a sufficiently

low voltage level to keep Q4 off.

When the input is LOW, the base-emitter junction ofQ1 is forward-biased, and the baseemitter junctionis the reverse-biased. There is current through R1and base-emitter junction of Q1 to the LOW input.A LOW provide a path to ground for the current.There is no current into the base of Q2, so it is off.

The collector of Q2 is HIGH, thus turning the Q4 on.A saturated Q4 provides a low-resistance path fromVCC to the output. Therefore the output becomeHIGH for a LOW on the input. At the same time, theemitter of Q2 is at ground potential, keeping the Q3off.


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Basically, it is the same as the invertercircuit except for the additional inputemitter of Q1.

In TTL technology, multiple emittertransistor are used for the input devices.

These multiple-emitter transistor can becompared to diode arrangement.

A LOW on either input A or input B

forward-biases the corresponding diodeand reverse-biases D3 (Q1 vase-collectorjunction) . This action keeps Q2 off andresults in a HIGH output

A LOW on both inputs will do the samething.

A HIGH on both inputs reverse-biases bothinput diodes and forward-biases D3 (Q1

base-collector junction). This action turnsQ2 on and results in a LOW output.

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AW-Basic Operational Charakteristics and Parameters