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Copyright 2008, Avnet, Inc. All Rights Reserved.
This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in any form or by any means without the prior written permission of Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All trademarks and trade names are the properties of their respective owners and Avnet, Inc. disclaims any proprietary interest or right in trademarks, service marks and trade names other than its own.
Avnet is not responsible for typographical or other errors or omissions or for direct, indirect, incidental or consequential damages related to this material or resulting from its use. Avnet makes no warranty or representation respecting this material, which is provided on an "AS IS" basis. AVNET HEREBY DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, INCLUDING, WITHOUT LIMITATION, REPRESENTATIONS REGARDING ACCURACY AND COMPLETENESS, ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, SUITABILITY OR FITNESS FOR A PARTICULAR PURPOSE, TITLE AND/OR NON-INFRINGEMENT. This material is not designed, intended or authorized for use in medical, life support, life sustaining or nuclear applications or applications in which the failure of the product could result in personal injury, death or property damage. Any party using or selling products for use in any such applications do so at their sole risk and agree that Avnet is not liable, in whole or in part, for any claim or damage arising from such use, and agree to fully indemnify, defend and hold harmless Avnet from and against any and all claims, damages, loss, cost, expense or liability arising out of or in connection with the use or performance of products in such applications.
Function
www.em.avnet.com/spartan3a-evl
1Cover Sheet
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4
9
Sheet Number
5
3
Avnet Design Services
8
10
Spartan-3A Evaluation Board
2
7
11
Block Diagram
Architecture
FPGA1
FPGA2
FPGA3
FPGA Power
PsOC
Memory
Miscellaneous
Board Power
Avnet Engineering ServicesTitle:
Sheet 1 - Lead SheetSize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 1 12
5/13/20088:54:32 AM
U_Sp3A Eval Block Diagram02 Sp3A Eval Block Diagram.SchDoc
12Revision History
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 2 - Block DiagramSize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 2 12
U_03 Sp3A Eval Architecture03 Sp3A Eval Architecture.SchDoc
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 3 - Spartan 3A Sample Board HierarchySize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 3 12
FLASH_CE#FLASH_WE#FLASH_OE#Flash_A[21..0]
IIC_SCLIIC_SDA
LED1LED2LED3LED4
UART_RXDFLASH_RY/BY# UART_TXD
Bank0_IO[32..1]
FPGA_PUDC
FLASH_BYTE#
PSOC_P7_7
BANK1_IO1
U_FPGA104 Sp3A Eval FPGA1.SchDoc
FPGA_PUSH AFPGA_PUSH B
PSOC_P2_1
FPGA_PUSH_C
PSOC_FPGA_M1
PSOC_P5_7
DIGI2_[3..0]
PSOC_FPGA_M0FPGA_INIT_B
FPGA_RESET
CLK_12MHZ
PSOC_P2_5PSOC_P2_3
PSOC_P2_7
PSOC_P7_0
PSOC_P5_3PSOC_P5_4
PSOC_P4_6
CLK_32KHZ
Flash_D[7..0]
SPI_CLK
DIGI1_[3..0]
PSOC_FPGA_M2
BANK3_IO1
FPGA_PUDC
FPGA_SPI_SEL#
SF_W#SF_HOLD#
Flash_D[14..8]
PSOC_P5_6
FLASH_RESET#
PSOC_P0_4
BANK3_IO2
FPGA_MOSIFPGA_MISO
U_FPGA205 Sp3A Eval FPGA2.SchDoc
FPGA_DONEPSOC_FPGA_PROG
JTAG_TMSJTAG_TCKJTAG_TDI
JTAG_TDO
PO_RESET#
JTAG_MUX_CTL
U_FPGA306 Sp3A Eval FPGA3.SchDoc
U_FPGA Power07 Sp3A Eval FPGA Power.SchDoc
SPI_CLKFPGA_MOSI
FLASH_RY/BY#
FLASH_OE#FLASH_WE#
Flash_D[7..0]
Flash_A[21..0]
FLASH_CE#
PO_RESET#SF_HOLD#
SF_W#
Flash_D[14..8]
FLASH_BYTE#
FLASH_RESET#
PSOC_SPI_MODE
PSOC_MOSIFPGA_SPI_SEL#
FPGA_MISOPSOC_SPI_SEL#
PSOC_MISO
U_Memory09 Sp3A Eval Memory.SchDoc
IIC_SDA
DIGI2_[3..0]DIGI1_[3..0]
Bank0_IO[32..1]
IIC_SCL
LED1
LED3LED4
LED2 BANK3_IO1
BANK1_IO1
BANK3_IO2
U_Miscellaneous10 Sp3A Eval Miscellaneous.SchDoc
PO_RESET#
U_Power11 Sp3A Eval Power.SchDoc
PSOC_P5_4
PSOC_P5_7
PSOC_P2_5PSOC_P2_3PSOC_P2_1
FPGA_PUSH_CPSOC_P4_6
PSOC_P2_7
PSOC_P5_3
CLK_32KHZ
SPI_CLK
PSOC_MOSI
JTAG_TCK
JTAG_TDOJTAG_TDI
PSOC_FPGA_PROG
PSOC_P7_7
PSOC_FPGA_M2PSOC_FPGA_M1
UART_TXD
FPGA_DONE
UART_RXD
JTAG_TMS
FPGA_RESET
CLK_12MHZ
PSOC_FPGA_M0
PSOC_P7_0
FPGA_PUSH AFPGA_PUSH B
FPGA_INIT_B
PSOC_P5_6
IIC_SDAIIC_SCL
JTAG_MUX_CTL
PSOC_SPI_MODE
PSOC_P0_4
PSOC_SPI_SEL#
PSOC_MISO
U_PsOC08 Sp3A Eval PsOC.SchDoc
Flash_D[7..0]
Flash_A[21..0]
Bank0_IO[32..1]
PO_R
ESET
#
SPI_CLK
SPI_CLK
PO_RESET#
Flash_D[14..8]
IIC_SCLIIC_SDAPSOC_SPI_MODE
PSOC_SPI_MODE
PSOC_MOSI
PSOC_MOSI
IIC_SDAIIC_SCL
PSOC_MISO
PSOC_SPI_SEL#
PSOC_SPI_SEL#
PSOC_MISO
DIGI1_[3..0]DIGI2_[3..0]
N0BANK00IO0320010 N0BANK00IO1 N0BANK00IO2 N0BANK00IO3 N0BANK00IO4 N0BANK00IO5 N0BANK00IO6 N0BANK00IO7 N0BANK00IO8 N0BANK00IO9 N0BANK00IO10 N0BANK00IO11 N0BANK00IO12 N0BANK00IO13 N0BANK00IO14 N0BANK00IO15 N0BANK00IO16 N0BANK00IO17 N0BANK00IO18 N0BANK00IO19 N0BANK00IO20 N0BANK00IO21 N0BANK00IO22 N0BANK00IO23 N0BANK00IO24 N0BANK00IO25 N0BANK00IO26 N0BANK00IO27 N0BANK00IO28 N0BANK00IO29 N0BANK00IO30 N0BANK00IO31 N0BANK00IO32
N0DIGI10030000 N0DIGI100 N0DIGI101 N0DIGI102 N0DIGI103
N0DIGI20030000 N0DIGI200 N0DIGI201 N0DIGI202 N0DIGI203
N0FLASH0A0210000 N0FLASH0A0 N0FLASH0A1 N0FLASH0A2 N0FLASH0A3 N0FLASH0A4 N0FLASH0A5 N0FLASH0A6 N0FLASH0A7 N0FLASH0A8 N0FLASH0A9 N0FLASH0A10 N0FLASH0A11 N0FLASH0A12 N0FLASH0A13 N0FLASH0A14 N0FLASH0A15 N0FLASH0A16 N0FLASH0A17 N0FLASH0A18 N0FLASH0A19 N0FLASH0A20 N0FLASH0A21
N0FLASH0D0 N0FLASH0D1 N0FLASH0D2 N0FLASH0D3 N0FLASH0D4 N0FLASH0D5 N0FLASH0D6 N0FLASH0D7
N0FLASH0D8 N0FLASH0D9 N0FLASH0D10 N0FLASH0D11 N0FLASH0D12 N0FLASH0D13 N0FLASH0D14 N0FLASH0D0140080
N0FLASH0D070000
N0IIC0SCL
N0IIC0SDA
N0PO0RESET#
N0PSOC0MISO
N0PSOC0MOSI
N0PSOC0SPI0MODE
N0PSOC0SPI0SEL#
N0SPI0CLK
N0PO0RESET#
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 4 - FPGA1 (Banks 0 & 1)Size: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 4 12
BA
NK
0IO_L01N_0C13
IO_L01P_0D13
IO_L02N_0B14
IO_L02P_0/VREF_0B15
IO_L03N_0D11
IO_L03P_0C12
IO_L04N_0A13
IO_L04P_0A14
IO_L05N_0A12
IO_L05P_0B12
IO_L06N_0/VREF_0E10
IO_L06P_0D10
IO_L07N_0A11
IO_L07P_0C11
IO_L08N_0A10
IO_L08P_0B10
IO_L09N_0/GCLK5D9
IO_L09P_0/GCLK4C10
IO_L10N_0/GCLK7A9
IO_L10P_0/GCLK6C9
IO_L11N_0/GCLK9D8
IO_L11P_0/GCLK8C8
IO_L12N_0/GCLK11B8
IO_L12P_0/GCLK10A8
IO_L13N_0C7
IO_L13P_0A7
IO_L14N_0/VREF_0E7
IO_L14P_0F8
IO_L15N_0B6
IO_L15P_0A6
IO_L16N_0C6
IO_L16P_0D7
IO_L17N_0C5
IO_L17P_0A5
IO_L18N_0B4
IO_L18P_0A4
IO_L19N_0B3
IO_L19P_0A3
IO_L20N_0/PUDC_BD5
IO_L20P_0/VREF_0C4
U10A
XC3S400A-4FTG256C
BA
NK
1 IO_L01N_1/LDC2 N14
IO_L01P_1/HDC N13
IO_L02N_1/LDC0 P15
IO_L02P_1/LDC1 R15
IO_L03N_1/A1 N16
IO_L03P_1/A0 P16
IO_L05N_1/VREF_1 M14
IO_L05P_1 M13
IO_L06N_1/A3 K13
IO_L06P_1/A2 L13
IO_L07N_1/A5 M16
IO_L07P_1/A4 M15
IO_L08N_1/A7 L16
IO_L08P_1/A6 L14
IO_L10N_1/A9 J13
IO_L10P_1/A8 J12
IO_L11N_1/RHCLK1 K14
IO_L11P_1/RHCLK0 K15
IO_L12N_1/TRDY1/RHCLK3 J16
IO_L12P_1/RHCLK2 K16
IO_L14N_1/RHCLK5 H14
IO_L14P_1/RHCLK4 J14
IO_L15N_1/RHCLK7 H16
IO_L15P_1/IRDY1/RHCLK6 H15
IO_L16N_1/A11 F16
IO_L16P_1/A10 G16
IO_L17N_1/A13 G14
IO_L17P_1/A12 H13
IO_L18N_1/A15 F15
IO_L18P_1/A14 E16
IO_L19N_1/A17 F14
IO_L19P_1/A16 G13
IO_L20N_1/A19 F13
IO_L20P_1/A18 E14
IO_L22N_1/A21 D15
IO_L22P_1/A20 D16
IO_L23N_1/A23 D14
IO_L23P_1/A22 E13
IO_L24N_1/A25 C15
IO_L24P_1/A24 C16
U10B
XC3S400A-4FTG256C
FLASH_CE#FLASH_OE#
FLASH_A19
FLASH_A20
Flash_A[21..0]
FLASH_A10FLASH_A11
FLASH_A12FLASH_A13
FLASH_A14FLASH_A15
FLASH_A16FLASH_A17
FLASH_A18
FLASH_A1
FLASH_A2FLASH_A3
FLASH_A4FLASH_A5
FLASH_A6FLASH_A7
FLASH_A8FLASH_A9
IIC_SCLIIC_SDA
V+1
CLK 2
GND3
U6
MAX7381
GND
+3.3V
C160.1uF 0402
Flash_A[21..0]
BANK0_IO3
BANK0_IO19
BANK0_IO22
FLASH_RY/BY#
UART_TXDUART_RXD
CLK_16MHZ
CLK_16MHZ
FPGA_PUDC
FLASH_A21
FLASH_A0
LED4
FLASH_BYTE#FLASH_WE#FLASH_CE#FLASH_OE#
IIC_SCLIIC_SDA
FLASH_RY/BY#UART_RXDUART_TXDFPGA_PUDC
1 R48
1K33 0402
1 R49
1K33 0402
+3.3V
R26
33R2 0402
FLASH_BYTE#FLASH_WE#
LED1LED2LED3LED4
LED1LED2LED3LED4
LED3LED2
LED1BANK1_IO1
BANK0_IO27
BANK0_IO23
BANK0_IO15
BANK0_IO13
BANK0_IO11
BANK0_IO7BANK0_IO1
BANK0_IO29
BANK0_IO21
BANK0_IO9
BANK0_IO4
BANK0_IO28
BANK0_IO25
BANK0_IO20
BANK0_IO17
BANK0_IO12
BANK0_IO8
BANK0_IO5
BANK0_IO26
BANK0_IO24
BANK0_IO18
BANK0_IO14
BANK0_IO10
BANK0_IO6
BANK0_IO16
PSOC_P7_7
PSOC_P7_7 PSOC_P7_7
BANK0_IO31BANK0_IO30
BANK0_IO32
Bank0_IO[32..1] Bank0_IO[32..1]
BANK0_IO2
BANK1_IO1BANK1_IO1
BANK0_IO1BANK0_IO2BANK0_IO3BANK0_IO4BANK0_IO5BANK0_IO6BANK0_IO7BANK0_IO8BANK0_IO9BANK0_IO10BANK0_IO11BANK0_IO12BANK0_IO13BANK0_IO14BANK0_IO15BANK0_IO16BANK0_IO17BANK0_IO18BANK0_IO19BANK0_IO20BANK0_IO21BANK0_IO22BANK0_IO23BANK0_IO24BANK0_IO25BANK0_IO26BANK0_IO27BANK0_IO28BANK0_IO29BANK0_IO30BANK0_IO31BANK0_IO32
P0C1601
P0C1602
P0R2601 P0R2602
P0R4801 P0R4802
P0R4901 P0R4902
P0U601
P0U602
P0U603
P0U100A3
P0U100A4
P0U100A5
P0U100A6
P0U100A7
P0U100A8
P0U100A9
P0U100A10
P0U100A11
P0U100A12
P0U100A13
P0U100A14
P0U100B3
P0U100B4
P0U100B6
P0U100B8
P0U100B10
P0U100B12
P0U100B14
P0U100B15
P0U100C4
P0U100C5
P0U100C6
P0U100C7
P0U100C8
P0U100C9
P0U100C10
P0U100C11
P0U100C12
P0U100C13
P0U100D5
P0U100D7
P0U100D8
P0U100D9
P0U100D10
P0U100D11
P0U100D13
P0U100E7
P0U100E10
P0U100F8
P0U100C15
P0U100C16
P0U100D14
P0U100D15
P0U100D16
P0U100E13
P0U100E14
P0U100E16
P0U100F13
P0U100F14
P0U100F15
P0U100F16
P0U100G13
P0U100G14
P0U100G16
P0U100H13
P0U100H14
P0U100H15
P0U100H16
P0U100J12
P0U100J13
P0U100J14
P0U100J16
P0U100K13
P0U100K14
P0U100K15
P0U100K16
P0U100L13
P0U100L14
P0U100L16
P0U100M13
P0U100M14
P0U100M15
P0U100M16
P0U100N13
P0U100N14
P0U100N16
P0U100P15
P0U100P16
P0U100R15
P0C1601
P0R4802
P0R4902
P0U601
N0BANK00IO0320010
P0BANK00IO0320010
P0U100A14
N0BANK00IO1
N0BANK00IO1
N0BANK00IO1
P0BANK00IO1
P0U100C4
N0BANK00IO2
N0BANK00IO2
N0BANK00IO2
P0BANK00IO2
P0U100A13
N0BANK00IO3
N0BANK00IO3
N0BANK00IO3
P0BANK00IO3
P0U100B14
N0BANK00IO4
N0BANK00IO4
N0BANK00IO4
P0BANK00IO4 P0U100C13
N0BANK00IO5
N0BANK00IO5
N0BANK00IO5 P0BANK00IO5
P0U100D13
N0BANK00IO6
N0BANK00IO6
N0BANK00IO6
P0BANK00IO6
P0U100A12
N0BANK00IO7
N0BANK00IO7
N0BANK00IO7
P0BANK00IO7
P0U100C12
N0BANK00IO8
N0BANK00IO8
N0BANK00IO8
P0BANK00IO8
P0U100B12
N0BANK00IO9
N0BANK00IO9
N0BANK00IO9
P0BANK00IO9
P0U100D11
N0BANK00IO10
N0BANK00IO10
N0BANK00IO10
P0BANK00IO10
P0U100A11
N0BANK00IO11
N0BANK00IO11
N0BANK00IO11
P0BANK00IO11
P0U100C11
N0BANK00IO12
N0BANK00IO12
N0BANK00IO12
P0BANK00IO12
P0U100A10
N0BANK00IO13
N0BANK00IO13
N0BANK00IO13
P0BANK00IO13
P0U100D10
N0BANK00IO14
N0BANK00IO14
N0BANK00IO14
P0BANK00IO14
P0U100A9
N0BANK00IO15
N0BANK00IO15
N0BANK00IO15
P0BANK00IO15
P0U100E10
N0BANK00IO16
N0BANK00IO16
N0BANK00IO16
P0BANK00IO16
P0U100C9
N0BANK00IO17
N0BANK00IO17
N0BANK00IO17
P0BANK00IO17
P0U100D9
N0BANK00IO18
N0BANK00IO18
N0BANK00IO18
P0BANK00IO18
P0U100A8
N0BANK00IO19
N0BANK00IO19
N0BANK00IO19
P0BANK00IO19
P0U100C8
N0BANK00IO20
N0BANK00IO20
N0BANK00IO20
P0BANK00IO20
P0U100B8
N0BANK00IO21
N0BANK00IO21
N0BANK00IO21
P0BANK00IO21
P0U100E7
N0BANK00IO22
N0BANK00IO22
N0BANK00IO22
P0BANK00IO22
P0U100A7
N0BANK00IO23
N0BANK00IO23
N0BANK00IO23
P0BANK00IO23
P0U100D8
N0BANK00IO24
N0BANK00IO24
N0BANK00IO24
P0BANK00IO24
P0U100C7
N0BANK00IO25
N0BANK00IO25 N0BANK00IO25
P0BANK00IO25
P0U100D7
N0BANK00IO26
N0BANK00IO26
N0BANK00IO26
P0BANK00IO26
P0U100A6
N0BANK00IO27
N0BANK00IO27
N0BANK00IO27
P0BANK00IO27
P0U100C6
N0BANK00IO28
N0BANK00IO28
N0BANK00IO28
P0BANK00IO28
P0U100B6
N0BANK00IO29
N0BANK00IO29
N0BANK00IO29
P0BANK00IO29
P0U100C5
N0BANK00IO30
N0BANK00IO30
N0BANK00IO30
P0BANK00IO30
P0U100A5
N0BANK00IO31
N0BANK00IO31
N0BANK00IO31
P0BANK00IO31
P0U100B4
N0BANK00IO32
N0BANK00IO32
N0BANK00IO32
P0BANK00IO32
P0U100E13
N0BANK10IO1
N0BANK10IO1
P0BANK10IO1
P0R2602
P0U100C10
N0CLK016MHZ
N0CLK016MHZ
N0FLASH0A0210000
P0FLASH0A0210000
P0U100P16
N0FLASH0A0
N0FLASH0A0
P0FLASH0A0
P0U100N16
N0FLASH0A1
N0FLASH0A1
P0FLASH0A1 P0U100L13 N0FLASH0A2
N0FLASH0A2 P0FLASH0A2
P0U100K13
N0FLASH0A3
N0FLASH0A3
P0FLASH0A3
P0U100M15
N0FLASH0A4
N0FLASH0A4
P0FLASH0A4
P0U100M16
N0FLASH0A5
N0FLASH0A5
P0FLASH0A5
P0U100L14
N0FLASH0A6
N0FLASH0A6
P0FLASH0A6
P0U100L16
N0FLASH0A7
N0FLASH0A7
P0FLASH0A7
P0U100J12
N0FLASH0A8
N0FLASH0A8
P0FLASH0A8
P0U100J13
N0FLASH0A9
N0FLASH0A9
P0FLASH0A9
P0U100G16
N0FLASH0A10
N0FLASH0A10
P0FLASH0A10
P0U100F16
N0FLASH0A11
N0FLASH0A11
P0FLASH0A11
P0U100H13
N0FLASH0A12
N0FLASH0A12
P0FLASH0A12
P0U100G14
N0FLASH0A13
N0FLASH0A13
P0FLASH0A13
P0U100E16
N0FLASH0A14
N0FLASH0A14
P0FLASH0A14
P0U100F15
N0FLASH0A15
N0FLASH0A15
P0FLASH0A15
P0U100G13
N0FLASH0A16
N0FLASH0A16
P0FLASH0A16
P0U100F14
N0FLASH0A17
N0FLASH0A17
P0FLASH0A17
P0U100E14
N0FLASH0A18
N0FLASH0A18
P0FLASH0A18
P0U100F13
N0FLASH0A19
N0FLASH0A19
P0FLASH0A19
P0U100D16
N0FLASH0A20
N0FLASH0A20
P0FLASH0A20
P0U100D15
N0FLASH0A21
N0FLASH0A21
P0FLASH0A21
P0U100N14 N0FLASH0BYTE# P0FLASH0BYTE#
P0U100P15 N0FLASH0CE# P0FLASH0CE#
P0U100R15 N0FLASH0OE#
P0FLASH0OE#
P0U100A4 N0FLASH0RY/BY# P0FLASH0RY/BY#
P0U100N13 N0FLASH0WE#
P0FLASH0WE#
P0U100D5 N0FPGA0PUDC
P0FPGA0PUDC
P0C1602
P0U603
P0R4801
P0U100M14 N0IIC0SCL
P0IIC0SCL
P0R4901
P0U100M13 N0IIC0SDA
P0IIC0SDA
P0U100D14
N0LED1
N0LED1
P0LED1
P0U100C16
N0LED2
N0LED2
P0LED2
P0U100C15
N0LED3
N0LED3
P0LED3
P0U100B15
N0LED4
N0LED4
P0LED4
P0R2601
P0U602
P0U100B10
P0U100F8
P0U100H14
P0U100H15
P0U100H16
P0U100J14
P0U100J16
P0U100K14
P0U100K15
P0U100K16
N0PSOC0P707
N0PSOC0P707
P0PSOC0P707
P0U100B3 N0UART0RXD
P0UART0RXD
P0U100A3 N0UART0TXD P0UART0TXD
P0FLASH0A0210000
P0BANK00IO0320010
P0BANK10IO1
P0FLASH0BYTE#
P0FLASH0CE#
P0FLASH0OE#
P0FLASH0RY/BY#
P0FLASH0WE#
P0FPGA0PUDC
P0LED1
P0LED2
P0LED3
P0LED4
P0PSOC0P707
P0UART0RXD
P0UART0TXD
P0IIC0SDA
P0IIC0SCL
P0BANK00IO1 P0BANK00IO2 P0BANK00IO3 P0BANK00IO4 P0BANK00IO5 P0BANK00IO6 P0BANK00IO7 P0BANK00IO8 P0BANK00IO9 P0BANK00IO10 P0BANK00IO11 P0BANK00IO12 P0BANK00IO13 P0BANK00IO14 P0BANK00IO15 P0BANK00IO16 P0BANK00IO17 P0BANK00IO18 P0BANK00IO19 P0BANK00IO20 P0BANK00IO21 P0BANK00IO22 P0BANK00IO23 P0BANK00IO24 P0BANK00IO25 P0BANK00IO26 P0BANK00IO27 P0BANK00IO28 P0BANK00IO29 P0BANK00IO30 P0BANK00IO31 P0BANK00IO32
P0FLASH0A0 P0FLASH0A1 P0FLASH0A2 P0FLASH0A3 P0FLASH0A4 P0FLASH0A5 P0FLASH0A6 P0FLASH0A7 P0FLASH0A8 P0FLASH0A9 P0FLASH0A10 P0FLASH0A11 P0FLASH0A12 P0FLASH0A13 P0FLASH0A14 P0FLASH0A15 P0FLASH0A16 P0FLASH0A17 P0FLASH0A18 P0FLASH0A19 P0FLASH0A20 P0FLASH0A21
P0C1601
P0C1602
P0R2601 P0R2602
P0R4801 P0R4802
P0R4901 P0R4902
P0U601
P0U602
P0U603
P0U100A3
P0U100A4
P0U100A5
P0U100A6
P0U100A7
P0U100A8
P0U100A9
P0U100A10
P0U100A11
P0U100A12
P0U100A13
P0U100A14
P0U100B3
P0U100B4
P0U100B6
P0U100B8
P0U100B10
P0U100B12
P0U100B14
P0U100B15
P0U100C4
P0U100C5
P0U100C6
P0U100C7
P0U100C8
P0U100C9
P0U100C10
P0U100C11
P0U100C12
P0U100C13
P0U100D5
P0U100D7
P0U100D8
P0U100D9
P0U100D10
P0U100D11
P0U100D13
P0U100E7
P0U100E10
P0U100F8
P0U100C15
P0U100C16
P0U100D14
P0U100D15
P0U100D16
P0U100E13
P0U100E14
P0U100E16
P0U100F13
P0U100F14
P0U100F15
P0U100F16
P0U100G13
P0U100G14
P0U100G16
P0U100H13
P0U100H14
P0U100H15
P0U100H16
P0U100J12
P0U100J13
P0U100J14
P0U100J16
P0U100K13
P0U100K14
P0U100K15
P0U100K16
P0U100L13
P0U100L14
P0U100L16
P0U100M13
P0U100M14
P0U100M15
P0U100M16
P0U100N13
P0U100N14
P0U100N16
P0U100P15
P0U100P16
P0U100R15
P0C1601
P0R4802
P0R4902
P0U601
N0BANK00IO0320010
P0BANK00IO0320010
P0U100A14
N0BANK00IO1
P0BANK00IO1
P0U100C4
N0BANK00IO2
P0BANK00IO2
P0U100A13
N0BANK00IO3
P0BANK00IO3
P0U100B14
N0BANK00IO4
P0BANK00IO4 P0U100C13
N0BANK00IO5
P0BANK00IO5
P0U100D13
N0BANK00IO6
P0BANK00IO6
P0U100A12
N0BANK00IO7
P0BANK00IO7
P0U100C12
N0BANK00IO8
P0BANK00IO8
P0U100B12
N0BANK00IO9
P0BANK00IO9
P0U100D11
N0BANK00IO10
P0BANK00IO10
P0U100A11
N0BANK00IO11
P0BANK00IO11
P0U100C11
N0BANK00IO12
P0BANK00IO12
P0U100A10
N0BANK00IO13
P0BANK00IO13
P0U100D10
N0BANK00IO14
P0BANK00IO14
P0U100A9
N0BANK00IO15
P0BANK00IO15
P0U100E10
N0BANK00IO16
P0BANK00IO16
P0U100C9
N0BANK00IO17
P0BANK00IO17
P0U100D9
N0BANK00IO18
P0BANK00IO18
P0U100A8
N0BANK00IO19
P0BANK00IO19
P0U100C8
N0BANK00IO20
P0BANK00IO20
P0U100B8
N0BANK00IO21
P0BANK00IO21
P0U100E7
N0BANK00IO22
P0BANK00IO22
P0U100A7
N0BANK00IO23
P0BANK00IO23
P0U100D8
N0BANK00IO24
P0BANK00IO24
P0U100C7
N0BANK00IO25
P0BANK00IO25
P0U100D7
N0BANK00IO26
P0BANK00IO26
P0U100A6
N0BANK00IO27
P0BANK00IO27
P0U100C6
N0BANK00IO28
P0BANK00IO28
P0U100B6
N0BANK00IO29
P0BANK00IO29
P0U100C5
N0BANK00IO30
P0BANK00IO30
P0U100A5
N0BANK00IO31
P0BANK00IO31
P0U100B4
N0BANK00IO32
P0BANK00IO32
N0BANK10IO1
P0U100E13
P0BANK10IO1
N0CLK016MHZ
P0R2602
P0U100C10
N0FLASH0A0210000
P0FLASH0A0210000
P0U100P16
N0FLASH0A0
P0FLASH0A0
P0U100N16
N0FLASH0A1
P0FLASH0A1 P0U100L13 N0FLASH0A2
P0FLASH0A2
P0U100K13
N0FLASH0A3
P0FLASH0A3
P0U100M15
N0FLASH0A4
P0FLASH0A4
P0U100M16
N0FLASH0A5
P0FLASH0A5
P0U100L14
N0FLASH0A6
P0FLASH0A6
P0U100L16
N0FLASH0A7
P0FLASH0A7
P0U100J12
N0FLASH0A8
P0FLASH0A8
P0U100J13
N0FLASH0A9
P0FLASH0A9
P0U100G16
N0FLASH0A10
P0FLASH0A10
P0U100F16
N0FLASH0A11
P0FLASH0A11
P0U100H13
N0FLASH0A12
P0FLASH0A12
P0U100G14
N0FLASH0A13
P0FLASH0A13
P0U100E16
N0FLASH0A14
P0FLASH0A14
P0U100F15
N0FLASH0A15
P0FLASH0A15
P0U100G13
N0FLASH0A16
P0FLASH0A16
P0U100F14
N0FLASH0A17
P0FLASH0A17
P0U100E14
N0FLASH0A18
P0FLASH0A18
P0U100F13
N0FLASH0A19
P0FLASH0A19
P0U100D16
N0FLASH0A20
P0FLASH0A20
P0U100D15
N0FLASH0A21
P0FLASH0A21
N0FLASH0BYTE# P0U100N14
P0FLASH0BYTE#
N0FLASH0CE# P0U100P15
P0FLASH0CE#
N0FLASH0OE# P0U100R15
P0FLASH0OE#
N0FLASH0RY/BY# P0U100A4 P0FLASH0RY/BY#
N0FLASH0WE# P0U100N13
P0FLASH0WE#
N0FPGA0PUDC P0U100D5 P0FPGA0PUDC
P0C1602
P0U603
N0IIC0SCL
P0R4801
P0U100M14
P0IIC0SCL
N0IIC0SDA
P0R4901
P0U100M13
P0IIC0SDA
N0LED1
P0U100D14
P0LED1 N0LED2
P0U100C16
P0LED2
N0LED3
P0U100C15
P0LED3
N0LED4
P0U100B15
P0LED4
P0R2601
P0U602
P0U100B10
P0U100F8
P0U100H14
P0U100H15
P0U100H16
P0U100J14
P0U100J16
P0U100K14
P0U100K15
N0PSOC0P707
P0U100K16
P0PSOC0P707
N0UART0RXD P0U100B3
P0UART0RXD
N0UART0TXD P0U100A3 P0UART0TXD
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 5 - FPGA2 (Banks 2 & 3)Size: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 5 12
BA
NK
2IO_L01N_2/M0P4
IO_L01P_2/M1N4
IO_L02N_2/CSO_BT2
IO_L02P_2/M2R2
IO_L03N_2/VS2T3
IO_L03P_2/RDWR_BR3
IO_L04N_2/VS0P5
IO_L04P_2/VS1N6
IO_L05N_2R5
IO_L05P_2T4
IO_L06N_2/D6T6
IO_L06P_2/D7T5
IO_L07N_2P6
IO_L07P_2N7
IO_L08N_2/D4N8
IO_L08P_2/D5P7
IO_L09N_2/GCLK13T7
IO_L09P_2/GCLK12R7
IO_L10N_2/GCLK15T8
IO_L10P_2/GCLK14P8
IO_L11N_2/GCLK1P9
IO_L11P_2/GCLK0N9
IO_L12N_2/GCLK3T9
IO_L12P_2/GCLK2R9
IO_L13N_2M10
IO_L13P_2N10
IO_L14N_2/MOSI/CSI_BP10
IO_L14P_2T10
IO_L15N_2/DOUTR11
IO_L15P_2/AWAKET11
IO_L16N_2N11
IO_L16P_2P11
IO_L17N_2/D3P12
IO_L17P_2/INIT_BT12
IO_L18N_2/D1R13
IO_L18P_2/D2T13
IO_L19N_2P13
IO_L19P_2N12
IO_L20N_2/CCLKR14
IO_L20P_2/D0/DIN/MISOT14
U10C
XC3S400A-4FTG256C
BA
NK
3 IO_L01N_3 C1
IO_L01P_3 C2
IO_L02N_3 D3
IO_L02P_3 D4
IO_L03N_3 E1
IO_L03P_3 D1
IO_L05N_3 E2
IO_L05P_3 E3
IO_L07N_3 G4
IO_L07P_3 F3
IO_L08N_3/VREF_3 G1
IO_L08P_3 F1
IO_L09N_3 H4
IO_L09P_3 G3
IO_L10N_3 H5
IO_L10P_3 H6
IO_L11N_3/LHCLK1 H1
IO_L11P_3/LHCLK0 G2
IO_L12N_3/IRDY2/LHCLK3 J3
IO_L12P_3/LHCLK2 H3
IO_L14N_3/LHCLK5 J1
IO_L14P_3/LHCLK4 J2
IO_L15N_3/LHCLK7 K1
IO_L15P_3/TRDY2/LHCLK6 K3
IO_L16N_3 L2
IO_L16P_3/VREF_3 L1
IO_L17N_3 J6
IO_L17P_3 J4
IO_L18N_3 L3
IO_L18P_3 K4
IO_L19N_3 L4
IO_L19P_3 M3
IO_L20N_3 N1
IO_L20P_3 M1
IO_L22N_3 P1
IO_L22P_3 N2
IO_L23N_3 P2
IO_L23P_3 R1
IO_L24N_3 M4
IO_L24P_3 N3
U10D
XC3S400A-4FTG256C
Flash_D[7..0] FLASH_D0FLASH_D1FLASH_D2FLASH_D3FLASH_D4FLASH_D5FLASH_D6FLASH_D7
FLASH_D1FLASH_D2
FLASH_D3
FLASH_D4FLASH_D5
FLASH_D6FLASH_D7
FPGA_MOSI
PSOC_FPGA_M0PSOC_FPGA_M1PSOC_FPGA_M2
Flash_D[7..0]
FPGA_RESETFPGA_PUSH AFPGA_PUSH B
CLK_12MHZ
2468
1357
JP4
HEADER 4X2 SM
FPGA_PUDC
GND
FPGA_SPI_SEL#
FLASH_D8FLASH_D9FLASH_D10FLASH_D11FLASH_D12FLASH_D13FLASH_D14
Flash_D[14..8] Flash_D[14..8]
FLASH_D8
FLASH_D9
FLASH_D12FLASH_D13
FLASH_D14
Note: Flash data bit D15 is on Flash_A0
18273645
RP1
1K0
+3.3V
GND
R10
1K0 0402
D6
LED_Green
GND
TP5TEST PAD
DOUT
CLK_32KHZ
FLASH_D10
+3.3V
FPGA_PUDC
PSOC_FPGA_M0PSOC_FPGA_M1PSOC_FPGA_M2
FPGA_VS0FPGA_VS1
FPGA_VS2
AWAKE
FPGA_INIT_B
SPI_CLK
FPGA_RESET
FPGA_PUSH B
FPGA_INIT_B
FPGA_SPI_SEL#
SF_W#SF_HOLD#
FLASH_RESET#
FLASH_D11
R40
1K0 0402R34
1K0 0402R32
1K0 0402
R41
DNP 0402R35
DNP 0402R33
DNP 0402
18273645
RP2
10K0
CLK_32KHZ
FPGA_MOSI
FLASH_RESET#
CLK_12MHZ
PSOC_P7_0PSOC_P5_7
PSOC_P5_3PSOC_P5_4
FPGA_PUSH_C
PSOC_P4_6
PSOC_P5_6
PSOC_P7_0PSOC_P5_7PSOC_P5_6PSOC_P5_4PSOC_P5_3
PSOC_P4_6
FPGA_RESETFPGA_PUSH AFPGA_PUSH B
SF_HOLD#SF_W#
SPI_CLK
PSOC_P2_1
PSOC_P2_5PSOC_P2_3
PSOC_P2_7
PSOC_P2_1PSOC_P2_3PSOC_P2_5PSOC_P2_7PSOC_P0_4 PSOC_P0_4
PSOC_P2_1DIGI2_3
PSOC_P4_6DIGI2_2FPGA_PUSH A
PSOC_P5_7PSOC_P5_3
FPGA_PUSH_C
PSOC_P5_4
BANK3_IO1
PSOC_P2_3PSOC_P2_7
PSOC_P2_5PSOC_P0_4
DIGI2_1
PSOC_P5_6
DIGI2_0
DIGI1_3
PSOC_P7_0
DIGI1_2
DIGI1_1DIGI1_0
DIGI1_0DIGI1_1DIGI1_2DIGI1_3
DIGI2_0DIGI2_1DIGI2_2DIGI2_3
DIGI1_[3..0]
DIGI2_[3..0]
BANK3_IO2
BANK3_IO1 BANK3_IO1BANK3_IO2 BANK3_IO2
R24
49R9 0402FLASH_D0
FPGA_MISO FPGA_MISO
R27
49R9 0402
DIGI1_[3..0]
DIGI2_[3..0]
JP4 default settings: 3:4, 5:6 jumpered, 1:2, 7:8 open
M2 M1 M0 PUDC_BConfiguration Mode: PC Pull-up: JP4 5:6 JP4 3:4 JP4 1:2 JP4 7:8Master Serial Yes Closed Closed Closed ClosedMaster Serial No Closed Closed Closed OpenSlave Serial Yes Open Open Open ClosedSlave Serial No Open Open Open OpenMaster SPI Yes Closed Closed Open ClosedMaster SPI No Closed Closed Open OpenBPI Up Yes Closed Open Closed ClosedBPI Up No Closed Open Closed OpenSlave Parallel Yes Open Open Closed ClosedSlave Parallel No Open Open Closed OpenJTAG Yes Open Closed Open ClosedJTAG No Open Closed Open Open
FPGA_PUSH_C
P0D601 P0D602
P0JP401 P0JP402
P0JP403 P0JP404
P0JP405 P0JP406
P0JP407 P0JP408
P0R1001 P0R1002
P0R2401 P0R2402
P0R2701 P0R2702
P0R3201 P0R3202 P0R3301 P0R3302
P0R3401 P0R3402 P0R3501 P0R3502
P0R4001 P0R4002 P0R4101 P0R4102
P0RP101
P0RP102
P0RP103
P0RP104 P0RP105
P0RP106
P0RP107
P0RP108
P0RP201
P0RP202
P0RP203
P0RP204 P0RP205
P0RP206
P0RP207
P0RP208
P0TP501
P0U100M10
P0U100N4
P0U100N6
P0U100N7
P0U100N8
P0U100N9
P0U100N10
P0U100N11
P0U100N12
P0U100P4
P0U100P5
P0U100P6
P0U100P7
P0U100P8
P0U100P9
P0U100P10
P0U100P11
P0U100P12
P0U100P13
P0U100R2
P0U100R3
P0U100R5
P0U100R7
P0U100R9
P0U100R11
P0U100R13
P0U100R14
P0U100T2
P0U100T3
P0U100T4
P0U100T5
P0U100T6
P0U100T7
P0U100T8
P0U100T9
P0U100T10
P0U100T11
P0U100T12
P0U100T13
P0U100T14
P0U100C1
P0U100C2
P0U100D1
P0U100D3
P0U100D4
P0U100E1
P0U100E2
P0U100E3
P0U100F1
P0U100F3
P0U100G1
P0U100G2
P0U100G3
P0U100G4
P0U100H1
P0U100H3
P0U100H4
P0U100H5
P0U100H6
P0U100J1
P0U100J2
P0U100J3
P0U100J4
P0U100J6
P0U100K1
P0U100K3
P0U100K4
P0U100L1
P0U100L2
P0U100L3
P0U100L4
P0U100M1
P0U100M3
P0U100M4
P0U100N1
P0U100N2
P0U100N3
P0U100P1
P0U100P2
P0U100R1
P0R3201
P0R3401
P0R4001
P0RP205
P0RP206
P0RP207
P0RP208
P0R1002 P0U100T11 N0AWAKE
P0U100D3
N0BANK30IO1
N0BANK30IO1
P0BANK30IO1
P0U100D4
N0BANK30IO2
N0BANK30IO2
P0BANK30IO2
P0U100N9 N0CLK012MHZ
P0CLK012MHZ
P0U100T7 N0CLK032KHZ P0CLK032KHZ
N0DIGI10030000 P0DIGI10030000
P0U100R1
N0DIGI100
N0DIGI100
N0DIGI100
P0DIGI100
P0U100P2
N0DIGI101
N0DIGI101
N0DIGI101
P0DIGI101
P0U100P1
N0DIGI102
N0DIGI102
N0DIGI102
P0DIGI102
P0U100N2
N0DIGI103
N0DIGI103
N0DIGI103
P0DIGI103
N0DIGI20030000
P0DIGI20030000
P0U100N1
N0DIGI200
N0DIGI200
N0DIGI200
P0DIGI200
P0U100M1
N0DIGI201
N0DIGI201
N0DIGI201
P0DIGI201
P0U100K1
N0DIGI202
N0DIGI202
N0DIGI202
P0DIGI202
P0U100G1
N0DIGI203
N0DIGI203
N0DIGI203
P0DIGI203
P0TP501
P0U100R11 N0DOUT
P0R2402
P0U100T14
N0FLASH0D0
N0FLASH0D0
N0FLASH0D0
P0FLASH0D0
P0U100R13
N0FLASH0D1
N0FLASH0D1
N0FLASH0D1
P0FLASH0D1
P0U100T13
N0FLASH0D2
N0FLASH0D2
N0FLASH0D2
P0FLASH0D2
P0U100P12
N0FLASH0D3
N0FLASH0D3
N0FLASH0D3
P0FLASH0D3
P0U100N8
N0FLASH0D4
N0FLASH0D4
N0FLASH0D4
P0FLASH0D4
P0U100P7
N0FLASH0D5
N0FLASH0D5
N0FLASH0D5
P0FLASH0D5
P0U100T6
N0FLASH0D6
N0FLASH0D6
N0FLASH0D6
P0FLASH0D6
P0U100T5
N0FLASH0D7
N0FLASH0D7
N0FLASH0D7
P0FLASH0D7
P0U100P11
N0FLASH0D8
N0FLASH0D8
N0FLASH0D8
P0FLASH0D8
P0U100R3
N0FLASH0D9
N0FLASH0D9
N0FLASH0D9
P0FLASH0D9
P0U100N11
N0FLASH0D10
N0FLASH0D10
N0FLASH0D10
P0FLASH0D10
P0U100N7
N0FLASH0D11
N0FLASH0D11
N0FLASH0D11
P0FLASH0D11
P0U100R5
N0FLASH0D12
N0FLASH0D12
N0FLASH0D12
P0FLASH0D12
P0U100T4
N0FLASH0D13
N0FLASH0D13
N0FLASH0D13
P0FLASH0D13
P0U100P6
N0FLASH0D14
N0FLASH0D14
N0FLASH0D14
P0FLASH0D14
N0FLASH0D0140080
P0FLASH0D0140080
N0FLASH0D070000
P0FLASH0D070000
P0U100T10 N0FLASH0RESET# P0FLASH0RESET#
P0U100T12 N0FPGA0INIT0B
P0FPGA0INIT0B
P0R2401 N0FPGA0MISO
P0FPGA0MISO
P0R2701
N0FPGA0MOSI
P0FPGA0MOSI
P0JP407
P0RP201
N0FPGA0PUDC P0FPGA0PUDC
P0U100K3
N0FPGA0PUSH A
N0FPGA0PUSH A
P0FPGA0PUSH A
P0U100H5
N0FPGA0PUSH B
N0FPGA0PUSH B
P0FPGA0PUSH B
P0U100L3
N0FPGA0PUSH0C
N0FPGA0PUSH0C
P0FPGA0PUSH0C
P0U100H4
N0FPGA0RESET
N0FPGA0RESET
P0FPGA0RESET
P0U100T2
N0FPGA0SPI0SEL# P0FPGA0SPI0SEL#
P0R3402 P0R3502
P0U100P5 N0FPGA0VS0
P0R3202 P0R3302
P0U100N6 N0FPGA0VS1
P0R4002 P0R4102
P0U100T3 N0FPGA0VS2
P0D601
P0R3301
P0R3501
P0R4101
P0RP105
P0RP106
P0RP107
P0RP108
P0D602 P0R1001
P0JP402 P0RP101
P0JP404 P0RP102
P0JP406 P0RP103
P0JP408 P0RP104
P0R2702
P0U100P10
P0U100C1
P0U100C2
P0U100D1
P0U100E1
P0U100E2
P0U100E3
P0U100F3
P0U100G3
P0U100G4
P0U100H6
P0U100J3
P0U100J4
P0U100J6
P0U100K4
P0U100L4
P0U100M10
P0U100N10
P0U100P8
P0U100P9
P0U100R7
P0U100R9
P0U100T8
P0U100T9
P0JP401
P0RP204
P0U100P4
N0PSOC0FPGA0M0
P0PSOC0FPGA0M0
P0JP403
P0RP203
P0U100N4
N0PSOC0FPGA0M1
P0PSOC0FPGA0M1
P0JP405
P0RP202
P0U100R2
N0PSOC0FPGA0M2
P0PSOC0FPGA0M2
P0U100J1
N0PSOC0P004
N0PSOC0P004
P0PSOC0P004
P0U100F1
N0PSOC0P201
N0PSOC0P201
P0PSOC0P201
P0U100G2
N0PSOC0P203
N0PSOC0P203
P0PSOC0P203
P0U100H3
N0PSOC0P205
N0PSOC0P205
P0PSOC0P205
P0U100H1
N0PSOC0P207
N0PSOC0P207
P0PSOC0P207
P0U100J2
N0PSOC0P406
N0PSOC0P406
P0PSOC0P406
P0U100L2
N0PSOC0P503
N0PSOC0P503
P0PSOC0P503
P0U100M3
N0PSOC0P504
N0PSOC0P504
P0PSOC0P504
P0U100M4
N0PSOC0P506
N0PSOC0P506
P0PSOC0P506
P0U100L1
N0PSOC0P507
N0PSOC0P507
P0PSOC0P507
P0U100N3
N0PSOC0P700
N0PSOC0P700
P0PSOC0P700
P0U100P13 N0SF0HOLD#
P0SF0HOLD#
P0U100N12 N0SF0W#
P0SF0W#
P0U100R14 N0SPI0CLK P0SPI0CLK
P0FLASH0D0140080
P0FLASH0D070000
P0DIGI20030000
P0DIGI10030000
P0SPI0CLK
P0BANK30IO1
P0BANK30IO2
P0CLK012MHZ
P0CLK032KHZ
P0FLASH0RESET#
P0FPGA0INIT0B
P0FPGA0MISO
P0FPGA0MOSI
P0FPGA0PUDC
P0FPGA0PUSH0C
P0FPGA0PUSH A
P0FPGA0PUSH B
P0FPGA0RESET
P0FPGA0SPI0SEL#
P0PSOC0FPGA0M0
P0PSOC0FPGA0M1
P0PSOC0FPGA0M2
P0PSOC0P004
P0PSOC0P201
P0PSOC0P203
P0PSOC0P205
P0PSOC0P207
P0PSOC0P406
P0PSOC0P503
P0PSOC0P504
P0PSOC0P506
P0PSOC0P507
P0PSOC0P700
P0SF0HOLD#
P0SF0W#
P0DIGI100 P0DIGI101 P0DIGI102 P0DIGI103
P0DIGI200 P0DIGI201 P0DIGI202 P0DIGI203
P0FLASH0D0 P0FLASH0D1 P0FLASH0D2 P0FLASH0D3 P0FLASH0D4 P0FLASH0D5 P0FLASH0D6 P0FLASH0D7
P0FLASH0D8 P0FLASH0D9 P0FLASH0D10 P0FLASH0D11 P0FLASH0D12 P0FLASH0D13 P0FLASH0D14
P0D601 P0D602
P0JP401 P0JP402
P0JP403 P0JP404
P0JP405 P0JP406
P0JP407 P0JP408
P0R1001 P0R1002
P0R2401 P0R2402
P0R2701 P0R2702
P0R3201 P0R3202 P0R3301 P0R3302
P0R3401 P0R3402 P0R3501 P0R3502
P0R4001 P0R4002 P0R4101 P0R4102
P0RP101
P0RP102
P0RP103
P0RP104 P0RP105
P0RP106
P0RP107
P0RP108
P0RP201
P0RP202
P0RP203
P0RP204 P0RP205
P0RP206
P0RP207
P0RP208
P0TP501
P0U100M10
P0U100N4
P0U100N6
P0U100N7
P0U100N8
P0U100N9
P0U100N10
P0U100N11
P0U100N12
P0U100P4
P0U100P5
P0U100P6
P0U100P7
P0U100P8
P0U100P9
P0U100P10
P0U100P11
P0U100P12
P0U100P13
P0U100R2
P0U100R3
P0U100R5
P0U100R7
P0U100R9
P0U100R11
P0U100R13
P0U100R14
P0U100T2
P0U100T3
P0U100T4
P0U100T5
P0U100T6
P0U100T7
P0U100T8
P0U100T9
P0U100T10
P0U100T11
P0U100T12
P0U100T13
P0U100T14
P0U100C1
P0U100C2
P0U100D1
P0U100D3
P0U100D4
P0U100E1
P0U100E2
P0U100E3
P0U100F1
P0U100F3
P0U100G1
P0U100G2
P0U100G3
P0U100G4
P0U100H1
P0U100H3
P0U100H4
P0U100H5
P0U100H6
P0U100J1
P0U100J2
P0U100J3
P0U100J4
P0U100J6
P0U100K1
P0U100K3
P0U100K4
P0U100L1
P0U100L2
P0U100L3
P0U100L4
P0U100M1
P0U100M3
P0U100M4
P0U100N1
P0U100N2
P0U100N3
P0U100P1
P0U100P2
P0U100R1
P0R3201
P0R3401
P0R4001
P0RP205
P0RP206
P0RP207
P0RP208
N0AWAKE P0R1002
P0U100T11
N0BANK30IO1
P0U100D3
P0BANK30IO1 N0BANK30IO2
P0U100D4
P0BANK30IO2
N0CLK012MHZ P0U100N9 P0CLK012MHZ
N0CLK032KHZ P0U100T7 P0CLK032KHZ
N0DIGI10030000 P0DIGI10030000
P0U100R1
N0DIGI100 P0DIGI100
P0U100P2
N0DIGI101 P0DIGI101
P0U100P1
N0DIGI102 P0DIGI102
P0U100N2
N0DIGI103 P0DIGI103
N0DIGI20030000
P0DIGI20030000
P0U100N1
N0DIGI200
P0DIGI200
P0U100M1
N0DIGI201
P0DIGI201
P0U100K1
N0DIGI202
P0DIGI202
P0U100G1
N0DIGI203
P0DIGI203
N0DOUT
P0TP501
P0U100R11
P0R2402
P0U100T14
N0FLASH0D0
P0FLASH0D0
P0U100R13
N0FLASH0D1
P0FLASH0D1
P0U100T13
N0FLASH0D2
P0FLASH0D2
P0U100P12
N0FLASH0D3
P0FLASH0D3
P0U100N8
N0FLASH0D4
P0FLASH0D4
P0U100P7
N0FLASH0D5
P0FLASH0D5
P0U100T6
N0FLASH0D6
P0FLASH0D6
P0U100T5
N0FLASH0D7
P0FLASH0D7
P0U100P11
N0FLASH0D8
P0FLASH0D8
P0U100R3
N0FLASH0D9
P0FLASH0D9
P0U100N11
N0FLASH0D10
P0FLASH0D10
P0U100N7
N0FLASH0D11
P0FLASH0D11
P0U100R5
N0FLASH0D12
P0FLASH0D12
P0U100T4
N0FLASH0D13
P0FLASH0D13
P0U100P6
N0FLASH0D14
P0FLASH0D14
N0FLASH0D0140080
P0FLASH0D0140080
N0FLASH0D070000
P0FLASH0D070000
N0FLASH0RESET# P0U100T10 P0FLASH0RESET#
N0FPGA0INIT0B P0U100T12
P0FPGA0INIT0B
N0FPGA0MISO P0R2401 P0FPGA0MISO
N0FPGA0MOSI
P0R2701
P0FPGA0MOSI
P0JP407
P0RP201
N0FPGA0PUSH A
P0U100K3
P0FPGA0PUSH A
N0FPGA0PUSH B
P0U100H5
P0FPGA0PUSH B
N0FPGA0PUSH0C
P0U100L3
P0FPGA0PUSH0C
N0FPGA0RESET
P0U100H4
P0FPGA0RESET
N0FPGA0SPI0SEL#
P0U100T2
P0FPGA0SPI0SEL#
N0FPGA0VS0
P0R3402 P0R3502
P0U100P5
N0FPGA0VS1
P0R3202 P0R3302
P0U100N6
N0FPGA0VS2
P0R4002 P0R4102
P0U100T3
P0D601
P0R3301
P0R3501
P0R4101
P0RP105
P0RP106
P0RP107
P0RP108
P0D602 P0R1001
P0JP402 P0RP101
P0JP404 P0RP102
P0JP406 P0RP103
P0JP408 P0RP104
P0R2702
P0U100P10
P0U100C1
P0U100C2
P0U100D1
P0U100E1
P0U100E2
P0U100E3
P0U100F3
P0U100G3
P0U100G4
P0U100H6
P0U100J3
P0U100J4
P0U100J6
P0U100K4
P0U100L4
P0U100M10
P0U100N10
P0U100P8
P0U100P9
P0U100R7
P0U100R9
P0U100T8
P0U100T9
N0PSOC0FPGA0M0
P0JP401
P0RP204
P0U100P4
P0PSOC0FPGA0M0 N0PSOC0FPGA0M1
P0JP403
P0RP203
P0U100N4
P0PSOC0FPGA0M1
N0PSOC0FPGA0M2
P0JP405
P0RP202
P0U100R2
P0PSOC0FPGA0M2
N0PSOC0P004
P0U100J1
P0PSOC0P004
N0PSOC0P201
P0U100F1
P0PSOC0P201
N0PSOC0P203
P0U100G2
P0PSOC0P203
N0PSOC0P205
P0U100H3
P0PSOC0P205
N0PSOC0P207
P0U100H1
P0PSOC0P207
N0PSOC0P406
P0U100J2
P0PSOC0P406
N0PSOC0P503
P0U100L2
P0PSOC0P503
N0PSOC0P504
P0U100M3
P0PSOC0P504
N0PSOC0P506
P0U100M4
P0PSOC0P506
N0PSOC0P507
P0U100L1
P0PSOC0P507
N0PSOC0P700
P0U100N3
P0PSOC0P700
N0SF0HOLD# P0U100P13 P0SF0HOLD#
N0SF0W# P0U100N12
P0SF0W#
N0SPI0CLK P0U100R14 P0SPI0CLK
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 6 - FPGA 3Size: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 6 12
IP_0D6
IP_0D12
IP_0E6
IP_0F7
IP_0F9
IP_0F10
IP_0/VREF_0E9
IP_L04N_1/VREF_1K12
IP_L04P_1K11
IP_L09N_1J11
IP_L09P_1/VREF_1J10
IP_L13N_1H11
IP_L13P_1H10
IP_L21N_1G11
IP_L21P_1/VREF_1G12
IP_L25N_1F11
IP_L25P_1/VREF_1F12
IP_2L7
IP_2L8
IP_2/VREF_2L9
IP_2/VREF_2L10
IP_2/VREF_2M7
IP_2/VREF_2M8
IP_2/VREF_2M11
IP_2/VREF_2N5
IP_L04N_3/VREF_3F4
IP_L04P_3E4
IP_L06N_3/VREF_3G5
IP_L06P_3G6
IP_L13N_3J7
IP_L13P_3H7
IP_L21N_3K6
IP_L21P_3K5
IP_L25N_3/VREF_3L6
IP_L25P_3L5
U10E
XC3S400A-4FTG256C
SUSPEND R16
DONE T15
PROG_B A2
TCK A15
TDI B1
TDO B16
TMS B2
U10F
XC3S400A-4FTG256C
+3.3V
GND
NC14 GND 13
NC12 GND 11
TDI10 GND 9
TDO8 GND 7
TCK6 GND 5
TMS4 GND 3
VREF2 GND 1
J5
Xilinx Parallel IV Connector
PSOC_FPGA_PROG
1 3
2
JP5
PO_RESET#
+3.3V
GND
R55
10K0 0402
R54
10K0 0402
1
24
53
U9
NC7SV08FPGA_PROG
FPGA_SUSPEND
GND
245
1
3
U18
NC7SV126
245
1
3
U16
NC7SV126
2 45
1
3
U17
NC7SV126
+3.3V
R43
33R2 0402
R38
33R2 0402
245
1
3
U15NC7SV126
JTAG_TMSJTAG_TCKJTAG_TDOJTAG_TDI
+3.3V
GND
+3.3V
GND
JTAG_MUX_CTL
1 82 73 64 5
RP4
4K7
+3.3V
JTAG_TDOJTAG_TDI
JTAG_TCKJTAG_TMS
CABLE_TDICABLE_TDOCABLE_TCKCABLE_TMS
JP5 Default Setting 2:3 (Suspend Mode disabled)
3
1
2
Q12N7002
R28330R 0603
+3.3V
FPGA_DONE
GND
+3.3V
R5681R 0603
D7
LED_Blue
FPGA_DONE
JTAG_TMSJTAG_TCKJTAG_TDI
R58
10K0 0402
P0D701 P0D702
P0J501 P0J502
P0J503 P0J504
P0J505 P0J506
P0J507 P0J508
P0J509 P0J5010
P0J5011 P0J5012
P0J5013 P0J5014
P0JP501
P0JP502
P0JP503
P0Q101
P0Q102
P0Q103
P0R501
P0R502
P0R2801
P0R2802
P0R3801 P0R3802
P0R4301 P0R4302
P0R5401 P0R5402 P0R5501 P0R5502
P0R5801 P0R5802
P0RP401
P0RP402
P0RP403
P0RP404 P0RP405
P0RP406
P0RP407
P0RP408
P0U901
P0U902
P0U903
P0U904
P0U905
P0U100D6
P0U100D12
P0U100E4
P0U100E6
P0U100E9
P0U100F4
P0U100F7
P0U100F9
P0U100F10
P0U100F11
P0U100F12
P0U100G5
P0U100G6
P0U100G11
P0U100G12
P0U100H7
P0U100H10
P0U100H11
P0U100J7
P0U100J10
P0U100J11
P0U100K5
P0U100K6
P0U100K11
P0U100K12
P0U100L5
P0U100L6
P0U100L7
P0U100L8
P0U100L9
P0U100L10
P0U100M7
P0U100M8
P0U100M11
P0U100N5
P0U100A2
P0U100A15
P0U100B1
P0U100B2
P0U100B16
P0U100R16
P0U100T15
P0U1501
P0U1502
P0U1503
P0U1504
P0U1505
P0U1601
P0U1602
P0U1603
P0U1604
P0U1605
P0U1701
P0U1702
P0U1703
P0U1704
P0U1705
P0U1801
P0U1802
P0U1803
P0U1804
P0U1805
P0J502
P0R501 P0R2801
P0R5401
P0R5801
P0RP401
P0RP402
P0RP403
P0RP404
P0U905
P0U1505
P0U1605
P0U1705
P0U1805
P0J506 P0R4302
N0CABLE0TCK
P0J5010
P0U1802
N0CABLE0TDI
P0J508
P0U1704
N0CABLE0TDO
P0J504
P0U1502
N0CABLE0TMS
P0Q101
P0R2802
P0U100T15
N0FPGA0DONE
P0FPGA0DONE
P0U904 P0U100A2 N0FPGA0PROG
P0JP502
P0U100R16
N0FPGA0SUSPEND
P0J501
P0J503
P0J505
P0J507
P0J509
P0J5011
P0J5013
P0Q102
P0R5502
P0U903
P0U1503
P0U1603
P0U1703
P0U1803
P0U1501
P0U1601
P0U1701
P0U1801
P0JTAG0MUX0CTL
P0R3801
P0RP406
P0U100A15
N0JTAG0TCK
N0JTAG0TCK
P0JTAG0TCK
P0RP407
P0U100B1
P0U1804
N0JTAG0TDI
N0JTAG0TDI
P0JTAG0TDI
P0U100B16
P0U1702 N0JTAG0TDO
P0JTAG0TDO
P0RP405
P0U100B2
P0U1504
N0JTAG0TMS
N0JTAG0TMS P0JTAG0TMS
P0D701
P0Q103
P0D702
P0R502
P0J5012
P0J5014
P0JP501 P0R5402
P0JP503
P0R5501
P0R3802 P0U1604
P0R4301
P0U1602
P0RP408
P0U100D6
P0U100D12
P0U100E4
P0U100E6
P0U100E9
P0U100F4
P0U100F7
P0U100F9
P0U100F10
P0U100F11
P0U100F12
P0U100G5
P0U100G6
P0U100G11
P0U100G12
P0U100H7
P0U100H10
P0U100H11
P0U100J7
P0U100J10
P0U100J11
P0U100K5
P0U100K6
P0U100K11
P0U100K12
P0U100L5
P0U100L6
P0U100L7
P0U100L8
P0U100L9
P0U100L10
P0U100M7
P0U100M8
P0U100M11
P0U100N5
P0U901
P0PO0RESET#
P0R5802
P0U902
P0PSOC0FPGA0PROG
P0PO0RESET#
P0FPGA0DONE
P0JTAG0MUX0CTL
P0JTAG0TCK
P0JTAG0TDI
P0JTAG0TDO
P0JTAG0TMS
P0PSOC0FPGA0PROG
P0D701 P0D702
P0J501 P0J502
P0J503 P0J504
P0J505 P0J506
P0J507 P0J508
P0J509 P0J5010
P0J5011 P0J5012
P0J5013 P0J5014
P0JP501
P0JP502
P0JP503
P0Q101
P0Q102
P0Q103
P0R501
P0R502
P0R2801
P0R2802
P0R3801 P0R3802
P0R4301 P0R4302
P0R5401 P0R5402 P0R5501 P0R5502
P0R5801 P0R5802
P0RP401
P0RP402
P0RP403
P0RP404 P0RP405
P0RP406
P0RP407
P0RP408
P0U901
P0U902
P0U903
P0U904
P0U905
P0U100D6
P0U100D12
P0U100E4
P0U100E6
P0U100E9
P0U100F4
P0U100F7
P0U100F9
P0U100F10
P0U100F11
P0U100F12
P0U100G5
P0U100G6
P0U100G11
P0U100G12
P0U100H7
P0U100H10
P0U100H11
P0U100J7
P0U100J10
P0U100J11
P0U100K5
P0U100K6
P0U100K11
P0U100K12
P0U100L5
P0U100L6
P0U100L7
P0U100L8
P0U100L9
P0U100L10
P0U100M7
P0U100M8
P0U100M11
P0U100N5
P0U100A2
P0U100A15
P0U100B1
P0U100B2
P0U100B16
P0U100R16
P0U100T15
P0U1501
P0U1502
P0U1503
P0U1504
P0U1505
P0U1601
P0U1602
P0U1603
P0U1604
P0U1605
P0U1701
P0U1702
P0U1703
P0U1704
P0U1705
P0U1801
P0U1802
P0U1803
P0U1804
P0U1805
P0J502
P0R501 P0R2801
P0R5401
P0R5801
P0RP401
P0RP402
P0RP403
P0RP404
P0U905
P0U1505
P0U1605
P0U1705
P0U1805
N0CABLE0TCK P0J506
P0R4302
N0CABLE0TDI P0J5010
P0U1802
N0CABLE0TDO P0J508
P0U1704
N0CABLE0TMS P0J504
P0U1502
N0FPGA0DONE P0Q101
P0R2802
P0U100T15
P0FPGA0DONE
N0FPGA0PROG P0U904 P0U100A2
N0FPGA0SUSPEND
P0JP502
P0U100R16
P0J501
P0J503
P0J505
P0J507
P0J509
P0J5011
P0J5013
P0Q102
P0R5502
P0U903
P0U1503
P0U1603
P0U1703
P0U1803
P0U1501
P0U1601
P0U1701
P0U1801
P0JTAG0MUX0CTL
N0JTAG0TCK
P0R3801
P0RP406
P0U100A15
P0JTAG0TCK
N0JTAG0TDI P0RP407
P0U100B1
P0U1804
P0JTAG0TDI
N0JTAG0TDO
P0U100B16
P0U1702 P0JTAG0TDO
N0JTAG0TMS P0RP405
P0U100B2
P0U1504
P0JTAG0TMS
P0D701
P0Q103
P0D702
P0R502
P0J5012
P0J5014
P0JP501 P0R5402
P0JP503
P0R5501
P0R3802 P0U1604
P0R4301
P0U1602
P0RP408
P0U100D6
P0U100D12
P0U100E4
P0U100E6
P0U100E9
P0U100F4
P0U100F7
P0U100F9
P0U100F10
P0U100F11
P0U100F12
P0U100G5
P0U100G6
P0U100G11
P0U100G12
P0U100H7
P0U100H10
P0U100H11
P0U100J7
P0U100J10
P0U100J11
P0U100K5
P0U100K6
P0U100K11
P0U100K12
P0U100L5
P0U100L6
P0U100L7
P0U100L8
P0U100L9
P0U100L10
P0U100M7
P0U100M8
P0U100M11
P0U100N5
P0U901
P0PO0RESET#
P0R5802
P0U902
P0PSOC0FPGA0PROG
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 7 - FPGA PowerSize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 7 12
VCCO_0B5
VCCO_0B9
VCCO_0B13
VCCO_0E8
VCCO_1E15
VCCO_1H12
VCCO_1J15
VCCO_1N15
VCCO_2M9
VCCO_2R4
VCCO_2R8
VCCO_2R12
VCCO_3D2
VCCO_3H2
VCCO_3J5
VCCO_3M2
VCCAUX E11
VCCAUX F5
VCCAUX L12
VCCAUX M6
VCCINT G7
VCCINT G9
VCCINT H8
VCCINT J9
VCCINT K8
VCCINT K10
U10G
XC3S400A-1FTG256C
GNDA1
GNDA16
GNDB7
GNDB11
GNDC3
GNDC14
GNDE5
GNDE12
GNDF2
GNDF6
GNDG8
GNDG10
GNDG15
GNDH9 GND J8GND K2GND K7GND K9GND L11GND L15GND M5GND M12GND P3GND P14GND R6GND R10GND T1GND T16U10H
XC3S400A-1FTG256C
+1.2V
+3.3V
GND GND
+
12
C23TAND 470uFC19
4.7uF 0603
+
12
C13TAND 470uF C30
4.7uF 0603C500.01uF 0201
C390.01uF 0201
C440.01uF 0201
C430.01uF 0201
GND
GND
C114.7uF 0603
C414.7uF 0603
GND
C34
0.01uF 0201
C36
0.01uF 0201
C32
0.01uF 0201
C33
0.01uF 0201
C37
0.01uF 0201
C420.01uF 0201
C350.01uF 0201
C550.01uF 0201
C560.01uF 0201
C570.01uF 0201
C480.01uF 0201
GND
+3.3V
C151.0uF 0402
C141.0uF 0402C17
1.0uF 0402C18
1.0uF 0402C20
1.0uF 0402
C451.0uF 0402
C311.0uF 0402
C491.0uF 0402
P0C1101
P0C1102
P0C1301
P0C1302
P0C1401
P0C1402
P0C1501
P0C1502 P0C1701
P0C1702
P0C1801
P0C1802
P0C1901
P0C1902
P0C2001
P0C2002
P0C2301
P0C2302
P0C3001
P0C3002
P0C3101
P0C3102
P0C3201
P0C3202
P0C3301
P0C3302
P0C3401
P0C3402
P0C3501 P0C3502
P0C3601
P0C3602
P0C3701
P0C3702
P0C3901
P0C3902
P0C4101
P0C4102
P0C4201 P0C4202
P0C4301
P0C4302
P0C4401
P0C4402
P0C4501
P0C4502
P0C4801 P0C4802
P0C4901
P0C4902
P0C5001
P0C5002
P0C5501 P0C5502
P0C5601 P0C5602
P0C5701 P0C5702
P0U100B5
P0U100B9
P0U100B13
P0U100D2
P0U100E8
P0U100E11
P0U100E15
P0U100F5
P0U100G7
P0U100G9
P0U100H2
P0U100H8
P0U100H12
P0U100J5
P0U100J9
P0U100J15
P0U100K8
P0U100K10
P0U100L12
P0U100M2
P0U100M6
P0U100M9
P0U100N15
P0U100R4
P0U100R8
P0U100R12
P0U100A1
P0U100A16
P0U100B7
P0U100B11
P0U100C3
P0U100C14
P0U100E5
P0U100E12
P0U100F2
P0U100F6
P0U100G8
P0U100G10
P0U100G15
P0U100H9 P0U100J8
P0U100K2
P0U100K7
P0U100K9
P0U100L11
P0U100L15
P0U100M5
P0U100M12
P0U100P3
P0U100P14
P0U100R6
P0U100R10
P0U100T1
P0U100T16
P0C1301
P0C3001
P0C3101
P0C3901
P0C4301
P0C4401
P0C4501
P0C5001
P0U100G7
P0U100G9
P0U100H8
P0U100J9
P0U100K8
P0U100K10
P0C1101
P0C1401
P0C1501
P0C1701
P0C1801
P0C1901
P0C2001
P0C2301
P0C3201
P0C3301
P0C3401
P0C3501
P0C3601
P0C3701
P0C4101
P0C4201
P0C4801
P0C4901
P0C5501
P0C5601
P0C5701
P0U100B5
P0U100B9
P0U100B13
P0U100D2
P0U100E8
P0U100E11
P0U100E15
P0U100F5
P0U100H2
P0U100H12
P0U100J5
P0U100J15
P0U100L12
P0U100M2
P0U100M6
P0U100M9
P0U100N15
P0U100R4
P0U100R8
P0U100R12
P0C1102
P0C1302
P0C1402
P0C1502
P0C1702
P0C1802
P0C1902
P0C2002
P0C2302
P0C3002
P0C3102
P0C3202
P0C3302
P0C3402
P0C3502
P0C3602
P0C3702
P0C3902
P0C4102
P0C4202
P0C4302
P0C4402
P0C4502
P0C4802
P0C4902
P0C5002
P0C5502
P0C5602
P0C5702
P0U100A1
P0U100A16
P0U100B7
P0U100B11
P0U100C3
P0U100C14
P0U100E5
P0U100E12
P0U100F2
P0U100F6
P0U100G8
P0U100G10
P0U100G15
P0U100H9 P0U100J8
P0U100K2
P0U100K7
P0U100K9
P0U100L11
P0U100L15
P0U100M5
P0U100M12
P0U100P3
P0U100P14
P0U100R6
P0U100R10
P0U100T1
P0U100T16
P0C1101
P0C1102
P0C1301
P0C1302
P0C1401
P0C1402
P0C1501
P0C1502 P0C1701
P0C1702
P0C1801
P0C1802
P0C1901
P0C1902
P0C2001
P0C2002
P0C2301
P0C2302
P0C3001
P0C3002
P0C3101
P0C3102
P0C3201
P0C3202
P0C3301
P0C3302
P0C3401
P0C3402
P0C3501 P0C3502
P0C3601
P0C3602
P0C3701
P0C3702
P0C3901
P0C3902
P0C4101
P0C4102
P0C4201 P0C4202
P0C4301
P0C4302
P0C4401
P0C4402
P0C4501
P0C4502
P0C4801 P0C4802
P0C4901
P0C4902
P0C5001
P0C5002
P0C5501 P0C5502
P0C5601 P0C5602
P0C5701 P0C5702
P0U100B5
P0U100B9
P0U100B13
P0U100D2
P0U100E8
P0U100E11
P0U100E15
P0U100F5
P0U100G7
P0U100G9
P0U100H2
P0U100H8
P0U100H12
P0U100J5
P0U100J9
P0U100J15
P0U100K8
P0U100K10
P0U100L12
P0U100M2
P0U100M6
P0U100M9
P0U100N15
P0U100R4
P0U100R8
P0U100R12
P0U100A1
P0U100A16
P0U100B7
P0U100B11
P0U100C3
P0U100C14
P0U100E5
P0U100E12
P0U100F2
P0U100F6
P0U100G8
P0U100G10
P0U100G15
P0U100H9 P0U100J8
P0U100K2
P0U100K7
P0U100K9
P0U100L11
P0U100L15
P0U100M5
P0U100M12
P0U100P3
P0U100P14
P0U100R6
P0U100R10
P0U100T1
P0U100T16
P0C1301
P0C3001
P0C3101
P0C3901
P0C4301
P0C4401
P0C4501
P0C5001
P0U100G7
P0U100G9
P0U100H8
P0U100J9
P0U100K8
P0U100K10
P0C1101
P0C1401
P0C1501
P0C1701
P0C1801
P0C1901
P0C2001
P0C2301
P0C3201
P0C3301
P0C3401
P0C3501
P0C3601
P0C3701
P0C4101
P0C4201
P0C4801
P0C4901
P0C5501
P0C5601
P0C5701
P0U100B5
P0U100B9
P0U100B13
P0U100D2
P0U100E8
P0U100E11
P0U100E15
P0U100F5
P0U100H2
P0U100H12
P0U100J5
P0U100J15
P0U100L12
P0U100M2
P0U100M6
P0U100M9
P0U100N15
P0U100R4
P0U100R8
P0U100R12
P0C1102
P0C1302
P0C1402
P0C1502
P0C1702
P0C1802
P0C1902
P0C2002
P0C2302
P0C3002
P0C3102
P0C3202
P0C3302
P0C3402
P0C3502
P0C3602
P0C3702
P0C3902
P0C4102
P0C4202
P0C4302
P0C4402
P0C4502
P0C4802
P0C4902
P0C5002
P0C5502
P0C5602
P0C5702
P0U100A1
P0U100A16
P0U100B7
P0U100B11
P0U100C3
P0U100C14
P0U100E5
P0U100E12
P0U100F2
P0U100F6
P0U100G8
P0U100G10
P0U100G15
P0U100H9 P0U100J8
P0U100K2
P0U100K7
P0U100K9
P0U100L11
P0U100L15
P0U100M5
P0U100M12
P0U100P3
P0U100P14
P0U100R6
P0U100R10
P0U100T1
P0U100T16
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 8 - PsOC ProcessorSize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 8 12
C590.1uF 0402
C600.1uF 0402
C510.1uF 0402
C540.1uF 0402
GND
+3.3V
GND
C470.1uF 0402
C380.1uF 0402
+3.3V
GND
P2[3] 1
P2[1] 2
P4[7]3
P4[5]4
P4[3]5
P4[1]6
P3[7]7
P3[5]8
P3[3]9
P3[1]10
P5[7]11
P5[5]12
P5[3]13
P5[1]14
P1[7]/SCL 15
P1[5]/SDA 16
P1[3] 17
P1[1] 18
VSS
19
USB D+ 20
USB D- 21
VD
D22
P7[7]23
P7[0]24
P1[0] 25
P1[2] 26
P1[4] 27
P1[6] 28
P5[0]29
P5[2]30
P5[4]31
P5[6]32
P3[0]33
P3[2]34
P3[4]35
P3[6]/XRES36
P4[0]37
P4[2]38
P4[4]39
P4[6]40
P2[0] 41
P2[2] 42
P2[4] 43
P2[6] 44
P0[0] 45
P0[2] 46
P0[4] 47
P0[6] 48
VD
D49
VSS
50
P0[7] 51
P0[5] 52
P0[3] 53
P0[1] 54
P2[7] 55
P2[5] 56
PAD
57
U12
CY8C24894-QFN56
+3.3V
GND
R22
24R3 0402
R23
24R3 0402
UART_RXD
UART_TXDPSOC_SPI_MODE
PSOC_MISO
PSOC_MOSI
SPI_CLK
FPGA_DONE
PSOC_FPGA_PROG
PSOC_FPGA_M0
PSOC_FPGA_M1
PSOC_FPGA_M2
PSOC_P7_7PSOC_P7_0
ISSP_SCLK
ISSP_SCLKISSP_DATA
ISSP_DATA
FPGA_INIT_B
PSOC_SPI_SEL#12EF4 RESET
12EF3 PUSH_C
12EF2 PUSH_B
12EF1 PUSH_A
C53 3900pF 0603
R56 5K11 0402 CSENSE_R
CSENSE_R
FPGA_RESET
FPGA_PUSH A
FPGA_PUSH BCLK_12MHZ
PSOC_P2_1
PSOC_P2_5
PSOC_P2_3
PSOC_P2_7CLK_32KHZ
PSOC_P4_6
FPGA_PUSH_C
PSOC_P5_3PSOC_P5_4
PSOC_P5_6
R25
4K75 0402
+3.3V
PSOC_P5_7
123
J9
HEA
DER
3PSOC_P0_1PSOC_P0_3PSOC_P0_5
VBUS1
D-2
D+3
ID4
GND5
SHIELD16
SHIELD27
SHIELD38
SHIELD49
P1
USB Min-AB
+5V_USB
C270.1uF 0402
C284.7uF 0603
GND
FB1
120, 3A, 1206
R2
10R0 2512
GND EARTHPSOC_P7_0PSOC_P7_7
FPGA_PUSH_C
PSOC_P5_3PSOC_P5_4
PSOC_P5_6PSOC_P5_7
PSOC_P4_6
UART_TXD
UART_RXD
PSOC_FPGA_M0
PSOC_FPGA_M1
PSOC_FPGA_M2
PSOC_FPGA_PROG
CLK_32KHZ
FPGA_PUSH A
FPGA_PUSH B
FPGA_DONEFPGA_RESETFPGA_INIT_B
CAPSENSE1
CAPSENSE2
CAPSENSE3
CAPSENSE4
PSOC_MOSI
2 45
1
3
U8
NC7SV125
245
1
3
U7
NC7SV125
2 45
1
3
U11
NC7SV125
2 45
1
3
U13
NC7SV125
GND
GND
GND
+3.3V
1 82 73 64 5
RP3
4K7
+3.3V
+3.3V
C400.1uF 0402
C460.1uF 0402
C520.1uF 0402
C580.1uF 0402
+3.3V
GND
TCK
JTAG_TCK
TMS
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_MUX_CTL
PSOC_P0_4
PSOC_SPI_MODE
PSOC_P2_7
PSOC_P2_5
PSOC_P2_3
CLK_12MHZ
PSOC_MISO
PSOC_P2_1SPI_CLK
JTAG_MUX_CTL
PSOC_P0_1
PSOC_P0_3
PSOC_P0_5
IIC_SCL
IIC_SDA
PSOC_P0_4
R39
4K75 0402
+3.3V
TDITDO
R31
33R2 0402
R29
33R2 0402
IIC_SCL
IIC_SDA
TMSTDITCK
PSOC_SPI_SEL#
+5V_Prog
12345
J2
ISSP
Soc
ket-5
R5910K0 0402
+3.3V
P0C2701
P0C2702
P0C2801
P0C2802
P0C3801
P0C3802
P0C4001
P0C4002
P0C4601
P0C4602
P0C4701
P0C4702
P0C5101
P0C5102
P0C5201
P0C5202
P0C5301 P0C5302
P0C5401
P0C5402
P0C5801
P0C5802
P0C5901
P0C5902
P0C6001
P0C6002
P0EF101
P0EF102
P0EF201
P0EF202
P0EF301
P0EF302
P0EF401
P0EF402
P0FB101 P0FB102
P0J201
P0J202
P0J203
P0J204
P0J205
P0J901
P0J902
P0J903
P0P101
P0P102
P0P103
P0P104
P0P105
P0P106
P0P107
P0P108
P0P109
P0R201 P0R202
P0R2201 P0R2202
P0R2301 P0R2302
P0R2501 P0R2502
P0R2901 P0R2902
P0R3101 P0R3102
P0R3901 P0R3902
P0R5601 P0R5602 P0R5901
P0R5902
P0RP301
P0RP302
P0RP303
P0RP304 P0RP305
P0RP306
P0RP307
P0RP308
P0U701
P0U702
P0U703
P0U704
P0U705
P0U801
P0U802
P0U803
P0U804
P0U805
P0U1101
P0U1102
P0U1103
P0U1104
P0U1105
P0U1201
P0U1202
P0U1203
P0U1204
P0U1205
P0U1206
P0U1207
P0U1208
P0U1209
P0U12010
P0U12011
P0U12012
P0U12013
P0U12014
P0U12015
P0U12016
P0U12017
P0U12018
P0U12019
P0U12020
P0U12021
P0U12022
P0U12023
P0U12024
P0U12025
P0U12026
P0U12027
P0U12028
P0U12029
P0U12030
P0U12031
P0U12032
P0U12033
P0U12034
P0U12035
P0U12036
P0U12037
P0U12038
P0U12039
P0U12040
P0U12041
P0U12042
P0U12043
P0U12044
P0U12045
P0U12046
P0U12047
P0U12048
P0U12049
P0U12050
P0U12051
P0U12052
P0U12053
P0U12054
P0U12055
P0U12056
P0U12057
P0U1301
P0U1302
P0U1303
P0U1304
P0U1305
P0C3801
P0C4001
P0C4601
P0C4701
P0C5101
P0C5201
P0C5401
P0C5801
P0C5901
P0C6001
P0R2501
P0R3901
P0R5901
P0RP301
P0RP302
P0RP303
P0RP304
P0U705
P0U805
P0U1105
P0U12022
P0U12049
P0U1305
P0J201
P0C2701
P0C2801 P0FB101
P0EF401
P0U1203 N0CAPSENSE1
P0EF301
P0U1204 N0CAPSENSE2
P0EF201
P0U1205 N0CAPSENSE3
P0EF101
P0U1206 N0CAPSENSE4
P0U12044 N0CLK012MHZ
P0CLK012MHZ
P0U1207 N0CLK032KHZ P0CLK032KHZ
P0R5602
P0U12012 N0CSENSE0R
N0CSENSE0R
P0P106
P0P107
P0P108
P0P109
P0R202
P0U12034 N0FPGA0DONE
P0FPGA0DONE
P0R2502
P0U12033 N0FPGA0INIT0B
P0FPGA0INIT0B
P0U1209 N0FPGA0PUSH A
P0FPGA0PUSH A
P0U1208 N0FPGA0PUSH B P0FPGA0PUSH B
P0U12014 N0FPGA0PUSH0C
P0FPGA0PUSH0C
P0U12010 N0FPGA0RESET
P0FPGA0RESET
P0C2702
P0C2802
P0C3802
P0C4002
P0C4602
P0C4702
P0C5102
P0C5202
P0C5302
P0C5402
P0C5802
P0C5902
P0C6002
P0J202
P0P105
P0R201
P0U703
P0U803
P0U1103
P0U12019
P0U12050
P0U12057
P0U1303
P0U12015 N0IIC0SCL P0IIC0SCL
P0U12016 N0IIC0SDA
P0IIC0SDA
P0J205
P0U12025
N0ISSP0DATA
N0ISSP0DATA
P0J204
P0U12018
N0ISSP0SCLK
N0ISSP0SCLK
P0R3902
P0U701
P0U801
P0U1101
P0U12048
P0U1301
N0JTAG0MUX0CTL
P0JTAG0MUX0CTL
P0R2902 P0JTAG0TCK
P0U1104
P0JTAG0TDI
P0U702
P0JTAG0TDO
P0U804
P0JTAG0TMS
P0C5301
P0R5601
P0U12051
P0EF102
P0EF202
P0EF302
P0EF402
P0FB102 P0P101
P0J203
P0U12036
P0P102
P0R2202
P0P103
P0R2302
P0P104
P0R2201
P0U12021
P0R2301
P0U12020
P0R2901
P0U1304
P0R3101
P0U12026
P0RP308
P0U12037 N0PSOC0FPGA0M0 P0PSOC0FPGA0M0
P0U12038 N0PSOC0FPGA0M1
P0PSOC0FPGA0M1
P0U12039 N0PSOC0FPGA0M2
P0PSOC0FPGA0M2
P0U12035 N0PSOC0FPGA0PROG
P0PSOC0FPGA0PROG
P0U12043 N0PSOC0MISO
P0PSOC0MISO
P0U12042 N0PSOC0MOSI
P0PSOC0MOSI
P0J903
P0U12054
N0PSOC0P001
N0PSOC0P001
P0J902
P0U12053
N0PSOC0P003
N0PSOC0P003
P0U12047 N0PSOC0P004
P0PSOC0P004
P0J901
P0U12052
N0PSOC0P005
N0PSOC0P005
P0U1202 N0PSOC0P201
P0PSOC0P201
P0U1201 N0PSOC0P203
P0PSOC0P203
P0U12056 N0PSOC0P205 P0PSOC0P205
P0U12055 N0PSOC0P207 P0PSOC0P207
P0U12040 N0PSOC0P406
P0PSOC0P406
P0U12013 N0PSOC0P503
P0PSOC0P503
P0U12031 N0PSOC0P504
P0PSOC0P504
P0U12032 N0PSOC0P506
P0PSOC0P506
P0U12011 N0PSOC0P507
P0PSOC0P507
P0U12024 N0PSOC0P700 P0PSOC0P700
P0U12023 N0PSOC0P707
P0PSOC0P707
P0U12046 N0PSOC0SPI0MODE
P0PSOC0SPI0MODE P0U12045 N0PSOC0SPI0SEL#
P0PSOC0SPI0SEL#
P0U12041 N0SPI0CLK
P0SPI0CLK
P0R3102
P0RP307
P0U1302
N0TCK
N0TCK
P0RP306
P0U1102
P0U12027 N0TDI
N0TDI
P0U704
P0U12017 N0TDO
P0RP305
P0U802
P0U12028 N0TMS
N0TMS
P0R5902
P0U12030 N0UART0RXD P0UART0RXD
P0U12029 N0UART0TXD P0UART0TXD
P0SPI0CLK
P0PSOC0SPI0SEL#
P0PSOC0SPI0MODE
P0PSOC0MOSI
P0PSOC0MISO
P0CLK012MHZ
P0CLK032KHZ
P0FPGA0DONE
P0FPGA0INIT0B
P0FPGA0PUSH0C
P0FPGA0PUSH A
P0FPGA0PUSH B
P0FPGA0RESET
P0JTAG0MUX0CTL
P0JTAG0TCK
P0JTAG0TDI
P0JTAG0TDO
P0JTAG0TMS
P0PSOC0FPGA0M0
P0PSOC0FPGA0M1
P0PSOC0FPGA0M2
P0PSOC0FPGA0PROG
P0PSOC0P004
P0PSOC0P201
P0PSOC0P203
P0PSOC0P205
P0PSOC0P207
P0PSOC0P406
P0PSOC0P503
P0PSOC0P504
P0PSOC0P506
P0PSOC0P507
P0PSOC0P700
P0PSOC0P707
P0UART0RXD
P0UART0TXD
P0IIC0SDA
P0IIC0SCL
P0C2701
P0C2702
P0C2801
P0C2802
P0C3801
P0C3802
P0C4001
P0C4002
P0C4601
P0C4602
P0C4701
P0C4702
P0C5101
P0C5102
P0C5201
P0C5202
P0C5301 P0C5302
P0C5401
P0C5402
P0C5801
P0C5802
P0C5901
P0C5902
P0C6001
P0C6002
P0EF101
P0EF102
P0EF201
P0EF202
P0EF301
P0EF302
P0EF401
P0EF402
P0FB101 P0FB102
P0J201
P0J202
P0J203
P0J204
P0J205
P0J901
P0J902
P0J903
P0P101
P0P102
P0P103
P0P104
P0P105
P0P106
P0P107
P0P108
P0P109
P0R201 P0R202
P0R2201 P0R2202
P0R2301 P0R2302
P0R2501 P0R2502
P0R2901 P0R2902
P0R3101 P0R3102
P0R3901 P0R3902
P0R5601 P0R5602 P0R5901
P0R5902
P0RP301
P0RP302
P0RP303
P0RP304 P0RP305
P0RP306
P0RP307
P0RP308
P0U701
P0U702
P0U703
P0U704
P0U705
P0U801
P0U802
P0U803
P0U804
P0U805
P0U1101
P0U1102
P0U1103
P0U1104
P0U1105
P0U1201
P0U1202
P0U1203
P0U1204
P0U1205
P0U1206
P0U1207
P0U1208
P0U1209
P0U12010
P0U12011
P0U12012
P0U12013
P0U12014
P0U12015
P0U12016
P0U12017
P0U12018
P0U12019
P0U12020
P0U12021
P0U12022
P0U12023
P0U12024
P0U12025
P0U12026
P0U12027
P0U12028
P0U12029
P0U12030
P0U12031
P0U12032
P0U12033
P0U12034
P0U12035
P0U12036
P0U12037
P0U12038
P0U12039
P0U12040
P0U12041
P0U12042
P0U12043
P0U12044
P0U12045
P0U12046
P0U12047
P0U12048
P0U12049
P0U12050
P0U12051
P0U12052
P0U12053
P0U12054
P0U12055
P0U12056
P0U12057
P0U1301
P0U1302
P0U1303
P0U1304
P0U1305
P0C3801
P0C4001
P0C4601
P0C4701
P0C5101
P0C5201
P0C5401
P0C5801
P0C5901
P0C6001
P0R2501
P0R3901
P0R5901
P0RP301
P0RP302
P0RP303
P0RP304
P0U705
P0U805
P0U1105
P0U12022
P0U12049
P0U1305
P0J201
P0C2701
P0C2801 P0FB101
N0CAPSENSE1
P0EF401
P0U1203
N0CAPSENSE2
P0EF301
P0U1204
N0CAPSENSE3
P0EF201
P0U1205
N0CAPSENSE4
P0EF101
P0U1206
P0U12044
P0U1207
N0CSENSE0R
P0R5602
P0U12012
P0P106
P0P107
P0P108
P0P109
P0R202
P0U12034
P0R2502
P0U12033
P0U1209
P0U1208
P0U12014
P0U12010
P0C2702
P0C2802
P0C3802
P0C4002
P0C4602
P0C4702
P0C5102
P0C5202
P0C5302
P0C5402
P0C5802
P0C5902
P0C6002
P0J202
P0P105
P0R201
P0U703
P0U803
P0U1103
P0U12019
P0U12050
P0U12057
P0U1303
P0U12015
P0U12016
N0ISSP0DATA P0J205
P0U12025
N0ISSP0SCLK P0J204
P0U12018
N0JTAG0MUX0CTL
P0R3902
P0U701
P0U801
P0U1101
P0U12048
P0U1301
P0R2902
P0U1104
P0U702
P0U804
P0C5301
P0R5601
P0U12051
P0EF102
P0EF202
P0EF302
P0EF402
P0FB102 P0P101
P0J203
P0U12036
P0P102
P0R2202
P0P103
P0R2302
P0P104
P0R2201
P0U12021
P0R2301
P0U12020
P0R2901
P0U1304
P0R3101
P0U12026
P0RP308
P0U12037
P0U12038
P0U12039
N0PSOC0FPGA0PROG P0U12035 N0PSOC0MISO P0U12043
P0PSOC0MISO
N0PSOC0MOSI P0U12042
P0PSOC0MOSI
N0PSOC0P001 P0J903
P0U12054
N0PSOC0P003
P0J902
P0U12053
P0U12047
N0PSOC0P005 P0J901
P0U12052
P0U1202
P0U1201
P0U12056
P0U12055
P0U12040
P0U12013
P0U12031
P0U12032
P0U12011
P0U12024
P0U12023
N0PSOC0SPI0MODE P0U12046
P0PSOC0SPI0MODE
N0PSOC0SPI0SEL# P0U12045
P0PSOC0SPI0SEL#
P0U12041
N0TCK
P0R3102
P0RP307
P0U1302
N0TDI
P0RP306
P0U1102
P0U12027
N0TDO
P0U704
P0U12017
N0TMS
P0RP305
P0U802
P0U12028
P0R5902
P0U12030
P0U12029
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 9 - MemorySize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 9 12
C60.1uF 0402
C40.1uF 0402
C30.1uF 0402
GND
+3.3V
R45
10K0 0402+3.3V
+3.3V
GND
R30
10K0 0402
SF_HOLD#SF_W#
C240.1uF 0402
n/c 1
n/c 2
A153 A144 A135 A126 A117 A108 A99 A810
A1911
A2012
WE#13
RESET#14
n/c 15
WP#/ACC 16
RY/BY#17
A1818 A1719
A720 A621 A522 A423 A324 A225 A126
n/c 27
n/c 28
VIO 29
n/c 30
A031
CE#32
VSS 33
OE#34
DQ0 35
DQ8 36
DQ1 37
DQ9 38
DQ2 39
DQ10 40
DQ3 41
DQ11 42
VCC 43
DQ4 44
DQ12 45
DQ5 46
DQ13 47
DQ6 48
DQ14 49
DQ7 50
DQ15 51
VSS 52
BYTE#53
A1654
n/c 55n/c 56
U22
S29GL032N
FLASH_CE#
FLASH_WE#FLASH_OE#
FLASH_RESET#
FLASH_RY/BY#
R51
10K0 0402
+3.3V
FLASH_A1FLASH_A2FLASH_A3FLASH_A4FLASH_A5FLASH_A6FLASH_A7FLASH_A8FLASH_A9FLASH_A10FLASH_A11FLASH_A12FLASH_A13FLASH_A14FLASH_A15FLASH_A16FLASH_A17FLASH_A18FLASH_A19FLASH_A20FLASH_A21
Flash_D[7..0]
+3.3V
FLASH_D0FLASH_D1FLASH_D2FLASH_D3FLASH_D4FLASH_D5FLASH_D6FLASH_D7
12
JP1
HEADER 2/THR4
10K0 0402
GND
Flash_D[7..0]
FLASH_A0
FLASH_A0
Flash_A[21..0]Flash_A[21..0]
GND
Flash_D[14..8]Flash_D[14..8]
FLASH_D8FLASH_D9FLASH_D10FLASH_D11FLASH_D12FLASH_D13FLASH_D14
FLASH_BYTE#
R16
10K0 0402GND
GND
+3.3V
123456
J8
HEA
DER
6_T
H
SPI_FLASH_SI
SPI_CLKSPI_FLASH_SO
+3.3V
GND
R44
10K0 0402
GND
R50
10K0 0402
Note: This footprint accomodates the future Spansion quad-bit SPI Flash. If that is used, SPI_MOSI is IO0, Flash_D0 is IO1, SPI_W# is IO2, and SPI_HOLD# is IO3. It also accomodates the the SOC008 package where Pin #1 of that package would mate with Pin #3 of the 16-pin footprint.
SPI_FLASH_SO
SPI_FLASH_SISPI_CLK
1
24
53
U4
NC7SV08
PO_RESET#
R5310K0 0402
+3.3V
GND
PSOC_SPI_SEL#
SF_HOLD#SF_W#
PSOC_MOSI
JP1 default setting = Open (no write protect)
SF_SEL#
Note: DQ15 becomes the LSB address input in Byte mode
SF_W#
SF_HOLD#
SF_SEL#SPI_CLK SPI_CLK
S1
1B1 2
1B2 3
1A4
2B1 5
2B2 6
2A7
GND8
3A9
3B2 10
3B1 114A12
4B2 13
4B1 14
OE15
VCC 16U20
SN74CB3T3257PW
1
24
53
U21
NC7SV08
2 4
5
3
U14
NC7SV04
SPI_FLASH_SISPI_FLASH_SO
R3749R9 0402
R3649R9 0402
PSOC_SPI_MODE
PSOC_MISO
FPGA_MOSI
FPGA_MISO
+3.3V
+3.3V
GND
GND
FLASH_CE#
FLASH_CE#
R52
10K0 0402
+3.3V
FPGA_SPI_SEL#
PSOC_SPI_SEL#1 2
JP6
PSOC_SPI_SEL#
R46
10K0 0402
R57
10K0 0402
+3.3V
+3.3V
GND
JP6 default = jumpered. Disconnect JP6 jumper to provide off-board SPI via J8
C620.1uF 0402
C210.1uF 0402
C610.1uF 0402
C220.1uF 0402
GND
GND
+3.3V
R47
10K0 0402
R42
10K0 0402
PsOC_SPI_MODE = 0 (default condition) , FPGA_SPI_SEL# or PsOC_SPI_SEL# = 0 (with JP6 jumpered): FPGA_MOSI or PsOC_MOSI to SPI_FLASH_SI SPI_FLASH_SO to FPGA_MISO and PsOC_MISO Flash_CE# must be high in order to enable the Mux (U14)
PsOC_SPI_MODE = 1: FPGA_MOSI to PsOC_MISO PsOC_MOSI to FPGA_MISO
PsOC/FPGA SPI interfaces are isolated through 100-ohm current-limiting resistors (2x 49.9-ohm each line).
Note that access to the parallel flash will cause the Mux (U20) to be disabled
HOLD#1
VCC 2
n/c 3
n/c 4
n/c 5
n/c 6
CS#7
SO8
W#9
GND 10
n/c 11
n/c 12
n/c 13
n/c 14
SI15 SCK16
U19
S25FL128P
P0C301
P0C302
P0C401
P0C402
P0C601
P0C602
P0C2101
P0C2102
P0C2201
P0C2202
P0C2401
P0C2402
P0C6101
P0C6102
P0C6201
P0C6202
P0J801
P0J802
P0J803
P0J804
P0J805
P0J806
P0JP101
P0JP102
P0JP601
P0JP602
P0R401 P0R402
P0R1601 P0R1602
P0R3001 P0R3002
P0R3601
P0R3602
P0R3701
P0R3702
P0R4201 P0R4202
P0R4401 P0R4402
P0R4501 P0R4502
P0R4601 P0R4602
P0R4701 P0R4702
P0R5001 P0R5002
P0R5101 P0R5102
P0R5201 P0R5202
P0R5301
P0R5302
P0R5701 P0R5702
P0U401
P0U402
P0U403
P0U404
P0U405
P0U1402
P0U1403
P0U1404
P0U1405
P0U1901
P0U1902
P0U1903
P0U1904
P0U1905
P0U1906
P0U1907
P0U1908
P0U1909
P0U19010
P0U19011
P0U19012
P0U19013
P0U19014
P0U19015
P0U19016
P0U2001
P0U2002
P0U2003
P0U2004
P0U2005
P0U2006
P0U2007
P0U2008
P0U2009
P0U20010
P0U20011 P0U20012
P0U20013
P0U20014
P0U20015
P0U20016
P0U2101
P0U2102
P0U2103
P0U2104
P0U2105
P0U2201
P0U2202
P0U2203
P0U2204
P0U2205
P0U2206
P0U2207
P0U2208
P0U2209
P0U22010
P0U22011
P0U22012
P0U22013
P0U22014
P0U22015
P0U22016
P0U22017
P0U22018
P0U22019
P0U22020
P0U22021
P0U22022
P0U22023
P0U22024
P0U22025
P0U22026
P0U22027
P0U22028
P0U22029
P0U22030
P0U22031
P0U22032
P0U22033
P0U22034
P0U22035
P0U22036
P0U22037
P0U22038
P0U22039
P0U22040
P0U22041
P0U22042
P0U22043
P0U22044
P0U22045
P0U22046
P0U22047
P0U22048
P0U22049
P0U22050
P0U22051
P0U22052
P0U22053
P0U22054
P0U22055
P0U22056
P0C301
P0C401
P0C601
P0C2101
P0C2201
P0C2401
P0C6101
P0C6201
P0J806
P0R402
P0R3001
P0R4501
P0R4602
P0R4701
P0R5002
P0R5101
P0R5202
P0R5301
P0R5702
P0U405
P0U1405
P0U1902
P0U19014
P0U20016
P0U2105
P0U22029
P0U22043
N0FLASH0A0210000
P0FLASH0A0210000
P0U22051
N0FLASH0A0
N0FLASH0A0
N0FLASH0A0
P0FLASH0A0
P0U22031
N0FLASH0A1
N0FLASH0A1
P0FLASH0A1
P0U22026
N0FLASH0A2
N0FLASH0A2
P0FLASH0A2
P0U22025
N0FLASH0A3
N0FLASH0A3
P0FLASH0A3
P0U22024
N0FLASH0A4
N0FLASH0A4
P0FLASH0A4
P0U22023
N0FLASH0A5
N0FLASH0A5
P0FLASH0A5
P0U22022
N0FLASH0A6
N0FLASH0A6
P0FLASH0A6
P0U22021
N0FLASH0A7
N0FLASH0A7
P0FLASH0A7
P0U22020
N0FLASH0A8
N0FLASH0A8
P0FLASH0A8
P0U22010
N0FLASH0A9
N0FLASH0A9
P0FLASH0A9
P0U2209
N0FLASH0A10
N0FLASH0A10
P0FLASH0A10
P0U2208
N0FLASH0A11
N0FLASH0A11
P0FLASH0A11
P0U2207
N0FLASH0A12
N0FLASH0A12
P0FLASH0A12
P0U2206
N0FLASH0A13
N0FLASH0A13
P0FLASH0A13
P0U2205
N0FLASH0A14
N0FLASH0A14
P0FLASH0A14
P0U2204
N0FLASH0A15
N0FLASH0A15
P0FLASH0A15
P0U2203
N0FLASH0A16
N0FLASH0A16
P0FLASH0A16
P0U22054
N0FLASH0A17
N0FLASH0A17
P0FLASH0A17
P0U22019
N0FLASH0A18
N0FLASH0A18
P0FLASH0A18
P0U22018
N0FLASH0A19
N0FLASH0A19
P0FLASH0A19
P0U22011
N0FLASH0A20
N0FLASH0A20
P0FLASH0A20
P0U22012
N0FLASH0A21
N0FLASH0A21
P0FLASH0A21
P0R1602
P0U22053 P0FLASH0BYTE#
P0R5001
P0U1402
P0U22032
N0FLASH0CE#
N0FLASH0CE#
P0FLASH0CE#
P0U22035
N0FLASH0D0
N0FLASH0D0
P0FLASH0D0
P0U22037
N0FLASH0D1
N0FLASH0D1
P0FLASH0D1
P0U22039
N0FLASH0D2
N0FLASH0D2
P0FLASH0D2
P0U22041
N0FLASH0D3
N0FLASH0D3
P0FLASH0D3
P0U22044
N0FLASH0D4
N0FLASH0D4
P0FLASH0D4
P0U22046
N0FLASH0D5
N0FLASH0D5
P0FLASH0D5
P0U22048
N0FLASH0D6
N0FLASH0D6
P0FLASH0D6
P0U22050
N0FLASH0D7
N0FLASH0D7
P0FLASH0D7
P0U22036
N0FLASH0D8
N0FLASH0D8
P0FLASH0D8
P0U22038
N0FLASH0D9
N0FLASH0D9
P0FLASH0D9
P0U22040
N0FLASH0D10
N0FLASH0D10
P0FLASH0D10
P0U22042
N0FLASH0D11
N0FLASH0D11
P0FLASH0D11
P0U22045
N0FLASH0D12
N0FLASH0D12
P0FLASH0D12
P0U22047
N0FLASH0D13
N0FLASH0D13
P0FLASH0D13
P0U22049
N0FLASH0D14
N0FLASH0D14
P0FLASH0D14
N0FLASH0D0140080
P0FLASH0D0140080
N0FLASH0D070000
P0FLASH0D070000
P0R5201
P0U22034
P0FLASH0OE#
P0R5302
P0U401 P0FLASH0RESET#
P0R5102
P0U22017 P0FLASH0RY/BY#
P0U22013
P0FLASH0WE#
P0U2009 P0FPGA0MISO
P0U2004 P0FPGA0MOSI
P0R4601
P0U2101 P0FPGA0SPI0SEL#
P0C302
P0C402
P0C602
P0C2102
P0C2202
P0C2402
P0C6102
P0C6202
P0J805
P0JP102
P0R1601
P0R4202
P0R4401
P0U403
P0U1403
P0U1906
P0U19010
P0U2008
P0U2103
P0U22033
P0U22052
P0JP101
P0R401
P0U22016
P0JP602
P0R4702
P0U2102
P0R3601 P0U2003
P0R3602
P0U20013
P0R3701
P0U2006
P0R3702
P0U20010
P0U404
P0U22014
P0U1404
P0U20015
P0U2201
P0U2202
P0U22015
P0U22027
P0U22028
P0U22030
P0U22055
P0U22056
P0U402 P0PO0RESET#
P0U20012 P0PSOC0MISO
P0U2007 P0PSOC0MOSI
P0R4201
P0U2001 P0PSOC0SPI0MODE
P0J801
P0JP601
P0R5701
N0PSOC0SPI0SEL#
N0PSOC0SPI0SEL#
P0PSOC0SPI0SEL#
P0R4502 P0U1901 P0U19013 N0SF0HOLD#
N0SF0HOLD#
P0SF0HOLD#
P0U1903
P0U1907
P0U2104
N0SF0SEL#
N0SF0SEL#
P0R3002
P0U1905
P0U1909
N0SF0W#
N0SF0W#
P0SF0W#
P0J804
P0R4402
P0U19012
P0U19016
N0SPI0CLK
N0SPI0CLK
N0SPI0CLK
P0SPI0CLK
P0J802
P0U19011
P0U19015 P0U2002
P0U2005
N0SPI0FLASH0SI
N0SPI0FLASH0SI
N0SPI0FLASH0SI
P0J803
P0U1904
P0U1908
P0U20011
P0U20014
N0SPI0FLASH0SO
N0SPI0FLASH0SO
N0SPI0FLASH0SO
P0FLASH0D0140080
P0FLASH0D070000
P0FLASH0A0210000
P0SPI0CLK
P0PSOC0SPI0SEL#
P0PSOC0SPI0MODE
P0PSOC0MOSI
P0PSOC0MISO
P0PO0RESET#
P0FLASH0BYTE#
P0FLASH0CE#
P0FLASH0OE#
P0FLASH0RESET#
P0FLASH0RY/BY#
P0FLASH0WE#
P0FPGA0MISO
P0FPGA0MOSI
P0FPGA0SPI0SEL#
P0SF0HOLD#
P0SF0W#
P0FLASH0A0 P0FLASH0A1 P0FLASH0A2 P0FLASH0A3 P0FLASH0A4 P0FLASH0A5 P0FLASH0A6 P0FLASH0A7 P0FLASH0A8 P0FLASH0A9 P0FLASH0A10 P0FLASH0A11 P0FLASH0A12 P0FLASH0A13 P0FLASH0A14 P0FLASH0A15 P0FLASH0A16 P0FLASH0A17 P0FLASH0A18 P0FLASH0A19 P0FLASH0A20 P0FLASH0A21
P0FLASH0D0 P0FLASH0D1 P0FLASH0D2 P0FLASH0D3 P0FLASH0D4 P0FLASH0D5 P0FLASH0D6 P0FLASH0D7
P0FLASH0D8 P0FLASH0D9 P0FLASH0D10 P0FLASH0D11 P0FLASH0D12 P0FLASH0D13 P0FLASH0D14
P0C301
P0C302
P0C401
P0C402
P0C601
P0C602
P0C2101
P0C2102
P0C2201
P0C2202
P0C2401
P0C2402
P0C6101
P0C6102
P0C6201
P0C6202
P0J801
P0J802
P0J803
P0J804
P0J805
P0J806
P0JP101
P0JP102
P0JP601
P0JP602
P0R401 P0R402
P0R1601 P0R1602
P0R3001 P0R3002
P0R3601
P0R3602
P0R3701
P0R3702
P0R4201 P0R4202
P0R4401 P0R4402
P0R4501 P0R4502
P0R4601 P0R4602
P0R4701 P0R4702
P0R5001 P0R5002
P0R5101 P0R5102
P0R5201 P0R5202
P0R5301
P0R5302
P0R5701 P0R5702
P0U401
P0U402
P0U403
P0U404
P0U405
P0U1402
P0U1403
P0U1404
P0U1405
P0U1901
P0U1902
P0U1903
P0U1904
P0U1905
P0U1906
P0U1907
P0U1908
P0U1909
P0U19010
P0U19011
P0U19012
P0U19013
P0U19014
P0U19015
P0U19016
P0U2001
P0U2002
P0U2003
P0U2004
P0U2005
P0U2006
P0U2007
P0U2008
P0U2009
P0U20010
P0U20011 P0U20012
P0U20013
P0U20014
P0U20015
P0U20016
P0U2101
P0U2102
P0U2103
P0U2104
P0U2105
P0U2201
P0U2202
P0U2203
P0U2204
P0U2205
P0U2206
P0U2207
P0U2208
P0U2209
P0U22010
P0U22011
P0U22012
P0U22013
P0U22014
P0U22015
P0U22016
P0U22017
P0U22018
P0U22019
P0U22020
P0U22021
P0U22022
P0U22023
P0U22024
P0U22025
P0U22026
P0U22027
P0U22028
P0U22029
P0U22030
P0U22031
P0U22032
P0U22033
P0U22034
P0U22035
P0U22036
P0U22037
P0U22038
P0U22039
P0U22040
P0U22041
P0U22042
P0U22043
P0U22044
P0U22045
P0U22046
P0U22047
P0U22048
P0U22049
P0U22050
P0U22051
P0U22052
P0U22053
P0U22054
P0U22055
P0U22056
P0C301
P0C401
P0C601
P0C2101
P0C2201
P0C2401
P0C6101
P0C6201
P0J806
P0R402
P0R3001
P0R4501
P0R4602
P0R4701
P0R5002
P0R5101
P0R5202
P0R5301
P0R5702
P0U405
P0U1405
P0U1902
P0U19014
P0U20016
P0U2105
P0U22029
P0U22043
P0U22051
P0U22031
P0U22026
P0U22025
P0U22024
P0U22023
P0U22022
P0U22021
P0U22020
P0U22010
P0U2209
P0U2208
P0U2207
P0U2206
P0U2205
P0U2204
P0U2203
P0U22054
P0U22019
P0U22018
P0U22011
P0U22012 P0R1602
P0U22053
P0R5001
P0U1402
P0U22032
P0U22035
P0U22037
P0U22039
P0U22041
P0U22044
P0U22046
P0U22048
P0U22050
P0U22036
P0U22038
P0U22040
P0U22042
P0U22045
P0U22047
P0U22049
P0R5201
P0U22034
P0R5302
P0U401
P0R5102
P0U22017
P0U22013
P0U2009
P0U2004
P0R4601
P0U2101
P0C302
P0C402
P0C602
P0C2102
P0C2202
P0C2402
P0C6102
P0C6202
P0J805
P0JP102
P0R1601
P0R4202
P0R4401
P0U403
P0U1403
P0U1906
P0U19010
P0U2008
P0U2103
P0U22033
P0U22052
P0JP101
P0R401
P0U22016
P0JP602
P0R4702
P0U2102
P0R3601 P0U2003
P0R3602
P0U20013
P0R3701
P0U2006
P0R3702
P0U20010
P0U404
P0U22014
P0U1404
P0U20015
P0U2201
P0U2202
P0U22015
P0U22027
P0U22028
P0U22030
P0U22055
P0U22056
P0U402
P0U20012
P0U2007
P0R4201
P0U2001
P0J801
P0JP601
P0R5701
P0R4502 P0U1901 P0U19013
N0SF0SEL#
P0U1903
P0U1907
P0U2104
P0R3002
P0U1905
P0U1909
P0J804
P0R4402
P0U19012
P0U19016
N0SPI0FLASH0SI
P0J802
P0U19011
P0U19015 P0U2002
P0U2005 N0SPI0FLASH0SO
P0J803
P0U1904
P0U1908
P0U20011
P0U20014
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 10 - Miscellaneous FunctionsSize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 10 12
SCL1
GND2 ADD1 3
V+ 4
ADD0 5SDA6
U1
TMP100
123456
J7
6-pi
n R
A H
eade
r
123456
J6
6-pi
n R
A H
eade
r
GND
GND
+3.3V
+3.3V
DIGI1_[3..0]
DIGI2_[3..0]
DIGI1_0DIGI1_1DIGI1_2DIGI1_3
DIGI2_0DIGI2_1DIGI2_2DIGI2_3
IIC_SCLIIC_SDA
GND
+3.3V
GND
DIGI1_[3..0]
DIGI2_[3..0]
1 23 45 67 89 10
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40
J4
HEADER 20x2 TH
GND GND
+3.3V
GND
+5V
Bank0_IO[32..1]
BANK0_IO1BANK0_IO3
BANK0_IO4
BANK0_IO5BANK0_IO6
BANK0_IO7BANK0_IO8
BANK0_IO9BANK0_IO10
BANK0_IO11BANK0_IO12
BANK0_IO13BANK0_IO14
BANK0_IO15BANK0_IO16
BANK0_IO17BANK0_IO18
BANK0_IO19BANK0_IO20
BANK0_IO21BANK0_IO22
BANK0_IO23BANK0_IO24
BANK0_IO25BANK0_IO26
BANK0_IO27BANK0_IO28
BANK0_IO29BANK0_IO30
BANK0_IO31BANK3_IO2BANK0_IO32BANK3_IO1
Bank0_IO[32..1]
1234
J1
HEA
DER
4_T
H
+3.3V
GND
D5
LED_Green
D4
LED_Green
D3
LED_Green
D2
LED_Green
R9
681R 0603
R3
681R 0603
R8
681R 0603
R7
681R 0603
LED1
LED2
LED3
LED4
GND
BANK3_IO1
BANK3_IO2
BANK1_IO1 BANK1_IO1
BANK0_IO2
Layout note: center-ton-center spacing of J6/J7 must be 0.9"
P0D201 P0D202
P0D301 P0D302
P0D401 P0D402
P0D501 P0D502
P0J101
P0J102
P0J103
P0J104
P0J401 P0J402
P0J403 P0J404
P0J405 P0J406
P0J407 P0J408
P0J409 P0J4010
P0J4011 P0J4012
P0J4013 P0J4014
P0J4015 P0J4016
P0J4017 P0J4018
P0J4019 P0J4020
P0J4021 P0J4022
P0J4023 P0J4024
P0J4025 P0J4026
P0J4027 P0J4028
P0J4029 P0J4030
P0J4031 P0J4032
P0J4033 P0J4034
P0J4035 P0J4036
P0J4037 P0J4038
P0J4039 P0J4040
P0J601
P0J602
P0J603
P0J604
P0J605
P0J606
P0J701
P0J702
P0J703
P0J704
P0J705
P0J706
P0R301 P0R302
P0R701 P0R702
P0R801 P0R802
P0R901 P0R902
P0U101
P0U102 P0U103
P0U104
P0U105 P0U106
P0J101
P0J403
P0J606
P0J706
P0U104
P0J402
N0BANK00IO0320010
P0BANK00IO0320010
P0J405
N0BANK00IO1
N0BANK00IO1
P0BANK00IO1
P0J404
N0BANK00IO2
N0BANK00IO2
P0BANK00IO2
P0J407
N0BANK00IO3
N0BANK00IO3
P0BANK00IO3
P0J406
N0BANK00IO4
N0BANK00IO4
P0BANK00IO4
P0J409
N0BANK00IO5
N0BANK00IO5
P0BANK00IO5
P0J408
N0BANK00IO6
N0BANK00IO6
P0BANK00IO6
P0J4011
N0BANK00IO7
N0BANK00IO7
P0BANK00IO7
P0J4010
N0BANK00IO8
N0BANK00IO8
P0BANK00IO8
P0J4013
N0BANK00IO9
N0BANK00IO9
P0BANK00IO9
P0J4012
N0BANK00IO10
N0BANK00IO10
P0BANK00IO10
P0J4015
N0BANK00IO11
N0BANK00IO11
P0BANK00IO11
P0J4014
N0BANK00IO12
N0BANK00IO12
P0BANK00IO12
P0J4017
N0BANK00IO13
N0BANK00IO13
P0BANK00IO13
P0J4016
N0BANK00IO14
N0BANK00IO14
P0BANK00IO14
P0J4019
N0BANK00IO15
N0BANK00IO15
P0BANK00IO15
P0J4018
N0BANK00IO16
N0BANK00IO16
P0BANK00IO16
P0J4021
N0BANK00IO17
N0BANK00IO17
P0BANK00IO17
P0J4020
N0BANK00IO18
N0BANK00IO18
P0BANK00IO18
P0J4023
N0BANK00IO19
N0BANK00IO19
P0BANK00IO19
P0J4022
N0BANK00IO20
N0BANK00IO20
P0BANK00IO20
P0J4025
N0BANK00IO21
N0BANK00IO21
P0BANK00IO21
P0J4024
N0BANK00IO22
N0BANK00IO22
P0BANK00IO22
P0J4027
N0BANK00IO23
N0BANK00IO23
P0BANK00IO23
P0J4026
N0BANK00IO24
N0BANK00IO24
P0BANK00IO24
P0J4029
N0BANK00IO25
N0BANK00IO25
P0BANK00IO25
P0J4028
N0BANK00IO26
N0BANK00IO26
P0BANK00IO26
P0J4031
N0BANK00IO27
N0BANK00IO27
P0BANK00IO27
P0J4030
N0BANK00IO28
N0BANK00IO28
P0BANK00IO28
P0J4033
N0BANK00IO29
N0BANK00IO29
P0BANK00IO29
P0J4032
N0BANK00IO30
N0BANK00IO30
P0BANK00IO30
P0J4035
N0BANK00IO31
N0BANK00IO31
P0BANK00IO31
P0J4036
N0BANK00IO32
N0BANK00IO32
P0BANK00IO32
P0J4037 N0BANK10IO1
P0BANK10IO1
P0J4038 N0BANK30IO1
P0BANK30IO1
P0J4034 N0BANK30IO2
P0BANK30IO2
N0DIGI10030000
P0DIGI10030000
P0J701
N0DIGI100
N0DIGI100 P0DIGI100
P0J702
N0DIGI101
N0DIGI101
P0DIGI101
P0J703
N0DIGI102
N0DIGI102
P0DIGI102
P0J704
N0DIGI103
N0DIGI103
P0DIGI103
N0DIGI20030000
P0DIGI20030000
P0J601
N0DIGI200
N0DIGI200 P0DIGI200
P0J602
N0DIGI201
N0DIGI201
P0DIGI201
P0J603
N0DIGI202
N0DIGI202
P0DIGI202
P0J604
N0DIGI203
N0DIGI203
P0DIGI203
P0D201
P0D301
P0D401
P0D501
P0J104
P0J401
P0J4039 P0J4040 P0J605
P0J705
P0U102 P0U103
P0U105
P0J102
P0U101 P0IIC0SCL
P0J103
P0U106 P0IIC0SDA
P0R901 P0LED1
P0R301 P0LED2
P0R801 P0LED3
P0R701 P0LED4 P0D202 P0R702
P0D302 P0R802
P0D402 P0R302
P0D502 P0R902
P0DIGI20030000
P0DIGI10030000
P0BANK00IO0320010
P0BANK10IO1 P0BANK30IO1
P0BANK30IO2
P0LED1
P0LED2
P0LED3
P0LED4
P0IIC0SDA
P0IIC0SCL
P0BANK00IO1 P0BANK00IO2 P0BANK00IO3 P0BANK00IO4 P0BANK00IO5 P0BANK00IO6 P0BANK00IO7 P0BANK00IO8 P0BANK00IO9 P0BANK00IO10 P0BANK00IO11 P0BANK00IO12 P0BANK00IO13 P0BANK00IO14 P0BANK00IO15 P0BANK00IO16 P0BANK00IO17 P0BANK00IO18 P0BANK00IO19 P0BANK00IO20 P0BANK00IO21 P0BANK00IO22 P0BANK00IO23 P0BANK00IO24 P0BANK00IO25 P0BANK00IO26 P0BANK00IO27 P0BANK00IO28 P0BANK00IO29 P0BANK00IO30 P0BANK00IO31 P0BANK00IO32
P0DIGI100 P0DIGI101 P0DIGI102 P0DIGI103
P0DIGI200 P0DIGI201 P0DIGI202 P0DIGI203
P0D201 P0D202
P0D301 P0D302
P0D401 P0D402
P0D501 P0D502
P0J101
P0J102
P0J103
P0J104
P0J401 P0J402
P0J403 P0J404
P0J405 P0J406
P0J407 P0J408
P0J409 P0J4010
P0J4011 P0J4012
P0J4013 P0J4014
P0J4015 P0J4016
P0J4017 P0J4018
P0J4019 P0J4020
P0J4021 P0J4022
P0J4023 P0J4024
P0J4025 P0J4026
P0J4027 P0J4028
P0J4029 P0J4030
P0J4031 P0J4032
P0J4033 P0J4034
P0J4035 P0J4036
P0J4037 P0J4038
P0J4039 P0J4040
P0J601
P0J602
P0J603
P0J604
P0J605
P0J606
P0J701
P0J702
P0J703
P0J704
P0J705
P0J706
P0R301 P0R302
P0R701 P0R702
P0R801 P0R802
P0R901 P0R902
P0U101
P0U102 P0U103
P0U104
P0U105 P0U106
P0J101
P0J403
P0J606
P0J706
P0U104
P0J402
P0J405
P0J404
P0J407
P0J406
P0J409
P0J408
P0J4011
P0J4010
P0J4013
P0J4012
P0J4015
P0J4014
P0J4017
P0J4016
P0J4019
P0J4018
P0J4021
P0J4020
P0J4023
P0J4022
P0J4025
P0J4024
P0J4027
P0J4026
P0J4029
P0J4028
P0J4031
P0J4030
P0J4033
P0J4032
P0J4035 P0J4036
P0J4037 P0J4038
P0J4034
P0J701
P0J702
P0J703
P0J704
P0J601
P0J602
P0J603
P0J604
P0D201
P0D301
P0D401
P0D501
P0J104
P0J401
P0J4039 P0J4040 P0J605
P0J705
P0U102 P0U103
P0U105
P0J102
P0U101
P0J103
P0U106
P0R901
P0R301
P0R801
P0R701 P0D202 P0R702
P0D302 P0R802
P0D402 P0R302
P0D502 P0R902
1
1
2
2
3
3
4
4
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Avnet Engineering ServicesTitle:
Sheet Sheet 11 - Board PowerSize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 11 12
GND
GND
+5V_USB
PO_RESET#
C29
0.47uF 0603
GND
RSTVDD1
GND2 MR 3
SENSE 4
RSTSENSE5 VDD6U3
TPS3106K33
+3.3V
GND
R14357K 0603
R20432K 0603
GND
+1.2V
GND
1 3
2
JP2
L1
3.3uH, 1.4A 12
C510uF 0805 LE
+3.3V
GND
R12
182K 0603
12
C710uF 0805 LE
R11806K 0603
GND
C25
0.01uF 0402 GND
+5V
314
2SW1
PB SPST Switch
+3.3V
GNDC20.1uF 0402
GND
L2
3.3uH, 1.4A 12
C1210uF 0805 LE
12
C910uF 0805 LE
R18182K 0603
R19
182K 0603
C1033pF 0402
GNDRSTSENSE#
12
JP3
HEADER 2/TH
GND
R13
0R0.10 0805
R21
0R0.10 0805
TP1
TEST PAD
TP3
TEST PAD
TP4
TEST PAD
TP2TEST PAD
JP3 default = Open. Jumper JP3 1:2 to hold Power-on Reset (PO_RESET#) active.
C80.01uF 0201
FB2120, 3A, 1206
JP2 default = 1:2 (USB Power)
D1
LED_Green
GND
GND 1
RESET# 2VDD3
U2
TPS3809K33
R1
681R 0603
R15
10K0 0402
R610K0 0402
R17
10K0 0402
+3.3V
RSTVDD#+3.3V
GND
1
2
J3
2.1m
m B
arre
l Soc
ket,
SMT
1 2C1
10uF 0805 LE
SW 1
MODE2 FB 3EN4 Vin5
GND6 PAD 7
U5
TPS62290
SW 1
MODE2 FB 3EN4 Vin5
GND6 PAD 7
U24
TPS62290
RSTVDD#
GND
A 3
Com 2
B 1
JT1
Jumper 0R0 0402
+5V
GND
GND
GND
C26
0.01uF 0402 GND
1 2C63
10uF 0805 LE
Layout Note:Place C1 & C25 as close as possible to U5.5
Layout Note:Place C63 & C26 as close as possible to U24.5
U_Sp3A Eval Revision History12 Sp3A Eval Revision History.SchDoc
JT1 default setting = 1:2
1
24
53
U23
NC7SV08
+5V_Prog
1 3
2
JP7
+5V
JP7 default = 1:2 (USB Power)
NOTE: The board may be powered as follows:from a +5V power supply (JP2=2:3, JP7=1:2), USB power (JP2=1:2, JP7=1:2), or via the Cypress MiniProg (JP7=2:3, JP2=N/A)
P0C101 P0C102
P0C201
P0C202
P0C501
P0C502
P0C701
P0C702
P0C801
P0C802
P0C901
P0C902
P0C1001
P0C1002
P0C1201
P0C1202
P0C2501 P0C2502
P0C2601 P0C2602
P0C2901 P0C2902
P0C6301
P0C6302
P0D101 P0D102
P0FB201
P0FB202
P0J301
P0J302
P0JP201
P0JP202
P0JP203
P0JP301
P0JP302
P0JP701
P0JP702
P0JP703
P0JT101
P0JT102
P0JT103
P0L101 P0L102
P0L201 P0L202
P0R101 P0R102
P0R601
P0R602
P0R1101
P0R1102
P0R1201 P0R1202
P0R1301 P0R1302
P0R1401
P0R1402
P0R1501 P0R1502
P0R1701 P0R1702
P0R1801
P0R1802
P0R1901 P0R1902
P0R2001
P0R2002
P0R2101 P0R2102
P0SW101 P0SW102
P0SW103 P0SW104
P0TP101
P0TP201
P0TP301
P0TP401
P0U201
P0U202
P0U203
P0U301
P0U302 P0U303
P0U304
P0U305
P0U306
P0U501
P0U502 P0U503
P0U504
P0U505
P0U506 P0U507
P0U2301
P0U2302
P0U2303
P0U2304
P0U2305
P0U2401
P0U2402 P0U2403
P0U2404
P0U2405
P0U2406 P0U2407
P0R1401
P0R2102
P0TP401
P0C2901
P0R601
P0R1302
P0R1502
P0R1702
P0TP201
P0U306
P0U2305
P0C101
P0C2501
P0C2601
P0C6301
P0FB201
P0JT103
P0R101
P0U203 P0U505
P0U2405
P0JP703
P0JP201
P0C102
P0C202
P0C502
P0C702
P0C802
P0C902
P0C1202
P0C2502
P0C2602
P0C2902
P0C6302
P0D101
P0J302
P0JP302
P0JT101
P0R1202
P0R1902
P0R2002
P0SW102
P0SW103
P0U201
P0U302
P0U506 P0U507
P0U2303
P0U2406 P0U2407
P0C201
P0JP301
P0R602
P0SW101
P0SW104
P0U2302
P0C501 P0C701
P0L102
P0R1101
P0R1301
P0TP101
P0C801
P0R1402
P0R2001
P0U304
P0C901
P0C1001
P0C1201
P0L202
P0R1801
P0R2101
P0TP301
P0C1002
P0R1802
P0R1901
P0U2403
P0D102 P0R102
P0FB202
P0JP702
P0J301 P0JP203
P0JP202
P0JP701
P0JT102
P0U502
P0U2402
P0L101
P0U501
P0L201
P0U2401
P0R1102
P0R1201
P0U503
P0U202 P0U504
P0U303
P0U2304 P0PO0RESET#
P0R1501
P0U305
P0U2301
N0RSTSENSE#
P0R1701
P0U301
P0U2404 N0RSTVDD#
N0RSTVDD#
P0PO0RESET#
P0C101 P0C102
P0C201
P0C202
P0C501
P0C502
P0C701
P0C702
P0C801
P0C802
P0C901
P0C902
P0C1001
P0C1002
P0C1201
P0C1202
P0C2501 P0C2502
P0C2601 P0C2602
P0C2901 P0C2902
P0C6301
P0C6302
P0D101 P0D102
P0FB201
P0FB202
P0J301
P0J302
P0JP201
P0JP202
P0JP203
P0JP301
P0JP302
P0JP701
P0JP702
P0JP703
P0JT101
P0JT102
P0JT103
P0L101 P0L102
P0L201 P0L202
P0R101 P0R102
P0R601
P0R602
P0R1101
P0R1102
P0R1201 P0R1202
P0R1301 P0R1302
P0R1401
P0R1402
P0R1501 P0R1502
P0R1701 P0R1702
P0R1801
P0R1802
P0R1901 P0R1902
P0R2001
P0R2002
P0R2101 P0R2102
P0SW101 P0SW102
P0SW103 P0SW104
P0TP101
P0TP201
P0TP301
P0TP401
P0U201
P0U202
P0U203
P0U301
P0U302 P0U303
P0U304
P0U305
P0U306
P0U501
P0U502 P0U503
P0U504
P0U505
P0U506 P0U507
P0U2301
P0U2302
P0U2303
P0U2304
P0U2305
P0U2401
P0U2402 P0U2403
P0U2404
P0U2405
P0U2406 P0U2407
P0R1401
P0R2102
P0TP401
P0C2901
P0R601
P0R1302
P0R1502
P0R1702
P0TP201
P0U306
P0U2305
P0C101
P0C2501
P0C2601
P0C6301
P0FB201
P0JT103
P0R101
P0U203 P0U505
P0U2405
P0JP703
P0JP201
P0C102
P0C202
P0C502
P0C702
P0C802
P0C902
P0C1202
P0C2502
P0C2602
P0C2902
P0C6302
P0D101
P0J302
P0JP302
P0JT101
P0R1202
P0R1902
P0R2002
P0SW102
P0SW103
P0U201
P0U302
P0U506 P0U507
P0U2303
P0U2406 P0U2407
P0C201
P0JP301
P0R602
P0SW101
P0SW104
P0U2302
P0C501 P0C701
P0L102
P0R1101
P0R1301
P0TP101
P0C801
P0R1402
P0R2001
P0U304
P0C901
P0C1001
P0C1201
P0L202
P0R1801
P0R2101
P0TP301
P0C1002
P0R1802
P0R1901
P0U2403
P0D102 P0R102
P0FB202
P0JP702
P0J301 P0JP203
P0JP202
P0JP701
P0JT102
P0U502
P0U2402
P0L101
P0U501
P0L201
P0U2401
P0R1102
P0R1201
P0U503
P0U202 P0U504
P0U303
P0U2304
N0RSTSENSE# P0R1501
P0U305
P0U2301
N0RSTVDD#
P0R1701
P0U301
P0U2404
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C C
B B
A A
Avnet Engineering ServicesTitle:
Sheet 12 - Revision HistorySize: Rev:
B BDocument Number:
Date: Sheet of
Doc #
5/13/2008 12 12
REV A REV B
Added 10K pullup (R58) to PsOC_FPGA_PROG
Corrected PCB footprint of J2 PsOC ISSP header (connector keying was reversed).
Renamed NET PsOC_P5_1 to PUSH_C
Updated silkscreen on PCB as follows: Change EF1 to PUSH_A Change EF2 to PUSH_B Change EF3 to PUSH_C Change EF4 to RESET
Add labels to J8: SEL#, MOSI, MISO, SCK, GND, 3.3V
Reduce font on JP4 and MODE to make room for mode setting information, such as: M1, M2 = SPI M0, M2 = BPI M1 = JTAG
Add labels to south side of JP4 M0 M1 M2 PUDC
Move J4 label to the right. Remove 1 and 4 labels. Using small font if necessary, label pins left to right as: 3.3V SCL SDA GND
Add "www.em.avnet.com/spartan3a-evl" wherever it will fit, either front or back
Replaced 5.0V power supervisor TPS3809I50DBVT (U2) with 3.3V version (TPS3809K33DBVT)
Changed 681-ohm resistor R1 from 0402 to 0603Changed 10K resistors (R6 & R15) from 0603 to 0402
Layout: Change J6/J7 spacing from the current 31/32" to 0.9"
Added Jumper JT1 to allow different 1.2V/3.3V enable modes.
Added 10K pullup resistor R59 to PsOC/FPGA UART_RxD line
Replaced TPS62420 dual step-down converter with two TPS62290 step-down converters; added additional 10uF (C63) and 0.01uF (C26) capacitors to Vin of additional converter.
Added jumper JP7 to allow board power from Cypress MiniProg
