Avionics databus.pdf

ELEC4504 Avionics Systems 157

CHAPTER 14. System Integration/ Data transferSince parts of systems are necessarily installed in different parts of the aircraft, it is necessary to provide some

means of transmitting information from one to another.

e.g. VOR receiver - avionics bay

Control head / Indicator - cockpit

Temperature sensor - outside skin

Air Data Computer - avionics bay

Also, as systems become more integrated more intercommunication is required

e.g. INU

INU

SatelliteAntennaSteering

Flight Management

System

CockpitDisplay

aircraft attitude

attitudepositionvelocity

steeringattitude

Figure 66:

Integration of INU, Satellite Antenna and Flight Management System

14.1. Synchros

Until recently much of the instrumentation in the cockpit has been of electromechanical design, with the infor-

mation being presented in the form of a rotating needle and a dial.

In order to transmit rotational information electrically, devices called synchros were used. These are essentially

rotating transformers and motors.

A

B C

A

B C

26VAC400Hz

TransmitterReceiver

Figure 67:

Wiring Diagram of Synchro Devices

158 ELEC4504 Avionics Systems

As shown above, each synchro consists of three static windings wound at 120˚ intervals, and a single rotor

winding. As the name suggests, the static windings are fixed to the body of the synchro while the rotor winding

is attached to a shaft which is free to rotate.

When an excitation voltage (in aircraft usually 400 Hz, 26 Volts) is applied to the rotors, voltages are induced

in each of the stator windings. The voltages are determined by the angle of rotation of the rotor.

When a synchro receiver is connected as shown, its rotor will take up the same angle of rotation as the trans-

mitter rotor.

Thus the angular information has been transmitted via an electrical connection.

Information available in this form includes:

i) pitch, roll and heading from INU

ii) altitude from an altimeter

iii) relative bearing from an ADF antenna

14.1.1 Problems that can occur with synchro systems are:

i) loss of the excitation voltage (circuit breaker opening)

ii) interchange of wires (causes incorrect readings)

14.1.2 Disadvantages

i) - relatively large and bulky

ii) - require separate excitation voltage

iii) - since they are mechanical, they are subject to wear and breakdown

iv) - in mixed analogue/digital systems, synchro to digital and digital to synchro conversion modules are

required and these are usually expensive.

Ironically, since synchros are present in many current aircraft systems, new, all digital equipment may still

produce information in synchro format by use of a digital to synchro converter. Some other all digital piece

of equipment may provide for synchro input by means of a synchro to digital converter.

14.2. Fundamentals of digital data transmission

Digital data transmission has the advantage that it is very flexible and has the potential to reduce drastically

the amount of wiring required.

e.g. to send pitch roll and heading information, the analogue approach would required 11 wires (3 for each

synchro and 2 for a shared reference. By contrast, a digital system needs only two wires and can transmit much

more data than just the attitude information.

A typical process for transmitting data digitally is as follows:


Processing16

(16 lines)

sensor

A/D

Figure 68:

Typical Digital Data Transfer

This does not appear to be much of an improvement, since 16 wires are required (1 bit/wire). However, it is

possible to send the same information in a serial fashion in which case only two wires are needed. Note that, in

the example given, the data rate would be reduced by a factor of 16, but the data rates can be increased to com-

pensate.

Example

Signal byte with binary representation 010110102 is to be transmitted serially

Tclock Txclock = 8 x Tclock

parallel

serial

Rxclock

serial

1

0

0 101 1

Start Stop

time

01011

01011010

010

01011010

10 0

shift register

shiftregister

register

Rclock

parallel

01011010

register

Figure 69:

Diagram of Conversion between Parallel/Serial/Parallel Data Transfer

Note: a shift register shifts its contents one bit for each clock pulse e.g.


REGISTER

0 1 0 1 1

1 0 1 0 1

OutputInput

1

1

1

0

0 1 0 1 0

Start

Clock pulse 1

Clock pulse 2

Time domain multiplexing of individual bits allows transmission on a single line. The data rate, however, is

lower T xclock

T clock------------------ = number of bits transmitted/number of words transmitted

In Figure 67. all 8 bits of the byte are clocked in to the parallel register, they are then copied to the serial shift

register. Then the bits clocked from the serial shift register on to the transmission line.

14.2.1 Logic Levels

The transmitter sends binary ones and zeros as specific voltage levels. However, during their travel along the trans-

mission wires, the signals become modified by attenuation and noise, so that it can be difficult for the receiver to

decide whether the signal is a one or a zero. Thus for each type of logic, the voltage levels representing ones and

zeros are set far enough apart that there is little chance of misinterpretation.

5V

0V

transmitted ‘high’ or ‘1’

transmitted ‘low’ or ‘0’

voltage values receiverinterprets as a ‘1’

voltage values receiverinterprets as a ‘0’

Figure 70:

Illustration of Logic Levels


Example (TTL or transistor-transistor logic)

0.4V 0.7V

driver is requiredto provide logic 0signal lower than 0.4V

receiver is requiredto accept as logic 0all signals withamplitude ≤ 0.7V

Figure 71:

TTL Noise Margin

In this case the noise margin is 0.3V which means that the transmitted signal can be distorted by 0.3V before

a false value is detected

14.2.2 Synchronization

One way by which a receiver can improve the probability of choosing the right value is to average the signal over

the width of a bit. To do this, however, it must know where the boundaries of the bits are. If it were to average a

signal over half a zero bit and half a one bit, the result would not be correct. Thus it is advantageous for the receiver

to have a copy of the clock signal from the transmitter.

This can be sent on a separate set of wires but, as we shall see, data can be sent using codes which are self-clocking

in which case, only one set of wires is needed.

14.3. Overview of Digital Devices

Today’s digital devices are built exclusively in the form of integrated circuits (ICs)

These can be divided into the following categories:

a) programmable execution devices (microprocessors, microcontrollers)

b) memory devices

i) SRAM (static random access memory)

ii) DRAM (dynamic random access memory)

iii) ROM (read only memory)

iv) EPROM (erasable programmable ROM)

Discrete logic devices

a) logic families such as TTL (based on the methods used to implement the functions)


b) programmable logic devices

c) ASICs - application specific integrated circuits

14.3.1 Microprocessors

The manufacturing technology allows creation of devices containing ~ 109 (Intel Tukwila 2x109 announced

2 Feb 2008 ) transistors, but MIL spec, high reliability ICs are available only after a 5 - 10 year lag. Military/

avionics technology (MIL spec), therefore is conservative compared to the current consumer market technolo-

gy

14.3.1.1 Current Standard:

-MIL STD 1750A

- standardized instruction set

- 16 bit data bus

- price ~ 10 x today’s microprocessors

14.3.2 Memory Devices

RAM - random access memory

in each memory cycle an arbitrary (random) location can be read or written to

m

2m = n2addressregister

row decoder

column decoder

2m

2

2m

2

1

n1 n

memory arrayn x n

selectedcell

indicatesthe numberof lines

Figure 72:

Random Access Memory


Static Memory (SRAM) uses a bistable device (flip-flop) to store binary information

D

CK

Q

Q

DATA IN

STROBE

DATA OUT

Figure 73:

Static RAM Element

The data out is set to whatever data in is when the strobe pulse is received

The flip-flop stores the information as long as power supply voltage is provided, but it dissipates power con-

tinuously causing high power consumption for large memories.

Requires at least two transistors plus resistors and capacitors. (takes up a lot of space on the chip)

14.3.3 Dynamic Memory (DRAM)

Information is stored on a capacitor and unless restored, will disappear with time due to the leakage of charge

from the capacitor. (leakage current)

bit information

control signal toopen switch

does not have to beanactual capacitor

Figure 74:

Memory Element for DRAM

DRAM memory requires only one transistor for 1 bit of information.

High capacity (Gbit) low power consumption memory uses DRAM technology.

14.3.4 Other types of Memory:

ROM (read only memory)

a) mask programmable - programmed at the factory, can’t be changed

b) electrically programmable, UV erasable EPROM. can be programmed in the field. Erased by exposure to

ultraviolet light

c) electrically programmable and erasable EEPROM - can be erased and programmed electronically


14.4. Avionics Data Buses

Prior to the introduction of digital technology, avionics systems were connected by wires which were dedicated to

one task. e.g. the wiring between an ILS receiver and the HSI

synchro bearing

horizontal deviation

horizontal flag

vertical deviation

vertical flag

course select

ILSReceiver HSI

synchro reference

Figure 75:

Wiring for analog ILS receiver/HSI

Using data bus technology, the above function can be accomplished using two pairs of twisted, shielded wires.

14.4.1 The Twisted Shielded Pair

Most data buses use a twisted shielded pair of wires for data transmission. A pair of wires is used so that each

signal path has both a signal wire and a ground wire. Normally analog signals are carried on one wire with either

a single separate wire serving as ground for several signals or the aircraft ground is used. In either case the

ground can be noisy and can cause interference.

The wires are twisted to reduce the effects of magnetic interference. Remember that a changing magnetic field

passing through a conducting loop will induce a voltage in the loop. An aircraft is full of varying magnetic fields

caused mainly by the electrical system which operates at 400 Hz and uses the aircraft frame as a ground con-

ductor.


Two parallel wiresand their terminationsform a loop

A changing magnetic field into or out ofthe page will induce a voltage into the loop

If the wires are twisted, the loops alternate inorientation and the induced voltage tendsto average out

Figure 76:

Effect of Magnetic Field on

Untwisted and Twisted Wire Pairs

The twisted wires are then shielded to reduce electrical coupling from outside sources (especially adjacent

wires in a cable).

14.4.2 Data Links

Data links can be divided into three main categories

i) Single source/Single sink - This is a dedicated link between two units. If the data can be transmitted only

in one direction it is called a half-duplex link. If data can be transmitted in both directions it is called a full

duplex link

ii) Single source/Multiple sink - This describes a system in which one transmitting unit can transmit to sev-

eral other units. The ARINC 429 data bus to be described later is of this type

iii) Multiple source/Multiple sink - In this system several transmitting units can transmit to several receiv-

ers. MIL-STD 1553 and ARINC 629 (used on the Boeing 777) are examples of this system

14.4.3 Coding Schemes

Digital transmissions represent data in binary notation i.e. ones and zeros. However there are many ways to

represent these values using an electrical signal and the choice of any given method depends on the require-

ments of the application.

One consideration is the synchronization of the transmitter and receiver clocks. One means of synchronizing

the clocks is to transmit the clock on a separate set of wires but this increases the wiring and weight. It is pos-

sible, however, to code the signal so that it is self-clocking.

Another consideration is the requirement for transformer or magnetic coupling. This can be an advantage in

the design of systems with many connections


14.4.3.1 Common Coding Schemes

14.4.3.1.1 Bipolar Return to Zero

1 0 1 1 0

+1

-1

0

Figure 77:

Bipolar Return to Zero Code

This is called bipolar because the ones and zeroes are represented by positive and negative values and is

called return to zero because the signal returns to zero value during each bit interval. One advantage of this

system is that it is self-clocking. i.e. by rectifying the bitstream, a clock can be generated.

Note: this method is complicated by the fact that three levels are required to be decoded.

14.4.3.1.2 Biphase level (also called Manchester code)

1 0 1 1 0

+1

-1

0

Figure 78:

Biphase Level (Manchester) Code

In this case, a one is indicated by the signal being positive in the first half of the bit period while the zero in

indicated by the signal being positive in the second half of the bit period. Self clocking is provided by the

fact that a transition occurs in the middle of every bit period


14.4.4 ARINC 429

ARINC 429 is probably the most prevalent data bus in commercial aviation today.

As mentioned above it is a single source/multiple sink system.

It operates at two clock speeds: the Low rate which clocks at 12-14.5 kHz and the High rate which clocks at

100 kHz.

The data format is shown in Figure 7.

Figure 79:

ARINC 429 Data Word

The label describes the type of data in the word. Each parameter has a unique label

e.g. x acceleration, altitude, temperature

The source/destination identifies where the information is coming from (e.g. INS) and where is going (e.g.

Flight management system)

Up to 20 receivers can be accommodated by one transmitter.

A modern aircraft such as a Boeing 767 may have as many as 150 data links to interconnect different units.


A typical topology is shown below

1 2

3 4

5

Figure 80:

Typical ARINC 429 Topology

One disadvantage of Single Source/Single Sink system is the complexity involved in making changes to the

system. This is also shown in Figure 78. The original connections are shown in solid lines while the additional

connections required to add a fifth unit are shown in dotted lines. this shows a disadvantage of the single source/

multiple sink topology.

The code used in ARINC 429 is bipolar RTZ and the wiring is twisted shielded pair

The electrical specification is shown below:

10V

-10V

0V

± 1V

± 1V

± 0.5V

TRANSMIT RECEIVE

1

0

13V

6.5V

2.5V

-2.5V

-6.5V

-13V

As can be seen in the diagram the noise margin is 2.5 V (9 - 6.5 or -6.5 - 9)


14.4.5 MIL STD 1553

This data bus standard has been in effect since 1973 and has been used on all new military aircraft since then.

most notably the F16.

The topology of this system is completely different from that of ARINC 429 since it is a multiple source system

BusController

RemoteTerminal

RemoteTerminal

only buscontrollercan initiatea data transfer

up to 31 RTs

2

2

optional

redundant bus

RemoteTerminal

BusMonitor

Figure 81:

MIL STD 1553 Data Bus Topology

Note that adding a unit to the bus is far less complicated than in the case of the ARINC 429 system

The bus controller initiates all information transfers

The bus monitor provides monitoring of bus activities

14.4.6 Data Transfer

In a simple data transfer, the bus controller (BC) sends a transmit command to a particular remote terminal

(RT). The RT then transmits a status word followed by up to 32 data words depending on the amount of data

required.

A more complex transfer is one in which an RT is to transfer data to another RT. In this case the BC issues a

transmit command to the first RT and then a receive command to the second RT. The first RT then transmits

the status word followed by the data as above. When all the data has been transmitted, the second RT transmits

a single status word to indicate that the transfer is complete and whether it was successful or not.

14.4.7 Data Transfer Formats

Manchester coding described above is used. This is good for clock recovery and also allows transformer cou-

pling to the data bus (this is an important part of the topology)


The format of the words is as follows:

the time required to transfer one data word from one RT to anotheris around 120 μseconds which is rather an expensive overhead. If, however a maximum of 32 data words were transferred, the overheads would be the samebut representing a much lower percentage of overall message time.

The Allowed RT response time is 4 to 12 μsec

intermessage gap 4 μsec

timing watchdog (response time) 14 μsec

14.4.8 Coupling Into the Bus.

Direct or Transformer coupling

Transformer

upto20 ft.,

up to 1 ft.

RT

RT

RTBC

Figure 82:

Coupling into the MIL STD 1553 Data Bus


14.4.8.1 Advantages of MIL - STD 1553 data bus

a) easy to add units to the data bus

b) less wiring than ARINC 429

c) will handle redundant busses and bus controllers

14.4.8.2 Disadvantages

a) need to have additional units (bus controller and bus monitor)

14.4.9 ARINC 629

In the civil aviation world the disadvantages of ARINC 429 have been realized.

To overcome these, a new standard, ARINC 629 has been developed and was used on the Boeing 777.

This system is similar to the MIL STD 1553 system except that the bus controllers are incorporated into each

unit on the bus

Coupling can be made using current transformers and thus the wire does not have to be cut.

14.5. Other Databusses in use today (primarily for general aviation and business aircraft)

14.5.1 Commercial Standard Data Bus

Developed by Collins Division of Rockwell International (a major avionics manufacturer)

a) similar to ARIN 429 (unidirectional)

b) two data rates - 12.5 kbits/sec or 50 kbits/sec

14.5.2 Avionics Standard Communications Bus

Developed by Honeywell

a) similar to MIL STD 1553 but uses two isolated busses

b) units may listen on both busses but transmit on only one

- allows less critical systems to receive data from more critical systems without being able to affect their

operation

c) data rate is 300 kbits/ second

d) bus can support up to 48 users


14.6. Fiber optics

One of the limitations of twisted shielded pairs is the frequency of data transmission. The upper limit is dependent

on the length of cable but is about 2 MHz. An alternative to twisted, shielded wire is fiber optic cable.

14.6.1 Advantages

Fiber optic cable provides the possibility of data rates in the neighbourhood of 100 MHz

Another advantage is the immunity to electromagnetic interference.

14.6.2 Disadvantages

Fiber optic cables connections require very accurate alignment and thus it is difficult to make reliable connec-

tors. The requirement for fiber optic connectors in the vibration and shock environment of an aircraft is espe-

cially severe.

Also, glass fibers are relatively fragile which makes them susceptible to breakage under aircraft conditions.

14.7. Software Development

Obviously without software none of the digital equipment we have been talking about would be of much use.

In fact the design, testing and control of software is one of the biggest challenges in avionics today.

14.7.1 Determining the criticality

RTCA document DO 178A “Software Considerations in Airborne Systems and Equipment Certification” de-

fines the specific methods and techniques of software design, testing, configuration and documentation.

The first step in designing software for an new avionics system is to define the criticality category. This is done

by assessing the system’s application and all failures which could result from a system malfunction. The three

categories are:

i) flight critical

ii) flight essential and

iii) flight non-essential.

A system’s category is defined by its most critical function.

The next step is to translate the criticality of the system to the software. The levels adopted by DO 178A are

Levels 1, 2 and 3 which correspond to flight critical, flight essential and flight non-essential respectively.


14.7.2 Development, Verification and Validation

First a software development plan is submitted to the regulatory agency (FAA, CAA, Transport Canada). This

includes:

- software functions

- the criticality of each function and software level

- hardware and software interfaces

- microprocessor characteristics

- built in test (BIT) and monitoring requirements

- what functional losses would occur as the result of software failure

- timing, test and partitioning requirements

Once written the software must be tested. This includes, module testing, module integration tests and software/

hardware integration tests

As an example, module testing includes logic and computational tests to determine if the module performs its

intended function. Logic testing is used to detect illogical sequences and constructs such as halted execution,

executions trapped in a loop and missing input data. Computational tests consider an algorithm’s reaction to

data within, outside and on the border of a specified range.

For flight critical systems, all verification results must be retained and all problems logged

For flight essential systems, only a Statement of Compliance is required as a summary of the testing process.

System validation is intended to show that the system function properly under adverse and failure conditions

14.7.3 Software Configuration Management (SCM) and Software Quality Assurance (SQA)

Any system incorporating software must undergo SCM and SQA.

This requires the submission of an SCM plan which may be part of the overall SQA plan. This includes a de-

scription of how SCM will be implemented and followed throughout the certification process. It should also

include how SCM will be applied during the service life of the equipment.

SCM should include documentation, identification and change control and status accounting. This involves

any post-certification software change


If the change does not affect interchangeability or the certification basis, it may be called a software status

change. If it does affect interchangeability or certification, the system will require a new part number

To comply with current standards it is necessary to use top-down programming techniques. This technique re-

quires that the overall function of the software be broken down into a hierarchy of levels with each level per-

forming more and more specific tasks. Ideally the smallest unit, called the module above, performs only one

function and has exactly specified inputs and outputs.

This structure allows testing to be done in a logical fashion starting with each module and progressing up the

chain

Figure 83:

Top Down Software Configuration

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