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Avatrel® Stress Buffer Coatings: Low Stress Passivation and Redistribution Applications
May 6, 2004Symposium on Polymers for Microelectronics
Ed Elce, Chris Apanius, Jeff Krotine, Jim Sperk, Andrew Bell, Rob Shick*
Sue Bidstrup-Allen, Paul Kohl
Takashi Hirano, Junya Kusunoki, Toshiro Takeda
Outline
§ Motivation– Simple Coatings– FEM Verification of Concept
• Modulus vs. CTE
§ Avatrel– Properties– Processing
§ Materials Integration and Reliability – Flip Chip Packages– Thermal Cycling– Pressure Cooker Test
§ New Generations§ Summary
Low Stress Motivation
§ Die are getting larger and more fragile (low k)
§ Reduction of Stress is important to maintain reliability
§ Reduce material shrinkage§ Reduce thermal stress
– Reduce Modulus, E(T) and/or CTE, α(T)
E (T) x E (T) x ∆∆αα (T) dT(T) dTss = = ∫Thermal Stress (Simple View):
Wafer Warpage with Simple Coatings
Wafer: 8 inch Si WaferThickness: 625 µmMeasuring span: 100 mm
Wafer Stress with Simple Coatings
A More Detailed View UsingFinite Element Modeling
The distortion element of 4 nodal point (#11)Nodal point : 9007
Element : 8649
Thermal stress analysis from 125 to –55degC
5 µm Mesh cut
Magnification
x
y
o
Chip
Underfill ( SB: CRP-4152R5)
BT substrate
Bump
Buffer Material(Avatrel and PBO)
ppm/ºCkgf/mm2ºCUnit
40
300
-40ºC: 212025ºC: 162080ºC: 1320125ºC: 1120
x, z: 1990y: 870
E1: 820E2: 3.1
16800
Modulus
0.30150200Avatrel
10 µm thick
0.3050330PBO (CRC)
10 µm thick
0.3529.2-Bump
0.39x, z: 17.6y: 64.1
-BT substrate
0.30α1: 32
α2: 10280Underfill
0.343.0-Chip
Poisson’s ratioCTETgItem
Material Properties
FEM Findings…
0
5
10
15
20
25
HorizontalStress
VerticalStress
ShearStress
No CoatingPBOAvatrelSt
ress
(M
Pa)
(Stress is 5 µm inside chip surface)
Reducing Modulus has a greater impact than reducing CTE
SixNy Passivation
Redistribution
Buffer CoatingBuffer Coating
Pb/Sn Solder
Wafer Level Packaging
Synergies Between Two Chemistries
Polynorbornene§ Low Dielectric Constant § Low Moisture Absorption§ Isotropic Properties§ High Tg From Backbone§ Transparency § Alkyl – Tune Modulus/Stress
Epoxy§ Adhesion§ Photosensitive§ Accepted Chemistry
Epoxy
Alkyl
Typical Properties§ ElectricalØ Dielectric Constant
2.50 @ 1 MHz
Ø Dissipation Factor0.009 @ 1 MHz
§ Thermo-MechanicalØ Tg = 220oC (TMA)Ø Modulus, 0.5 GPaØ ETB, 20%Ø Stress, 0-5 MPa
§ MoistureØ 0.14% (100% RH, 24 hrs, RT)
§ PhotodefinitionØ Negative Tone, Solvent DevelopØ Up to 50 µm thickØ 1:1 Aspect RatioØ 250-500 mJ/cm2
§ AdhesionØ Pressure Cooker (196 hours) on Si,
SiON, SixNy, SiO2, PI, Al & Cu No delamination and passes tape test
§ Top Layer MetalØ Cr/Cu & Ti/Cu
90º Peel = 4 lb/in
§ JEDEC Solder Reflow*
Ø Level 2A – PASS(60ºC/60% RH, 120 hours, 260ºC reflow 3x)
Ø Level 3 – PASS(30ºC/60% RH, 192 hours, 260ºC reflow 3x)
* 8 µm on 0.32 mm SiN wafer, 160ºC cure, SB-epoxy molding compound, 208 L QFP with Cu L/F, scanning acoustic microscope inspection
Processing
1. Plasma Pre-Treatment (O2:Ar) at 300 mTorr and 300 Watts for 30 seconds
2. Dehydration bake before coating is optional § 4 minutes at 250ºC is effective
3. Spin Coat Avatrel on wafer with a spread spin of 800 rpm for 8 seconds and Final Spin for 30 seconds to obtain final film thickness
4. Soft Bake at 120°C for 5 minutes5. I-Line UV Exposure with Adjusted Depth of Focus6. Post Exposure Bake at 100°C for 4 minutes7. Spray Develop for 30 seconds with limonene, Rinse with IPA for
10 seconds 5 second overlap and Spin Dry8. Cure at 160°C for 60 minutes
Typical process, but low T final cure
Formulation & Process Optimization: Overlapping process space for Al and Silicon Nitride
100
89
78
67
56
44
33
22
11
DepthOf
Focus(% Film
Thickness)
9008508007507006506005505004504003503002502001501005010 um
Via
365nm UV Exposure Dose (mJ/cm2)
Peeling on Al Good on Al Good on PE SiN Good on both
Imaging of 2195P
Imaging of Avatrel, 50 µm
Test Package
100 µm Vias150 µm Dicing
Lanes
Avatrel® PD Dielectric Polymer
Avatrel® PD Dielectric Polymer
Silicon Oxynitride
Silicon
Al
Imaging of Avatrel, 10 µmPrebake: 120ºC/5minExposure dose: 400mJ/cm2
PEB: 100ºC/4min
Bird’s-eye View Cross section
Magnification : x2000Magnification : x400
Curing: 160ºC/60min in N2Observation pattern: 40um via hole
Afterdeveloping
After curing
10 micron film
Reliability Testing of Avatrel
§ Sample Preparation– Silicon wafer coated with Avatrel or Non-photosensitive Polyimide, 5 µm thick– Substrate: FR5 with solder resist– Underfill: standard grade (CRP-4152R5) or new, low stress grade (CRP-X4498)– Post-cure 150ºC, 120 minutes
§ Treatment– JEDEC Level III
• Baking: 150ºC / 24 hours• Humidity: 30ºC / 60%RH / 192 hours• Reflow: 240ºC IR reflow 3 times
§ Reliability Testing– Thermal Cycling (T/C): 125ºC/30min ßà -55ºC/30 min (no interval), 200
cycles– Pressure Cooker Test (PCT): 125ºC/100%RH/2.3 atm, 96 hours
§ Evaluation by Scanning Acoustic Microscopy
Reliability Testing of Avatrel 2195P
100% Fail100% PassPCT
100% Pass100% PassT/C TestLow Modulus & Low Moisture Underfill(CRP-X4498)
100% Pass100% PassPCT
100% Pass100% PassT/C TestConventional Underfill(CRP-4152R5)
Non-photo PIAvatrel
Avatrel is compatible with standard and new, high reliability underfill materials
Major Factors Affecting Reliability
0
10
20
30
40
50
60
70
80
90
100
Modulus CTE Cure Temp Shrinkage Moisture
PIPBOAvatrel
2.8
GP
a
2.8
GP
a0.
5 G
Pa
150
-19
0 p
pm
/C
43 p
pm
50 p
pm
340º
C
340º
C16
0ºC
40%
40%
3%
1.5%
0.3%
0.14
% M
axim
um V
alue
Avatrel Development Activities
§ Sloped Sidewalls to facilitate conformal metalization and bumping processes§ Increased elongation and higher strength
versions under evaluation§ Aqueous Base developable versions are
underway
GT – “Polymer Pillars” Highly Compliant, Low Stress Approach
Polymer pillar
Metal interconnect
WG ElevatorPolymer WG
Mirror
Optical I/O Interconnection Electrical I/O Interconnection
Substrate
Chip
Solder
Single I/O structure functioning as both an electrical and optical interconnection
Grating Coupler
Avatrel Pillars…
63 x 325 µm
Avatrel Summary
§ Low Stress Materials focusing on stress buffer layers and redistribution
§ Early results indicate significantly improved reliability is possible§ 160°C final cure temperature is compatible with back end wafer
processing and post bump process steps§ Exceptionally low cure shrinkage§ Very good mechanical properties§ Very good photo definition in 5 to 50 µm thick films§ Good adhesion to all substrates§ Very low moisture absorption§ Highly tailorable – new versions are in development