AVANCE DX AQR ACB · 2018. 5. 24. · User Manual Version 003 BRUKER 7 (41) General 1 1 Overview 1.1 The ACB is designed to control up to eight amplifiers, using the SBS (Serial Bruker

AQR ACB

Amplifier Control BoardUser Manual

BRUKER

Version
003

The information in this manual may be altered without notice.

BRUKER accepts no responsibility for actions taken as a resultof use of this manual. BRUKER accepts no liability for anymistakes contained in the manual, leading to coincidentaldamage, whether during installation or operation of theinstrument. Unauthorised reproduction of manual contents,without written permission from the publishers, or translationinto another language, either in full or in part, is forbidden.

This manual was written by

G. Hiß

© February 4, 1997: Bruker Elektronik GmbH

Rheinstetten, Germany

P/N: Z31224DWG-Nr: 894003

Contents

Contents .............................................................. iii

Index ..................................................................... 5

1 General.................................................................... 71.1 Overview ............................................................................. 71.2 Layout ................................................................................. 81.3 Front panel .......................................................................... 91.4 Topology ........................................................................... 10

2 Installation ............................................................ 112.1 Jumpers ............................................................................ 112.2 Connections ...................................................................... 112.3 Part numbers ..................................................................... 12

3 Operation .............................................................. 133.1 Generating Display Data .................................................... 133.2 Linear Amplifier Commands ............................................... 133.3 TPD (Transmission Power Down) ...................................... 13

4 Hardware/Firmware............................................... 154.1 Hardware .......................................................................... 15

CPU1 & CPU2 ...............................................................15Decoder (PAL) ...............................................................15I²C E²Prom .....................................................................16Interfaces ......................................................................16

4.2 Firmware ........................................................................... 18Boot firmware (CPU1 & CPU2) .......................................18Application firmware ......................................................18

5 Connector Pinout.................................................. 195.1 Display Data Out ............................................................... 195.2 RS-232 .............................................................................. 205.3 SBS Master ....................................................................... 20

A PAL listings ........................................................ 23ACB0AB01-KE (PAL U18) ..............................................24ACB0AA02-KE (PAL U38) ..............................................25

B Schematics ......................................................... 27

User Manual Version 003 BRUKER iii

Contents

Figures ................................................................. 37

Tables .................................................................. 39

iv BRUKER User Manual Version 003

Index

A

Addressing .......................................................................................................... 10Application firmware............................................................................................ 18AQR .................................................................................................................... 11

B

BBIS ...................................................................................................................... 7Boot firmware ...................................................................................................... 18BSMS keyboard .................................................................................................. 13

C

Commands.......................................................................................................... 13

E

EPROM ......................................................................................................... 11, 15

F

Firmware ............................................................................................................. 18FLASH EPROM .................................................................................................. 15front panel ............................................................................................................. 9

I

Interface to the BSMS keyboard ......................................................................... 17

J

Jumpers .............................................................................................................. 11

M

Memory map ....................................................................................................... 16

P

PAL ..................................................................................................................... 23Part numbers....................................................................................................... 12PGMODE ............................................................................................................ 15Pinout .................................................................................................................. 19

User Manual Version 003 BRUKER 5 (41)

Index

R

RAM .................................................................................................................... 15RS-232 Interface ................................................................................................. 16RS-485 Interface ................................................................................................. 17

S

SBS ....................................................................................................................... 7Schematics.......................................................................................................... 27SCL ..................................................................................................................... 17SDA..................................................................................................................... 17SDIR.................................................................................................................... 17SPENAB.............................................................................................................. 13

T

terminate ............................................................................................................. 11Topology ............................................................................................................. 10TPD (Transmission Power Down)................................................................. 11, 13

6 (41) BRUKER User Manual Version 003

1General 1

Overview 1.1

The ACB is designed to control up to eight amplifiers, using the SBS (SerialBruker Spectrospin) protocol. It is the Interface between host computer (CCU)and the Bruker Linear Amplifiers (BLA).

Additionally the ACB prepares amplifier data for display on the BSMS keyboard.This display data contains, for each amplifier selected, forward and reflectedpower and a status byte. The display data can also be transferred via the RS232interface to the host computer for display on the computer monitor.

To perform a high refresh rate of the display data, the ACB is equipped with twoseparate micro controllers: one for data acquisition (CPU2) and the other (CPU1)for communication to the host computer.

Other features implemented on the ACB:

• Control of the Spectrometer Enable signal. The ACB turns off all selectedlinear amplifiers if the „Transmission Power Down“ button on the BSMSkeyboard is pressed.

• On board BBIS (Bruker Board Information System).

• External I2C bus, intended for communication with the BBIS of other AQRboards.


General

Layout 1.2

Figure 1.1. ACB top view

RS232 interface

FLASHEPROM

FLASHEPROM

AlternativeEPROM

AlternativeEPROM

EPROMRAM

RAM EPROM

SBS bus interface

µC80C515

CPU2

µC80C515

CPU1

interface to BSMS keyboard

DisplayData Out

Reset

RS-232(CCU)

SBSMaster


Front panel

Front panel 1.3

Figure 1.2. ACB front panel

+5V VCC

+5V PWR

+5V X

+5V VPI

DISPLAYDATA OUT

RESET

RS232-X32

SBS-MASTER

12

34

5

67

89

AQRECL 0x

ACB

12

34

56

78

91

0111

2131

415

12

34

56

78

91

0111

2131

415

Voltage control (all of +5V). The LED lights if the corresponding voltage value exceeds 4.5 Volt.

Display Data OutProvides the display data for the BSMS keyboard. It has a differential RS485 output.

Reset switch

RS-232 interface to the host computer (CCU)

SBS bus Interface to the linear amplifiers with RS485 levels


General

Topology 1.4

Figure 1.3. Topology ACB / Liner Amplifier (BLA)

The ACB can interface up to 8 amplifiers via the SBS bus. Addressing is doneusing the hex switches placed on the front panel of each amplifier. The sequencein which the amplifier addresses are set is unimportant for the ACB. However alladdresses must be different.

Amp 0

Amp 1

Amp 2

Amp 3

Amp 4

Amp 5

Amp 6

Amp 7

SBS busACBmaster slave

RS-232

bit streamCCU

BSMS


2Installation 2

Jumpers 2.1

Before placing the ACB into the AQR Rack check the jumper settings. If anEPROM with 32 kByte (27256) is used J4 and J8 should be set as shown below:

Figure 2.1. jumper settings

The other jumpers (J1, J2, J3, J5, J6, J7) are not needed for this specificoperation. If any of these jumper bases are present ensure that none is set.

Connections 2.2

The ACB must be situated in the AQR in the second slot from the right hand side.

• The ACB connector „RS232-X32“ is linked by the RS232 cable to a connectoron the serial interface board (SIB) of the host computer.

• The ACB connector „SBS-MASTER“ is linked by the SBS bus cable to theamplifiers (BLA). The end of the bus cable must be terminated.

• The link to the BSMS keyboard is done via the 15 pin cable (delivered with theBSMS). This cable must connect the ACB connector, „Display Data Out“, withthe BSMS CPU where the signals are brought through to the keyboardconnector on the BSMS CPU. It contains both the lines for display data and thelines for the two switches next to the display.

➪ IMPORTANT:

This cable must be attached before starting the spectrometer, otherwise severalboards in the AQR (ASU, Router) will be disabled and the ACB reacts as if theTPD (Transmission Power Down) button were pressed turning off all amplifierspresent.

27256

27512

J4

27256

27512

J8


Installation

Part numbers 2.3

Table 2.1. Part Numbers

ACB H5483

SBS Bus Cable H5624

RS232 cable HZ1482 (2m)

RS485 cable delivered with BSMS

SBS terminator H5167


3Operation 3

Generating Display Data 3.1

After starting up the system the ACB scans all possible addresses on the SBSbus for amplifiers present. This operation takes a few seconds. Next the hostcomputer requests the information about which amplifiers are present in thesystem, and starts an initialising sequence defining in the ACB which amplifiersare to be scanned and which amplifier’s data should be displayed on the BSMSkeyboard. Once this is done the ACB starts updating the BSMS keyboard display.

If a hard/software reset occurs the initialisation must be repeated.

Linear Amplifier Commands 3.2

If commands are to be given directly to the linear amplifiers the continuousscanning of the amplifiers must be interrupted. The ACB, therefore, contains aturn off command.

For application specific communication to the linear amplifiers the Multi ChannelCommands must be used.

Using the service features (downloading of new firmware, etc.) thecommunication occurs in the usual way by using the Device Identifier of thecorresponding linear amplifier.

TPD (Transmission Power Down) 3.3

A feature of the ACB is the control of the Spectrometer Enable Signal (!SPENAB).This line is present on the AQR back plane board and enables/disables particularAQR boards. Pressing the TPD button will cause the signal !SPENAB to goinactive (spectrometer disable) until the host computer reactivates it again with acommand, or a hard/software reset occurs.


Operation


4Hardware/Firmware 4

Hardware 4.1

The Hardware is divided to the following parts:

• CPU1 (communication)

• CPU2 (acquisition)

• external I2C bus

• RS232 Interface to host computer (galvanically isolated)

• RS485 Interface to linear amplifiers (galvanically isolated)

• Interface to the BSMS keyboard (galvanically isolated)

CPU1 & CPU2 4.1.1

The organisational structure of both CPUs is identical so that the description hereof CPU1 applies equally to CPU2.

The CPU is the micro controller 80C515AN from Siemens, clocked by a frequencyof 18 MHz. For memory there are three chips in use:

1. EPROM(U15, DIL base)

Either type 27C256 (32 kByte) or 27C512 (64 kByte) and contains the bootand download firmware.Alternatively to DIL the PLCC base (U17) can be used.

2. FLASH EPROM(U16, PLCC base)

Type: 27F256 (32 kByte)Contains the application firmware

3. RAM(U14, DIL)

Type: 62256 (32 kByte)

The use of Flash EPROMs enables new firmware to be downloaded withoutopening the unit, even by the customer.

Decoder (PAL) 4.1.2

The remainder of the PAL logic is used to decode the Memory section. Thememory map is dependant on the signal PGMODE (Program Mode) at Pin P1.7 ofthe micro controller.


Hardware/Firmware

I²C E²Prom 4.1.3

A serial E²Prom X24C16 (U22) with I2C bus-structure is used to store all BBIS(Bruker Board Information System) data. This chip is linked to both CPUs.

Interfaces 4.1.4

All interfaces are galvanically isolated from the CPUs. These are:

RS-232 Interface

The basic serial interface hardware is integrated in the 80C515AN. The data andhandshake lines are connected to port pins of the micro controller (U12) or to theseparate output port (U20). After the galvanic isolation the lines are brought toRS232 levels.

Table 4.1. Memory map

PGMODE EPROM FLASH RAM

0(applica-tion mode)

not mapped Code 0x000-0x7FFF

Data0x000-0x7FFF

1(boot mode

Code0x000-0x7FFF

Data0x000-0x7FFF

not mapped

Table 4.2. RS-232 interface

Signal name Meaning Sent by

!RxD receive data host computer

!TxD transmit data ACB

CTS clear to send host computer

RTS request to send ACB

DSR data set ready host computer

DTR data terminal ready ACB


Hardware

RS-485 Interface

Used for communication with the linear amplifiers.

Interface to the BSMS keyboard containing TPD

All signals have RS485 levels..

External I²C bus

This bus is used for access to serial E²PROMS placed on other boards in theAQR.

Table 4.3. RS-485 interface


RxD+RxD-

receive data pos.receive data neg.

amplifier

TxD+TxD-

transmit data pos.transmit data neg.

ACB

!WUP wake up line ACB

Table 4.4. interface to BSMS keyboard


DATA+DATA-

serial display datapos./neg.

ACB

CLOCK+CLOCK-

clock signalpos./neg.

ACB

STROBE+STROBE-

strobe signalpos./neg.

ACB

TOGGLE+TOGGLE-

toggle of power indicatorpos. /neg.

keyboard

TPD+TPD-

Transmission Power Downpos. /neg.

keyboard

Table 4.5. external I²C bus


SDA serial data bidirectional

SCL serial clock ACB

SDIR serial direction0 : transmit1 : receive

ACB


Hardware/Firmware

Firmware 4.2

Each CPU in the ACB contains two independent software modules; the bootfirmware and the application firmware.

Boot firmware (CPU1 & CPU2) 4.2.1

The boot firmware controls the reset sequence and the downloading of newfirmware releases. After initialisation, it checks if there is a valid applicationfirmware stored on the Flash EPROM. If all tests are good, it switches to theapplication program by driving pin PGMODE to low. This causes the memorydecoder to use the Flash EPROM as code memory and the RAM as datamemory. The application program can now run.

While the boot program is running, the memory decoder maps the PROM as codememory and the Flash EPROM as Data memory (only data memory can bewritten by micro controller). As RAM, only the internal memory of the microcontroller is used.

Application firmware 4.2.2

All application specific functions for the ACB are controlled by the applicationprogram. After the initialisation in both CPUs has been completed the programsrun their main loops executing the following program parts:

CPU1 (communication CPU, master)

main functions:

• Command interpreter for all SBS commands.

• CPU link to CPU2 for display data.

• CPU link to CPU2 for SBS commands.

• Conversion and transmission of display data to the BSMS keyboard.

• Storage of display data available, on request, to the host computer.

CPU2 (acquisition CPU, slave)

main functions:

• Command interpreter for all SBS commands via the CPU link.

• Polling of the amplifiers selected for forward and reflected power and theirstatus.


5Connector Pinout 5

Display Data Out 5.1

15 pin Mini-D female

Table 5.1. Pinout - Display Data Out

Pin No. Pin Name

1 PGND

2 -

3 DATA+

4 CLOCK+

5 STROBE+

6 TOGGLE+

7 TPD+

8 PGND

9 -

10 DATA-

11 CLOCK-

12 STROBE-

13 TOGGLE-

14 TPD-

15 +10V

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15


Connector Pinout

RS-232 5.2

9 pin Mini-D male

SBS Master 5.3

15 pin Mini-D female

Table 5.2. Pinout - RS232

Pin No. Pin Name

1 -

2 !RxD

3 !TxD

4 DTR

5 XGND

6 DSR

7 RTS

8 CTS

9 -

Table 5.3. Pinout - SBS Master

Pin No. Pin Name

1 DI_GND9V

2 RxD+

3 !WUP

4 TxD+

5 -

6 DI_GND9V

1 2 3 4 5

6 7 8 9

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15


SBS Master

7 DI_GND9V

8 DI_GND9V

9 RxD-

10 -

11 TxD-

12 -

13 DI_P9V

14 DI_P9V

15 DI_P9V

Table 5.3. Pinout - SBS Master

Pin No. Pin Name


Connector Pinout


APAL listings A

ACB0AB01-KE (PAL U18)

ACB0AA02-KE (PAL U38)


ACB0AB01-KE (PAL U18) A.0.1

*IDENTIFICATION ACB0AB01-KE 14.07.1993 CS:7128 Günther Hiß Bruker Elektronik GmbH

design function : - Generation of CS-signals for RAM, EPROM, FLASH and 74S138. - Realisation of a D-FlipFlop with asynchronous set/reset input to storage the signal !SPENABLE (TPD).

*X-NAMES HWRESET, PSEN,WR,RD,A[15..11], ! Address decoder PGMODE, ! Address decoder TPDDATA, ! Set/Reset FlipFlop with DATA TPDOWN,PALCLOCK; ! Spectrometer Enable FlipFlop

*Y-NAMES CSROM,CSRAM,CSFLASH, ! Address decoder WRFLASH,RDFLASH,CS138, ! Address decoder TPDNEG, ! Set 1 if TPD button is pressed TPDACTIVE, ! TPDNEG inverted RESET;

*FUNCTION-TABLE $(A[15..11]), PGMODE, PSEN : CSROM, CSFLASH, CSRAM, CS138; 0H..1FH , 1 , - : 0 , 0 , 1 , 1 ; 0H..1EH , 0 , - : 1 , 0 , 0 , 1 ; 1FH , 0 , 0 : 1 , 0 , 1 , 1 ; 1FH , 0 , 1 : 1 , 1 , 1 , 0 ; REST : 1 , 1 , 1 , 1 ;

$(A[15..11]), PGMODE, RD , WR , PSEN : RDFLASH, WRFLASH; 0H..1FH , 1 , 1 , 0 , 1 : 1 , 0 ; write flash D 0H..1FH , 1 , 0 , 1 , 1 : 0 , 1 ; read flash D 0H..1FH , 0 , 1 , 1 , 0 : 0 , 1 ; read flash C REST : 1 , 1 ;

*BOOLEAN-EQUATIONS RESET = HWRESET; TPDNEG := /TPDDATA; TPDNEG.RS = TPDOWN; TPDACTIVE = /TPDNEG;

*SPECIAL-FUNCTIONS TPDNEG.INV = NO; TPDNEG.REG = YES;

*RUN-CONTROL LISTING = PLOT, EQUATIONS, PINOUT, SYMBOLTABLE, NETTABLE; LONG; PROGFORMAT = JEDEC;

*PLD TYPE = AMPAL22V10;

*PIN PALCLOCK=1, TPDOWN=3, ! Inputs TPDDATA=14, HWRESET=2, PSEN=4, WR=5, RD=6, A11=7, A12=8, A13=9, A14=10, A15=11, PGMODE=13, RESET=23, ! Outputs CSROM=21, CSRAM=20, CSFLASH=19, WRFLASH=18, RDFLASH=17, CS138=16, TPDACTIVE=22, TPDNEG=15;

*END

1

2

3

4

5

6

7

8

9

10

11

12 13

14

15

16

17

18

19

20

21

22

23

24

!HWRESET

TPDOWN

!PSEN

!WR

!RD

AS11

AS12

AS13

AS14

AS15

GND

VCC

!RESET

TPDACTIVE

!CSROM

!CSRAM

!CSFLASH

!WRFLASH

!RDFLASH

!CS138

TPDATA

ID180FH

PAL 22V10

ACB0AB01-KE

PALCLOCK


ACB0AA02-KE (PAL U38) A.0.2

*IDENTIFICATION ACB0AA02-KE 14.07.1993 CS:2AA8 Günther Hiß Bruker Elektronik GmbH

design function : - Generation of CS-signals for RAM, EPROM and FLASH.

*X-NAMES PSEN,WR,RD,A[15..9], PGMODE;

*Y-NAMES CSROM,CSRAM,CSFLASH, WRFLASH,RDFLASH;

*FUNCTION-TABLE $(A[15..9]), PGMODE, PSEN : CSROM, CSFLASH, CSRAM; 0H..7FH , 1 , - : 0 , 0 , 1 ; 0H..7FH , 0 , - : 1 , 0 , 0 ; REST : 1 , 1 , 1 ;

$(A[15..9]), PGMODE, RD , WR , PSEN : RDFLASH, WRFLASH; 0H..7FH , 1 , 1 , 0 , 1 : 1 , 0 ; write flash D 0H..7FH , 1 , 0 , 1 , 1 : 0 , 1 ; read flash D 0H..7FH , 0 , 1 , 1 , 0 : 0 , 1 ; read flash C REST : 1 , 1 ;

*RUN-CONTROL LISTING = PLOT, EQUATIONS, PINOUT, SYMBOLTABLE, NETTABLE; LONG; PROGFORMAT = JEDEC;

*PLD TYPE = AMPAL18P8;

*PIN PSEN=1,WR=2,RD=3, A9=4,A10=5,A11=6,A12=7,A13=8,A14=9,A15=11, PGMODE=12, RDFLASH=15,WRFLASH=16, CSFLASH=17,CSRAM=18,CSROM=19;

*END

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20

!WR

!RD

A9

A10

A11

A12

A13

A14

GND

VCC

!CSROM

!CSRAM

!CSFLASH

!WRFLASH

!RDFLASH

PGMODE

A15

PAL 18P8

ACB0AA02-KE

!PSEN



BSchematics B

AQR Amplifier Control Board - Root

AQR Amplifier Control Board - RS232 Interfacep

AQR Amplifier Control Board - Bit Stream

AQR Amplifier Control Board - Power

AQR Amplifier Control Board - CPU1

AQR Amplifier Control Board - CPU2

AQR Amplifier Control Board - SBS-Bus

AQR Amplifier Control Board - Spare parts


Figure B

.1.A

CB

- Root

Date: November 10, 1993 Sheet 1 of 8

Size Document Number REV

B H3S101003 D

Title

AQR AMPLIFIER CONTROL BOARD (ROOT)

Engineer : G. HissPrint No. : H3P1983Print Part No. : H5489Board Part No. : H5483

BRUKER ELEKTRONIK GmbH

XD

NS

TXD

UP

DC /ADC

GALVANIC

ISOLATED

SBS PORT RS485

RXD

/ENTRANS

TXD

/WUP

TXD

SBS-PORT.SHE

RXD

/ENTRANS

/WUP

H3P1983C.SHE

28 (41)B

RU

KE

RU

ser Man

ual V

ersion

003

BIT-STREAM & POWER SUPPLY

/ADC

DATACLOCKSTROBE

I2SCLI2SEROUTI2SERINI2SDIR

TOGGLETPDOWNTPDACTIVE

I2SCL

AQR DISPLAY & LINEAR AMPLIFIER CONTROL BOARD

DATACLOCK

STROBE

I2SEROUTI2SERINI2SDIR

TOGGLETPDOWN

TPDACTIVE

GALVANIC

ISOLATED KEYBOARD

I2C-BUS

BSMS-

(TPD)

ADC

BIT-STR.SHE

/ADC

DATACLOCKSTROBE

TOGGLETPDOWNTPDACTIVE

CPU 1

X32 COMMUNICATION CPU

/SBS.STRB

CPU.SBS.[0..7]

SYSCLK

/ADC

/RESETSL

SCL.INTSDA.INT

/AMP.STRB

AMP.AD.[0..7]

DATACLOCKSTROBE

TOGGLE

/DSR.TTL/DTR.TTL

/RTS.TTL/CTS.TTL

RXD.TTLTXD.TTL


/E2P.STRB

TPDOWNTPDACTIVE /AMP.STRB

/ADC

CPU 2

ACQUISITION CPU

R

/ENTRA

/W

/A

/SBS.STRB

CPU.SBS.[0..7]

SYSCLK

/RESETSL

SDA.INTSCL.INT

/AMP.STRB

AMP.AD.[0..7]

/E2P.STRB

CPU.SBS.[0..7]

/SBS.STRB

AMP.AD.[0..7]I2SCLI2SEROUTI2SERINI2SDIR

RS232 TO X32

RXD.TTLTXD.TTL

/CTS.TTL/RTS.TTL

/DSR.TTL/DTR.TTL

GALVANIC

ISOLATED

RXD.TTLTXD.TTL

/CTS.TTL/RTS.TTL

/DSR.TTL/DTR.TTL

SYSCLK

/RESETSL

SCL.INTSDA.INT/E2P.STRB

SPARE PARTS

CPU2.SHECPU1.SHEPORTX32.SHE

H2

HOLE28

H1

HOLE28

H3

HOLE28

SPARE.SHE

Figure B

.2.A

CB

- RS

232 Interface



B H3S101013 D

Title

AQR AMPLIFIER CONTROL BOARD (RS232)



1 2

U5A

74LS07

TP6

3 4

U5B

74LS07

TP7

TXD.TTL

/RTS.TTL

/DTR.TTL 5 6

U5C

74LS07

TP8

TXD.TTL

/RTS.TTL

/DTR.TTL

TP9

RXD.TTL

/CTS.TTL

/DSR.TTL

TP10

RXD.TTL

/CTS.TTL

/DSR.TTL

TP11

PORTX32.SHE

User M

anu

al Versio

n 003

BR

UK

ER

29 (41)

1 2IR5A

4x470R

VCC

LIGHT -> LOW

1

2 7

5

8U24A

HCPL-2630

1 2IR6A

5x3k3

+5VEX+5VEX

RS232 CONNECTION TO X32

+5VEX

C1+ 10

C2+13

T2IN 18

T3IN19

T4IN21

C1- 12

C2- 14

T1IN 5T1OUT 2

T2OUT 1

T3OUT 24

T4OUT 20

V+ 11

V- 15

GND

8

VCC

9

R1OUT 6

R2OUT 4

R3OUT 22

R4OUT 17

R1IN 7

R2IN 3

R3IN 23

R4IN 16

U23

MAX238_SP

C44

1u

+5VEX

C341u

4

3 6

U24B

HCPL-2630

3 4IR6B

5x3k3

+5VEX

HPCL-2731

3 4IR5B

4x470R

VCC

HPCL-2731

R21

330R

VCC

1

2 8

7U28A

MCT6

R19

3k3

+5VEXC331u

C43

1u

RTS.X32DTR.X32

/TXD.X32

/RXD.X32

(Signal Ground)

(RXD)

(TXD)

(DTR)(CTS)

(RTS)

(DSR)

5 9 4 8 3 7 2 6 1

X2

MINI D 9PIN MALE H

DSR.X32

RTS.X32

CTS.X32DTR.X32

/RXD.X32

/TXD.X32

CTS.X32DSR.X32

1

27

5

8U27A

HCPL-2630

5 6IR5C

4x470R

+5VEX

+5VEX 5 6

IR6C

5x3k3

VCCVCC

HPCL-2731

7 8IR6D

5x3k3

VCC

4

36

U27B

HCPL-2630

7 8IR5D

4x470R

+5VEX

1 2

14

7

U26A

74LS07SPC37100n

C321u

+5VEX

3 4

U26B

74LS07SP

5 6

U26C

74LS07SP

4

3 5

6U28B

MCT6

R20

330R

+5VEX

HPCL-2731

R22

3k3

VCC

GB3GND BRIDGE

C38100n

C42100n

C3510u

+5VEXC8

100n

C1010u

VCCC45

100n

Figure B

.3.A

CB

- bit stream to B

SM

S-keyboard



B H3S101023 D

Title

AQR AMPLIFIER CONTROL BOARD (BIT-STREAM)



BSMSKEYBOARD

1 9 2 10 3 11 4 12 5 13 6 14 7 15 8

X1

MINI D 15PIN FEMALE H

N.C.N.C.

DATA-DATA+CLOCK-CLOCK+STROBE-STROBE+TOGGLE-TOGGLE+TPD-TPD+

+10VB

R31330R

VCC

POWER CONNECTION

ADCONGND

/SPENAB

SPENABGND


ADCON

-20mA

1

2 8

7U49A

MCT6

/SPENAB

SPENABGND

TO CPU1

WN

TPDACTIVE

ADCON

ADCONGND

BIT-STR.SHE

POW-CON.SHE



D5LED 3MMGREENH SAG

140R

30 (41)B

RU

KE

RU

ser Man

ual V

ersion

003

DATA+

R4

120R

KEYBOARD CONNECTION

4 16 8

1

7

2 3 6 5

U1A

75174

VPIPUG0

PUG2

VPI

1

27

5

8U4A

HCPL-2630

1 2IR1A

4x470R

9 8

U5D

74LS07

VCC

TP1

DATA

TP2

CLOCK

4

36

U4B

HCPL-2630

3 4IR1B

4x470R

11 10

U5E

74LS07

VCC

HCPL-2731

HCPL-2731

PUG3

DATA+DATA-CLOCK+CLOCK-

R5

120R

DATA-

CLOCK+

CLOCK-

STROBE+

STROBE-

R12

120R

12

9

15

10111413

U1B

75174

STROBE+STROBE-

HCPL-2731

PUG1

PUG4

PUG5

VPI

1

27

5

8U6A

HCPL-2630

5 6IR1C

4x470R

13 12

U5F

74LS07

4

36

U6B

HCPL-2630

VCC

TP3

STROBE

SPARE PART

VPI

HCPL-2731

VPIR6240R

VPI

R9240R

VPI

4

3 5

6U49B

MCT6R27

330R

TPDO

R11240R

R10120R

4

3

2

1

6

7

8

5

U375176

TPD+

TPD-

R8240R

R7120R

TOGGLE-

TOGGLE+

4

3

2

1

6

7

8

5

U2

75176HCPL-2731

7

8IR1D4x470R

R23k3

1

2 7

5

8U7A

HCPL-2630

VCCTP4

TOGGLE TOGGLE

VCC

TP5

/ADC /ADC

VCC

HCPL-2731

R33k3

4

3 6

U7B

HCPL-2630

R1390R

D11N4148

ADCON

ADCONGND

VPI

VPIVPI

TP31

R233k3

SIN 7

RSIN 2

VREF 1

CT 3

RES 6

RES 5

GND 4

VCC 8

U29

TL7705_SP

VPIVPID6

1N4148

D71N4148C16

1u

VPI

VI 1GND

2

VO 3

U87805

TO220_7K!!TO220_7_K

C1510u

+10VB

C5100n

VPIVCC

2 3 4 5 6 7 8 9

1IR2

8x3k3

PUG0PUG1PUG2PUG3PUG4PUG5

C3100n

C4100n

C6100n

C1100n

C2100n

C710u

GB1GND BRIDGE

VPI

HEATSINK

C39CAP SAL2u2

C46100n

R39

Figure B

.4.A

CB

- power supply



B H3S101033 D

Title

AQR AMPLIFIER CONTROL BOARD (POWER SUPPLY)



G.I. X32

GENERAL SUPPLY

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16

X6

VG48A MALE H

SDASDIR

+9VX

VCC

WRGND

+12V ADCON/SPENAB

-12VNOT USED (-12V)

FLASH EPROM

G.I. I2C-BUS & AMP

G.I. X32

GENERAL SUPPLY

FLASH EPROM

B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16

X5

VG48B MALE H

ADCONGNDSPENABGND

+9VX

VCC

+12V

WRGND

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16

X4

VG48C MALE H

+9VX

-12VNOT USED (-12V)

G.I. X32

G.I. I2C-BUS & AMP

GENERAL SUPPLY

NOT USED (-12V)

FLASH EPROM

SCLI2CGND

VCC

-12V

+12V

WRGND

TP30

C7310u

TP34

+12V

G.I. I2C-BUS & AMP

C7610u

TP35

+9VPWR

POW-CON.SHE

C75100n

FLASH EPROM G.I. OF POWER AMPLIFIER(BLA & I2C-BUS)

C74100n

C67100n

720n

User M

anu

al Versio

n 003

BR

UK

ER

31 (41)

SCL

R322k2

+5VPWR

1 2 3

14

7

U50A

74HC125SP

PD0

+5VPWR

+5VPWR

1

27

5

8U48A

HCPL-2630

1 2IR14A

5x3k3

+5VPWR

1 2

U47A

74LS07

1 2IR12A

4x470R

VCC

POWER SUPPLY

I2SCL I2SCL

I2SEROUT I2SEROUT 3 4

U47B

74LS07

5 6IR12C

4x470R

VCC

HCPL-2731

HCPL-2731

4

36

U48B

HCPL-2630

3 4IR14B

5x3k3 4 5 6

U50B

74HC125SP

+5VPWRR332k2

+5VPWR

VPSDA

+9VPWR

SDIR

PD11312 11

U50D

74HC125SP

10 9 8

U50C

74HC125SP

PD2

HCPL-2731

3 4IR12B

4x470R

+5VPWR

VCC

4

3 6

U42B

HCPL-2630

7 8IR14D

5x3k3

VCC

I2SERIN I2SERIN

I2SDIR I2SDIR 5 6

U47C

74LS07

7 8IR12D

4x470R

VCC

HCPL-2731+5VPWR

5 6IR14C

5x3k3 4

36

U46B

HCPL-2630

+5VPWR

23456789

1

IR15

8x1k

PD0PD1

I2CGND

VP

+9VPWR

+9VPWR

PD2

GB5GND BRIDGE

TP21/SPENAB

SPENABGND

ADCON

ADCONGND

/SPENAB

SPENABGND

ADCON

ADCONGND

R253k3

C48

100nC41CAP SAL2u2

+5VEX+5VEX D4LED 3MMGREENH SAG

R16390R

SIN 7

RSIN 2

VREF 1

CT 3

RES 6

RES 5

GND 4

VCC 8U31

TL7705_SP

+5VEX+5VEX

R243k3

C47

100nC40CAP SAL2u2

+5VPWR

SIN 7

RSIN 2

VREF 1

CT 3

RES 6

RES 5

GND 4

VCC 8U30

TL7705_SP

+5VPWR

+5VPWR

D3LED 3MMGREENH SAG

R15390R

+5VPWRVP

C6410u

VCC

GENERAL SUPPLYTP33

+5VPWR

C191u

D91N4148

D8

1N4148

VI 1

GND

2

VO 3

U97805

TO220_7K!!TO220_7_K

C1710u

+9VPWRD11

1N4148

D101N4148C54

1u

TP32

+5VEX

C5310u

VI 1

GND

2

VO 3

U327805

TR220_7!!TR220_7

+9VX

+5V FOR G.I. OF RS232 TO X32

NO HEATSINK

C56100n

(0.4W) HEATSINK

C18100n

+5V FOR G.I. OF I2C-BUSAND G.I. OF B-LAX

VCC C70100n

C71100n

C10

+5VPWR

Figure B

.5.A

CB

- CP

U1



B H3S101043 D

Title

AQR AMPLIFIER CONTROL BOARD (CPU1)



A0 12

A1 11

A2 10

A3 9

A4 8

A5 7

A6 6

A7 5

A8 27

A9 26

A10 23

A11 25

A12 4

A13 28

A14 29

DQ0 13

DQ1 14

DQ2 15

DQ3 17

DQ4 18

DQ5 19

DQ6 20

DQ7 21

A15 3

WE 31

OE 24

CE 22

VPP 1NC 2

NC 30

U16

28F512 PLCC

DS0DS1DS2DS3DS4DS5DS6

AS0AS1AS2AS3AS4AS5AS6


0 11

1 12

2 13

3 15

4 16

5 17

6 18

7 19 AS7AS8AS9AS10AS11AS12AS13AS14AS15

DS7

/WRFLASH/RDFLASH/CSFLASH

DS7

FLASH

PU1

TESTPIN1

BOOT-JUMPER

1 2J1

+12VRAM

DS0DS1DS2DS3DS4DS5DS6DS7

TP18

I1/CLK 1

I2 2

I3 3

I4 4

I5 5

I6 6

I7 7

I8 8

I9 9

I10 10

I11 11

I12 13

O123

O222

O321

O420

O519

O618

O717

O8 16

O10 14O9 15

U18

22V10

1 2J3

/PSEN/WR

/HWRESETTPDOWN

PALCLOCK

/CSROM

PU2

TESTPIN2

/RESETTPDACTIVE

(inp.)

/CSRAM/CSFLASH/WRFLASH/RDFLASH/CS138

TPDDATA

TP17 1 2J2

AS11AS12AS13AS14AS15

/RD

PGMODEVCC

R13390R

PGMODE-JUMPER

1 2

6 4 5

151413121110 9

3

7

U19

74S138

TPDACTIVEPU5

4

5 6

U21B

74HC32

PORT62

CPU1.SHE

(74AS138 8.5ns)

/CSDATA/CSCLOCK/CSSTROB/CSPORT7/CS_SDIR

11ns

/CS138

PU6

/WR

AS0AS1AS2

NT

NT

32 (41)B

RU

KE

RU

ser Man

ual V

ersion

003

A0 10

A1 9

A2 8

A3 7

A4 6

A5 5

A6 4

A7 3

A8 25

A9 24

A10 21

A11 23

A12 2

A14 1

CS 20

WE 27

DDDDDDDD

OE 22

A13 26

U14

62256


A0 11

A1 10

A2 9

A3 8

A4 7

A5 6

A6 5

A7 4

A8 29

A9 28

A10 24

A11 27

A12 3

A13 30

A14 31

O0 13

O1 14

O2 15

O3 18

O4 19

O5 20

O6 21

O7 22

OE 25

CE 23

A15 2

U17

27512 PLCC



DS[0..7] 4 3 2 1

5

6

U11A

74HC74

10111213

9

8

U11B

74HC74

DS0/CSDATA

PU7

PU8

/HWRESET

BIT-STREAM

TP27

TP26

DATA

CLOCK

DATA

CLOCK

CPU1

I2-BUS

I2SCL I2SCL

CPU COMMUNICATION

I2SEROUT

I2SERIN

I2SDIR

I2SEROUT

I2SERIN

I2SDIR TP29

TP28 STROBE

TOGGLE

STROBE

4 3 2 1

5

6

U10A

74HC74

DS1

DS2

/CSCLOCK

/CSSTROB

PU9

/HWRESET

/HWRESET

AS7AS8AS9AS10AS11AS12AS13AS14

/CSROM/PSEN

ASJ15

DS7 AS7AS8AS9AS10AS11AS12AS13AS14

/CSRAM/WR/RD

A0 10

A1 9

A2 8

A3 7

A4 6

A5 5

A6 4

A7 3

A8 25

A9 24

A10 21

A11 23

A12 2

A13 26

A14 27

A15 1

CE 20

OE 22

O011

O112

O213

O315

O416

O517

O618

O719

U15

27512

AS[0..4]

EPROM

2725627512

1 2 3

J4

AS0

AS15

PU3

ASJ15

TOGGLE

AN0/P6.0 20

AN1/P6.1 19

AN2/P6.2 18

AN3/P6.3 17

AN4/P6.4 16

AN5/P6.5 15

AN6/P6.6 14

AN7/P6.7 13

P4.0/ADST 1

P4.1 2

P4.2 3

P4.3 5

P4.4 6

P4.5 7

P4.6 8

P4.7 9

P5.0 67

P5.1 66

P5.2 65

P5.3 64

P5.4 63

P5.5 62

P5.6 61

P5.7 60

XTAL1 40

XTAL2 39

PE/SWD 4

VAREF 11

VAGND 12

RESET 10

EA 51

INT3/P1.036

INT4/P1.135

INT5/P1.234

INT6/P1.333

INT2/P1.432

T2EX/P1.531

CLKOUT/P1.630

T2/P1.729

AD0/P0.052

AD1/P0.153

AD2/P0.254

AD3/P0.355

AD4/P0.456

AD5/P0.557

AD6/P0.658

AD7/P0.759

A8/P2.0 41

A9/P2.1 42

A10/P2.2 43

A11/P2.3 44

A12/P2.4 45

A13/P2.5 46

A14/P2.6 47

A15/P2.7 48

RXD/P3.0 21

TXD/P3.1 22

INT0/P3.2 23

INT1/P3.3 24

T0/P3.4 25

T1/P3.5 26

WR/P3.6 27

RD/P3.7 28

PSEN 49

ALE 50

VCC-VBB

37

GND

38

HWPD/VCC 68

U12

80C515A

CPU.SBS.[0..7]

/AMP.STRB

/SBS.STRB

AMP.AD.[0..7] VCC

TP15

TP13 /AMP.STRB

/SBS.STRB

AMP.AD.[0..7]

CPU.SBS.[0..7]

/ADC

TPDOWN

TESTPIN1TESTPIN2

/ADC

AMP.AD.0AMP.AD.1AMP.AD.2AMP.AD.3

/RTS.TTL/DTR.TTLTPDOWN

PORT62

DS0DS1DS2DS3

/AMP.STRB/SBS.STRB

TOGGLEI2SCLI2SEROUTI2SERIN

/E2P.STRB

PGMODE 1 11

2 3 4 5 6 7 8 9

1918171615141312

U1374HC573

DS0DS1DS2DS3

ALE

AS0AS1AS2AS3

AS1AS2AS3AS4AS5AS6AS7AS8AS9AS10AS11AS12AS13

D2LED 3MM

GREENH SAG

VCC

AS4AS5AS6AS7


AS14

/CSROM/PSEN

ASJ15DS4DS5DS6DS7

DS4DS5DS6DS7


CPU.SBS.0CPU.SBS.1CPU.SBS.2CPU.SBS.3CPU.SBS.4CPU.SBS.5CPU.SBS.6


8Q1

12MHz

TP19

SYSCLK

SYSCLK

CPU.SBS.7

/HWRESET

N.C.

VCC /WR/RD

/PSENALE

AS15

RXD.TTLTXD.TTL/CTS.TTL/DSR.TTLSCL.INTSDA.INT

23456789

1IR7

8x3k3

/AMP.STRB/SBS.STRB

/E2P.STRB/CSDATA/CSCLOCK/CSSTROB/CSPORT7/CS_SDIR

VCC

C30CAP VAX

100n

2 3

1

SW1AS15 PU4

SIN 7

RSIN 2

VREF 1

CT 3

RES 6

RES 5

U25

TL7705C31CAP SAL2u2

EEPROM

A0 1

A1 2

A2 3

WC 7

SCL 6

SDA 5

U22

X24C02

I2SDIR 10 11 12 13

9

8

U10B

74HC74

DS3

PU10

/CS_SDIR/HWRESET

111

2 3 4 5 6 7 8 9

19 18 17 16 15 14 13 12

U20

74HC574

/CSPORT7

RXD.TTL

/CTS.TTL

/DSR.TTL

/RTS.TTL

/DTR.TTL

TXD.TTL

RXD.TTLTXD.TTL

/CTS.TTL

/DSR.TTL

/RTS.TTL

/DTR.TTL

23456789

1IR4

8x3k3

23456789

1IR3

8x3k3

PU3PU4PU5

PU1PU2

PU6PU7PU8

VCC VCC/RTS.TTL/DTR.TTL

/RESETSLDATACLOCKSTROBETOGGLE

PU9PU10

TPDOWN

TPDDATAPALCLOCK

PALCLOCK

PORT7

/RESETSL

DS0DS1DS2DS3DS4DS5DS6DS7

TP12

TP14

SDA.INT

SCL.INT

VCCR172k2

R182k2

TP16

SDA.I

SCL.I

/E2P.STRB/E2P.STRB

Figure B

.6.A

CB

- CP

U2



B H3S101053 D

Title

AQR AMPLIFIER CONTROL BOARD (CPU2)



A0 10

A1 9

A2 8

A3 7

A4 6

A5 5

A6 4

A7 3

A8 25

A9 24

A10 21

A11 23

A12 2

A14 1

CS 20

WE 27

D0 11

D1 12

D2 13

D3 15

D4 16

D5 17

D6 18

D7 19

OE 22

A13 26

U35

62256

D0D1D2D3D4

A0A1A2

A4A3

D0D1D2D3D4

DQ0 13

DQ1 14

DQ2 15

DQ3 17

DQ4 18

DQ5 19

DQ6 20

DQ7 21

NC 2

NC30

LCC

A5A6A7A8A9A10A11A12A13A14

D5D6D7

/CSRAM/WR

D5D6D7

RAM

A0 10

A1 9

A2 8

A3 7

A4 6

A5 5

A6 4

A7 3

A8 25

A9 24

A10 21

A11 23

A12 2

A13 26

A14 27

A15 1

CE 20

OE 22

O011

O112

O213

O315

O416

O517

O618

O719

U36

27512

D0D1D2

D0D1D2

/RD

D[0..7]

A0A1A2

O013

O114

O215

O318

O419

O520

O621

O722

C

D3D4D5D6D7

A4A5A6A7A8A9A10A11A12A13A14

A3

AJ15

D3D4D5D6D7

EPROM

/CSROM/PSEN

0

O1 19

O2 18

O3 17

O4 16

O5 15

O6 14

O7 13

O8 12

8

P8

RXDTXD

/ENTRANS/WUP

/CSRAM/CSFLASH

/CSROM

/WRFLASH/RDFLASH

SBS

23456789

1IR8

8x3k3

RXDTXD

/ENTRANS/WUP

PU1PU2

VCC

CPU2.SHE

PU3PU4PU5

inp

TP20PGMODE

1 2J6

C49100n

User M

anu

al Versio

n 003

BR

UK

ER

33 (41)

A0 12

A1 11

A2 10

A3 9

A4 8

A5 7

A6 6

A7 5

A8 27

A9 26

A10 23

A11 25

A12 4

A13 28

A14 29

A15 3

WE 31

OE 24

CE 22

VPP 1

U37

28F512 P

A0A1A2

A4A3

2 3 4 5 6 7 8 9

1IR9

8x3k3

VCC

2 3 4 5 6 7 8 9

1IR10

8x3k3

CPU.SBS.0CPU.SBS.1CPU.SBS.2CPU.SBS.3

VCC


1 2J5

JUMPER2

TESTPIN1

PU1

CPU2

CPU.SBS.[0..7]

/SBS.STRB

AMP.AD.[0..7]

/AMP.STRB

/SBS.STRB

/AMP.STRB

1 2J7

JUMPER2

PU2

TESTPIN2

AMP.AD.[0..7]

CPU.SBS.[0..7]


VCC

CPU.SBS.4CPU.SBS.5CPU.SBS.6CPU.SBS.7

1 11

2 3 4 5 6 7 8 9

1918171615141312

U34

74HC573

A5A6A7A8A9A10A11A12A13A14A15

/WRFLASH

FLASH

A0 11

A1 10

A2 9

A3 8

A4 7

A5 6

A6 5

A7 4

A8 29

A9 28

A10 24

A11 27

A12 3

A13 30

A14 31

OE 25

CE 23

A15 2

U39

27512 PLC

A0A1A2

/CSFLASH/RDFLASH

+12VA0A1A2A3A4A5A6A7

D0

ALE

D0D1D2D3

D5D6D7

D4

PGMODE

/SBS.STRB/AMP.STRB/E2P.STRB

AN0/P6.0 20

AN1/P6.1 19

AN2/P6.2 18

AN3/P6.3 17

AN4/P6.4 16

AN5/P6.5 15

AN6/P6.6 14

AN7/P6.7 13

P4.0/ADST 1

P4.1 2

P4.2 3

P4.3 5

P4.4 6

P4.5 7

P4.6 8

P4.7 9

P5.0 67

P5.1 66

P5.2 65

P5.3 64

P5.4 63

P5.5 62

P5.6 61

P5.7 60

XTAL1 40

XTAL2 39

PE/SWD 4

VAREF 11

VAGND 12

RESET 10

EA 51

INT3/P1.036

INT4/P1.135

INT5/P1.234

INT6/P1.333

INT2/P1.432

T2EX/P1.531

CLKOUT/P1.630

T2/P1.729

AD0/P0.052

AD1/P0.153

AD2/P0.254

AD3/P0.355

AD4/P0.456

AD5/P0.557

AD6/P0.658

AD7/P0.759

A8/P2.041

A9/P2.142

A10/P2.243

A11/P2.344

A12/P2.445

A13/P2.546

A14/P2.647

A15/P2.748

RXD/P3.0 21

TXD/P3.1 22

INT0/P3.2 23

INT1/P3.3 24

T0/P3.4 25

T1/P3.5 26

WR/P3.6 27

RD/P3.7 28

PSEN 49

ALE 50

VCC-VBB

37

GND

38

HWPD/VCC 68

U33

80C515A

TESTPIN1

/ADC

TESTPIN2

AMP.AD.0

/ADC

CPU.SBS.0CPU.SBS.1CPU.SBS.2CPU.SBS.3CPU.SBS.4

AMP.AD.1AMP.AD.2AMP.AD.3AMP.AD.4AMP.AD.5AMP.AD.6AMP.AD.7

D1D2D3

D5D6D7

D4

A8A9A10A11A12

A8A9A10A11A12

A4A5A6A7A8A9A10A11A12A13A14

A3

AJ15

2725627512

1 2 3

J8

/CSROM/PSEN

PU3

A15AJ15

A13A14A15

/RD/WR

RXDTXD

/ENTRANS

A13A14A15

/WUP

SCL.INTSDA.INT

N.C.

SYSCLK

CPU.SBS.5CPU.SBS.6CPU.SBS.7

VCC

SYSCLK

/RESETSL

PU4VCC

SIN 7

RSIN 2

VREF 1

CT 3

RES 6

RES 5

U40

TL7705

/RESET

SDA.INT SDA.INT TP22

ALE/PSEN

TP23

TP24

TP25

I1 1

I2 2

I3 3

I4 4

I5 5

I6 6

I7 7

I8 8

I9 9

I1 11

U3

18

/PSEN/WR/RD

A10A9

A11A12A13A14A15

SCL.INT

/E2P.STRB

SCL.INT

/E2P.STRB

PU5

C58CAP VAX

100n

C59CAP SAL2u2

C3610u

C910u

GB4GND BRIDGE

VCC

BLOCK CAPACITIES CPU1

C14100n

C13100n

C12100n

C22100n

C23100n

C11100n

C20100n

C26100n

C29100n

C25100n

C28100n

C24100n

C21100n

C27100n

BLOCK CAPACITIES CPU2

C57100n

C52100n

C6110u

VCCC51

100nC50

100nC55

100nC60

100n

Figure B

.7.A

CB

- SB

S Interface to B

LA-C

ontroller



B H3S101063 D

Title

AQR AMPLIFIER CONTROL BOARD (BLA)



BLA CONTROLLER

1 9 2 10 3 11 4 12 5 13 6 14 7 15 8

X3

MINI D 15PIN FEMALE H

TXD+

+9VPWR

RXD+RXD-

TXD-/WUP.POW

SBS-PORT.SHE

34 (41)B

RU

KE

RU

ser Man

ual V

ersion

003

RS485 CONNECTION TO BLA

TXD 9 8

U47D

74LS07

TXD

1

27

5

8U43A

HCPL-2630

1 2IR11A

4x470R

+5VPWRVCC

1 2IR13A

5x3k3

+5VPWR

4

3

2

1

6

7

8

5

U41

75176

TXD+

+5VPWR

R26120R

1 2 3

14

7

U44A

74HC125SP

TXD-

+5VPWR

3 4IR13B

5x3k3

5 6IR13C

5x3k3

+5VPWR

+5VPWR

4

36

U43B

HCPL-2630

3 4IR11B

4x470R

5 6IR11C

4x470R

+5VPWR

VCC

VCC

11 10

U47E

74LS07

/ENTRANS /ENTRANS

/WUP /WUP 13 12

U47F

74LS07

1

27

5

8U46A

HCPL-2630

4

3

2

1

6

7

8

5

U45

75176

+5VPWRR30240R

+5VPWR

R29120R

R28240R

RXD+

RXD- 7 8

IR11D

4x470R

+5VPWR

1

2 7

5

8U42A

HCPL-2630

7 8IR13D

5x3k3

VCC

RXD

VCC

RXD

C68100n

C65100n

C66100n

C63100n

C69100n

GB6GND BRIDGE

+5VPWRC62100n

VCC

GB2GND BRIDGE

Figure B

.8.A

CB

- spare parts



B H3S101073 D

Title

AQR AMPLIFIER CONTROL BOARD (SPARE PARTS)



PARTS

AGNDY

2.SHE

EVICES ON SHEET:

IR6ERES PACK55x3k3

PARTS

, AGND

EVICES ON SHEET:

RT.SHE

E PACK53

SPARE.SHE

User M

anu

al Versio

n 003

BR

UK

ER

35 (41)

9 8

U26D

74LS07SP

9

10 8

U21C

74HC32

1

2 3

U21A

74HC32

SPARE PARTS

VCC, DGND

CPU1.SHE

USED DEVICES ON SHEET:

11 10

U26E

74LS07SP

SPARE

+5VEX,

PORTX3

USED D

9

10

13 12

U26F

74LS07SP

12

1311

U21D

74HC32

SPARE

+5VPWR

USED D

4 5 6

U44B

74HC125SP

10 9 8

U44C

74HC125SP

13 12 11

U44D

74HC125SP

SBS-PO

9

10

IR13RES5x3k

SPARE PARTS

POW-CON.SHE

USED DEVICES ON SHEET:

9

10

IR14ERES PACK55x3k3


Figures

1 General 7Figure 1.1. ACB top view ........................................................................8Figure 1.2. ACB front panel .....................................................................9Figure 1.3. Topology ACB / Liner Amplifier (BLA) ..................................10

2 Installation 11Figure 2.1. jumper settings ....................................................................11

3 Operation 13

4 Hardware/Firmware 15

5 Connector Pinout 19


Figures


Tables

1 General 7

2 Installation 11Table 2.1. Part Numbers ................................................................ 12

3 Operation 13

4 Hardware/Firmware 15Table 4.1. Memory map .................................................................. 16Table 4.2. RS-232 interface ............................................................ 16Table 4.3. RS-485 interface ............................................................ 17Table 4.4. interface to BSMS keyboard ........................................... 17Table 4.5. external I²C bus .............................................................. 17

5 Connector Pinout 19Table 5.1. Pinout - Display Data Out .............................................. 19Table 5.2. Pinout - RS232 .............................................................. 20Table 5.3. Pinout - SBS Master ...................................................... 20


Tables



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AVANCE DX AQR ACB · 2018. 5. 24. · User Manual Version 003 BRUKER 7 (41) General 1 1 Overview 1.1 The ACB is designed to control up to eight amplifiers, using the SBS (Serial Bruker