Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis

http://csrl.kjist.ac.kr

DIC at KJIST 1 Oryong-dong Buk-gu, Kwangju 500-712, South Korea

Concurrent Systems Research Laboratory

Automatic Process-Oriented Control Automatic Process-Oriented Control Circuit Generation for Asynchronous Circuit Generation for Asynchronous

High-Level SynthesisHigh-Level Synthesis

Department of Information and Communications at K-JISTApril 5th, 2000

speaker : Euiseok Kim

ASYNC’2000 ASYNC’2000

( slide 2 )ASYNC’2000ASYNC’2000 Apr. 5 , 2000

ContentsContents

1.1. IntroductionIntroduction

2.2. PreliminariesPreliminaries

3.3. Approaches to Control Circuit GenerationApproaches to Control Circuit Generation

4.4. Controller Generation for CDFGController Generation for CDFG

5.5. Timing ConstrainsTiming Constrains

6.6. Experimental ResultsExperimental Results

7.7. ConclusionConclusion



1. Introduction1. Introduction

• Asynchronous system design styleAsynchronous system design style becomes popular.

• Existing CAD toolsExisting CAD tools are restricted to synchronous system dessynchronous system designign.

• ACAD toolsACAD tools are restricted to logic synthesislogic synthesis.

• UnwieldyUnwieldy to conceiveconceive and design controllers manuallydesign controllers manually.

In order to overcome above problems, automaticautomatic process-orientedprocess-oriented controller generation method from CDFGCDFG is presented as a part of an AHLSAHLS.

In order to overcome above problems, automaticautomatic process-orientedprocess-oriented controller generation method from CDFGCDFG is presented as a part of an AHLSAHLS.



2. Preliminaries2. Preliminaries

DFG-UNITDFG-UNITDFG-UNITDFG-UNIT Control Dataflow GraphControl Dataflow GraphControl Dataflow GraphControl Dataflow Graph

DFG-Unit 1DFG-Unit 1

ifif0 0

1 1

DFG-DFG-UnitUnit

endifendif

DFG-UnitDFG-Unit

whilewhile0 0

1 1

CDFG-Unit CDFG-Unit 22

ChildChild

BlockBlock

OP1OP1 OP2OP2

OP3OP3 OP4OP4

ALU1

++ALU

2

++

ALU2

++ALU

1

++

R1R1

R2R2 R3R3

R2R2 R3R3

R2R2 R3R3 R4R4

DFG-Unit DFG-Unit 33

++ ++

++ ++

COND COND NodeNode



3. Approaches to Control Circuit 3. Approaches to Control Circuit Generation - IGeneration - I

• Centralized ControllerCentralized Controller

- unsuitableunsuitable to asynchronous

system style

- may suffer from lossloss of parallelism,parallelism,

difficult hazard-free difficult hazard-free synthesissynthesis

and rapid area increase. rapid area increase.

• Hardware Oriented Hardware Oriented ControllerController

- decomposedecompose global controller

according to

hardware allocationhardware allocation

- may cause the same same problemsproblems

as centralized centralized controllerscontrollers



3. Approaches to Control Circuit 3. Approaches to Control Circuit Generation - IIGeneration - II

• Process-Oriented Process-Oriented ControllerController

- PProcess CController

- PProcess SSequencing CController

- CControl NNode CController

- UUnit SSequencing CController



ExampleExampleExampleExampleDFG-Unit 1DFG-Unit 1

ifif0 0

1 1

DFG-DFG-UnitUnit

endifendif

DFG-UnitDFG-Unit

whilewhile0 0

1 1


ChildChild

BlockBlockDFG-Unit DFG-Unit

33

++ ++

++ ++

COND. COND. NodeNode

3. Approaches to Control Circuit 3. Approaches to Control Circuit Generation - IIIGeneration - III

USCUSC

PSCPSC CNCCNC PSCPSC

PC

PC

PC

PC

USCUSC

PC

PC

PC

PCCNCCNCPSCPSC

PC

PC

PC



4. Controller Generation for CDFG - 4. Controller Generation for CDFG - II

Derivation of PCDerivation of PCDerivation of PCDerivation of PC

ReqStart+ReqStart+

ReqOP1+ReqOP1+ ReqOP2t+ReqOP2t+

ReqFU+ReqFU+

AckFU+AckFU+

ReqWDR+ReqWDR+

AckWDR+AckWDR+

AckStart+AckStart+

ReqOPReqOP1-1-

ReqOPReqOP1-1- ReqFU-ReqFU- ReqWDR-ReqWDR-

AckFU-AckFU- AckWDR-AckWDR-

ReqStart-ReqStart-

AckStart-AckStart-

Working PhaseWorking Phase

idling Phaseidling Phase

FUFUALU, MUL..ALU, MUL..

DD RegisterRegister

MUMUXX

MUMUXX

DD

MUMUXX



4. Controller Generation for CDFG - 4. Controller Generation for CDFG - IIII

Derivation of PSC - IDerivation of PSC - IDerivation of PSC - IDerivation of PSC - Istartstart

endend

PC1PC1 PC2PC2

PC3PC3 PC4PC4

OP1OP1 OP2OP2

OP3OP3 OP4OP4

ALU1

++ALU

2

++

ALU2

++ALU

1

++

R1R1

R2R2 R3R3

R2R2 R3R3

R2R2 R3R3 R4R4



4. Controller Generation for CDFG - 4. Controller Generation for CDFG - IIIIII Derivation of PSC Derivation of PSC

- II- IIDerivation of PSC Derivation of PSC

- II- IIstartstart

endend

PC1PC1 PC2PC2

PC3PC3 PC4PC4

Req+Req+

ReqPC1+ReqPC1+AckPC1+AckPC1+ AckPC2+AckPC2+ReqPC2+ReqPC2+

ReqPC3+ReqPC3+ ReqPC4+ReqPC4+

AckPC3+AckPC3+ AckPC4+AckPC4+

Ack+Ack+

Req-Req-

ReqPC2-ReqPC2-ReqPC1-ReqPC1- ReqPC4-ReqPC4-ReqPC3-ReqPC3-

AckPC2-AckPC2-AckPC1-AckPC1- AckPC4-AckPC4-AckPC3-AckPC3-

Ack-Ack-



4. Controller Generation for CDFG - 4. Controller Generation for CDFG - IVIV

CNC ControllersCNC ControllersCNC ControllersCNC Controllers

CNCCNC

ConditionalConditionalNodeNode

ChildChildBlockBlock

ReqConReqCon

AckConAckCon

ReqBlkReqBlk

AckBlkAckBlk

ReqReq AckAck

FlagFlag



4. Controller Generation for CDFG - 4. Controller Generation for CDFG - VV

Derivation of USCDerivation of USCDerivation of USCDerivation of USC

DFG-Unit 1DFG-Unit 1

ifif0 0

1 1

DFG-DFG-UnitUnit

endifendif

DFG-UnitDFG-Unit

whilewhile0 0

1 1

DFG-Unit DFG-Unit 33

++ ++

++

++


ChildChild

BlockBlock

StartStart

BlockBlock11

BlockBlock22

BlockBlock33

EndEnd

Req+Req+

ReqBlk1ReqBlk1++

AckBlk1AckBlk1++

ReqBlk2ReqBlk2++

AckBlk2AckBlk2++

ReqBlk3ReqBlk3++

AckBlk3AckBlk3++

ReqBlk2ReqBlk2--

AckBlk2AckBlk2--

Ack+Ack+

Req-Req-

Ack-Ack-

ReqBlk1ReqBlk1--

AckBlk1AckBlk1--

ReqBlk3ReqBlk3--

AckBlk3AckBlk3--



4. Controller Generation for CDFG - 4. Controller Generation for CDFG - VIVI

A given STGSTG should satisfy the following four propertiesthe following four properties in order to be synthesized into a speed-independent circuitspeed-independent circuit.

•BoundednessBoundedness

• ConsistencyConsistency

• Output Semi-ModularityOutput Semi-Modularity

• Complete State Coding PropertyComplete State Coding PropertyPCPC, PSCPSC, CNCCNC and USCUSC, which are derived through the suggested method, satisfysatisfy above fourfour propertiesproperties inherently !!!

PCPC, PSCPSC, CNCCNC and USCUSC, which are derived through the suggested method, satisfysatisfy above fourfour propertiesproperties inherently !!!



5. Timing Constraints - I5. Timing Constraints - I

For correct control, designer should satisfy following three timing

constraints;

1. DDFUFU Maximum OP Fetch DelayMaximum OP Fetch Delay + FU’s worst case delayFU’s worst case delay +

Destination Register’s input Mux’s worst case delaDestination Register’s input Mux’s worst case delayy

2. DDRegReg Worst case delay for Register writing delayWorst case delay for Register writing delay

3. For two consecutive processes, Pi and Pj using the same hardware, the idling phase of Pthe idling phase of P ii should not overlap withshould not overlap with the the working phase of Pworking phase of P jj.. : Constraint due to : Constraint due to

bundled delaybundled delay



5. Timing Constraints - II5. Timing Constraints - II

PC1PC1 PC2PC2

FU/REGISTERFU/REGISTERDD

ReqFU1ReqFU1

ReqFU2ReqFU2

AckFU1AckFU1 AckFU2AckFU2

Delay Constraint 3 Delay Constraint 3 - I- I

Delay Constraint 3 Delay Constraint 3 - I- I

11

11

11

11

00

11

11

00

00

11

PSCPSC

1100

11 00



5. Timing Constraints - III5. Timing Constraints - III

PC1PC1 PC2PC2

FU/REGISTERFU/REGISTERDD

ReqFU1ReqFU1

ReqFU2ReqFU2

AckFU1AckFU1 AckFU2AckFU2

Delay Constraint 3 Delay Constraint 3 - II- II

Delay Constraint 3 Delay Constraint 3 - II- II

11

00

11

00

11

PSCPSC

1111 00

00

00

00

00

11

11

11

11

11



6. Experimental Results - I6. Experimental Results - I

+

*

Adder1Adder1

MUL1MUL1

R1R1

R2R2

+

*

Adder1Adder1

MUL1MUL1

R2R2

R1R1

+

*

Adder1Adder1

MUL1MUL1

R1R1

R2R2

Adder : 1Adder : 1

Multiplier : Multiplier : 11

Register : Register : 22

11

22

33

44

55

66



6. Experimental Results - II6. Experimental Results - II

ControllersControllersControllersControllers

HO1HO1ADD/MULADD/MUL HO1HO1ADD/MULADD/MUL



# of Literals# of Literals# of Literals# of Literals

27(3)27(3)27(3)27(3)

51(6)51(6)51(6)51(6)

98(8)98(8)98(8)98(8)

AreaAreaAreaArea

73.8273.82 73.8273.82SynthesisSynthesisSynthesisSynthesis

17.5 sec 17.5 sec 17.5 sec 17.5 sec

146.68146.68146.68146.68

247.01247.01247.01247.01204.8 sec204.8 sec204.8 sec204.8 sec

790.36 sec 790.36 sec 790.36 sec 790.36 sec

HO1HO1REGREG HO1HO1REGREG


21(3)21(3)21(3)21(3) 71.49 71.49 71.49 71.49 6.8 sec 6.8 sec 6.8 sec 6.8 sec


47(3)47(3)47(3)47(3)

73(5)73(5)73(5)73(5) 81.5381.53 81.5381.53

151.99151.99151.99151.99 28.4 sec28.4 sec 28.4 sec28.4 sec

97.33 sec97.33 sec 97.33 sec97.33 sec

PCPCCOMPCOMP PCPCCOMPCOMP

PCPCASSIASSI PCPCASSIASSI

PSC2 PSC2 PSC2 PSC2

14141414

4444

5555

21.6221.62 21.6221.62 1.2 sec1.2 sec 1.2 sec1.2 sec

15.2915.29 15.2915.29

14.6314.63 14.6314.63 0.2 sec0.2 sec 0.2 sec0.2 sec

0.5 sec0.5 sec 0.5 sec0.5 sec

PSC4PSC4 PSC4PSC4

PSC8PSC8 PSC8PSC811111111 20.2820.2820.2820.28 2.1 sec2.1 sec 2.1 sec2.1 sec

23232323 31.2931.2931.2931.29 53.9 sec 53.9 sec 53.9 sec 53.9 sec

I/O RTI/O RTI/O RTI/O RT

2.09 ns2.09 ns2.09 ns2.09 ns

2.36 ns2.36 ns2.36 ns2.36 ns

3.40 ns3.40 ns3.40 ns3.40 ns

2.80 ns2.80 ns2.80 ns2.80 ns

1.97 ns1.97 ns1.97 ns1.97 ns

2.92 ns2.92 ns2.92 ns2.92 ns

0.71 ns0.71 ns0.71 ns0.71 ns

0.94 ns0.94 ns0.94 ns0.94 ns

0.68 ns0.68 ns0.68 ns0.68 ns

0.65 ns0.65 ns0.65 ns0.65 ns

0.51 ns0.51 ns0.51 ns0.51 ns

Table 1. Controller Comparison between Table 1. Controller Comparison between Hardware-OrientedHardware-Oriented/ / Process-Process-Oriented methodsOriented methods



6. Experimental Results - III6. Experimental Results - III

11

22

33

44

55

66

77

88

99

1010

11

33

55

77

88

99

1010

22

44 66

Differential Equation Differential Equation SolverSolver

Differential Equation Differential Equation SolverSolver

[Async’97, K. Y. Yun et al.]



6. Experimental Results - IV6. Experimental Results - IV

ControllersControllersControllersControllers

AFSMAFSMALU1ALU1 AFSMAFSMALU1ALU1

AFSMAFSMALU2ALU2 AFSMAFSMALU2ALU2

AFSMAFSMMUL1MUL1 AFSMAFSMMUL1MUL1

# of Literals# of Literals# of Literals# of Literals

43434343

139139139139

42424242

AreaAreaAreaArea

65.8665.86 65.8665.86SynthesisSynthesisSynthesisSynthesis


200.00200.00200.00200.00

64.1664.16 64.1664.1620.1 sec20.1 sec20.1 sec20.1 sec


AFSMAFSMMUL2MUL2 AFSMAFSMMUL2MUL2

TOTALTOTAL TOTALTOTAL15151515 23.9423.94 23.9423.94 2.5 sec2.5 sec 2.5 sec2.5 sec

239239239239 353.96353.96353.96353.96 32.3 sec32.3 sec32.3 sec32.3 sec

USCUSC USCUSC

CNCCNCWHILEWHILE CNCCNCWHILEWHILE

PSC3PSC3 PSC3PSC3

8888

27272727

9999

18.2918.29 18.2918.29 0.99 sec0.99 sec0.99 sec0.99 sec

68.1868.18 68.1868.18

17.3017.30 17.3017.301.25 sec1.25 sec1.25 sec1.25 sec

1.27 sec1.27 sec1.27 sec1.27 sec

PSC7PSC7 PSC7PSC7

PCPC PCPC21212121 28.9428.94 28.9428.94 29.7 sec29.7 sec29.7 sec29.7 sec

14 14 9 914 14 9 9 21.6221.629921.6221.6299 1.2 sec1.2 sec 1.2 sec1.2 sec

TOTALTOTAL TOTALTOTAL 191191191191 327.29327.29327.29327.29 34.41 sec 34.41 sec 34.41 sec 34.41 sec

I/O RTI/O RTI/O RTI/O RT

1.37 ns1.37 ns1.37 ns1.37 ns

2.49 ns2.49 ns2.49 ns2.49 ns

1.82 ns1.82 ns1.82 ns1.82 ns

1.32 ns1.32 ns1.32 ns1.32 ns

7.00 ns7.00 ns7.00 ns7.00 ns

0.52 ns0.52 ns0.52 ns0.52 ns

1.57 ns1.57 ns1.57 ns1.57 ns

0.44 ns0.44 ns0.44 ns0.44 ns

0.36 ns0.36 ns0.36 ns0.36 ns

0.71 ns0.71 ns0.71 ns0.71 ns

3.60 ns3.60 ns3.60 ns3.60 ns

Table 2. Controller Comparison between Table 2. Controller Comparison between Hardware-OrientedHardware-Oriented/ / Process-Process-Oriented methods Oriented methods for Differential Equation Solverfor Differential Equation Solver[Async’97 & 3D, K. Y. Yun et al.]



6. Experimental Results - V6. Experimental Results - V

Simulation result I - ControllersSimulation result I - Controllers



6. Experimental Results - VI6. Experimental Results - VI

Simulation result II - DatapathSimulation result II - Datapath



7. Conclusion7. Conclusion

In this paper, we suggest an automaticautomatic asynchronous controller generation method based on process-oriented methodprocess-oriented method having the following noticeable features; • to present a systematic systematic and hierarchicalhierarchical way

• to produce STGs satisfying four propertiesfour properties for SI-circuit synthesisSI-circuit synthesis

• to be efficientefficient in the points of areaarea and performanceperformance

• to be usefuluseful for controller generationcontroller generation of large initial specificationlarge initial specification

Consequently, process-oriented process-oriented methodmethod can be used as an alternativealternative approach to asynchronous controller asynchronous controller generationgeneration.

Consequently, process-oriented process-oriented methodmethod can be used as an alternativealternative approach to asynchronous controller asynchronous controller generationgeneration.

Documents

Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis