AUT-F0950 MPC560xB, MPC560xP, MPC560xS Low … MPC560xP, MPC560xS Low Power Features ... Module (BAM) Oscillator System Integration ... MPC560xB Modes Transition TM

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

AUT-F0950

MPC560xB, MPC560xP, MPC560xS Low Power Features

August, 2010

Hua Qian

Automotive Systems Engineer

Agenda

1. MPC560xB Overview

2. System Clock Structure

3. Low Power Management

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 2

4. Autonomous Intelligent Operations

TM

1. MPC560xB Overview

Cross Family Compatibility

CROSSBAR SWITCH

40K

SRAM

PowerPCTMe200z0

Core

VReg

Communications I/O System

Crossbar Slaves

Interrupt Controller

Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

FMPLL

FlexRay

CROSSBAR SWITCH

40K

SRAM

PowerPCTMe200z0

Core

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

FMPLL

FlexRay

CROSSBAR SWITCH

40K

SRAM

PowerPCTMe200z0

Core

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

FMPLL

FlexRay

CROSSBAR SWITCH

40K

SRAM

PowerPCTMe200z0

Core

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

FMPLL

FlexRay

CROSSBAR SWITCH

32K

SRAM

PowerPCTM

e200z0

Core

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

Memory Protection Unit (MPU)

System Integration

DMAReadyRTC

I/O

Bridge

FMPLL

Power Sw

PIT 4ch 32b

MCM

CROSSBAR SWITCH

32K

SRAM

PowerPCTM

e200z0

Core

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMAReadyRTC

I/O

Bridge

FMPLL

Power Sw

PIT 4ch 32b

MCM

CROSSBAR SWITCH

48K

SRAM

PowerPCTMe200z3

Core

SIMDMMU

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

FMPLL

Ca

l B

us I

nte

rface

CROSSBAR SWITCH

48K

SRAM

PowerPCTMe200z3

Core

SIMDMMU

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

FMPLL

Ca

l B

us I

nte

rface

CROSSBAR SWITCH

48K

SRAM

PowerPCTMe200z3

Core

SIMDMMU

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

FMPLL

Ca

l B

us I

nte

rface

CROSSBAR SWITCH

48K

SRAM

PowerPCTMe200z3

Core

SIMDMMU

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

FMPLL

Ca

l B

us I

nte

rface

CROSSBAR SWITCH

64K

SRAM

PowerPCTM

e200z0

Core

External

Bus

(208MAPBGA)

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

DisplayInterface

UnitRTC

I/O

Bridge

FMPLL

VideoRAM

(tbd)

CROSSBAR SWITCH

64K

SRAM

PowerPCTM

e200z0

Core

External

Bus

(208MAPBGA)

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

DisplayInterface

UnitRTC

I/O

Bridge

FMPLL

VideoRAM

(tbd)

CROSSBAR SWITCH

64K

SRAM

PowerPCTM

e200z0

Core

External

Bus

(208MAPBGA)

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

DisplayInterface

UnitRTC

I/O

Bridge

FMPLL

VideoRAM

(tbd)

CROSSBAR SWITCH

64K

SRAM

PowerPCTM

e200z0

Core

External

Bus

(208MAPBGA)

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

DisplayInterface

UnitRTC

I/O

Bridge

FMPLL

VideoRAM

(tbd)

“Monaco”(Powertrain)

“Pictus”(Steering/Airbag)

“Bolero”(Body/Gateway)

“Spectrum”(Inst Cluster)

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

►Maximum IP reuse

►Optimized design and test flow

►Consolidated tool chain

► Strong marketing message in compatibility

4

1or2

FlexCAN

1

eSCI

Mc T

imer

3DSPI

Mc T

ime

r

Mc T

ime

r

Mc P

WM ADC I/F

10 bit650 nsec

S&H S&H

mux mux

1or2

FlexCAN

1

eSCI

Mc T

imer

3DSPI

Mc T

ime

r

Mc T

ime

r

Mc P

WM ADC I/F

10 bit650 nsec

S&H S&H

mux mux

1or2

FlexCAN

1

eSCI

Mc T

imer

3DSPI

Mc T

ime

r

Mc T

ime

r

Mc P

WM ADC I/F

10 bit650 nsec

S&H S&H

mux mux

1or2

FlexCAN

1

eSCI

Mc T

imer

3DSPI

Mc T

ime

r

Mc T

ime

r

Mc P

WM ADC I/F

10 bit650 nsec

S&H S&H

mux mux


3 FlexCAN

4LINFlex

32 ch

ATD12bit

eMIOSLite8ch IO

36ch shiftPWM

3

DSPI2

I2C


3 FlexCAN

4LINFlex

32 ch

ATD12bit

eMIOSLite8ch IO

36ch shiftPWM

3

DSPI2

I2C


2

FlexCAN

2

eSCI

32 ch

ATD

12bit

eMIOSLite24ch

2

DSPIeTPU

32 ch.

2.5K Code

RAM

12K Data

RAM


2

FlexCAN

2

eSCI

32 ch

ATD

12bit

eMIOSLite24ch

2

DSPIeTPU

32 ch.

2.5K Code

RAM

12K Data

RAM


2

FlexCAN

2

eSCI

32 ch

ATD

12bit

eMIOSLite24ch

2

DSPIeTPU

32 ch.

2.5K Code

RAM

12K Data

RAM


2

FlexCAN

2

eSCI

32 ch

ATD

12bit

eMIOSLite24ch

2

DSPIeTPU

32 ch.

2.5K Code

RAM

12K Data

RAM


2 CAN

2

LIN

Flex

16 ch

ATD10bit

6

gauge

drivers

eMIOSLite

24 ch.

2

I2C

3

DSPI

so

un

d

40x4

LCD


2 CAN

2

LIN

Flex

16 ch

ATD10bit

6

gauge

drivers

eMIOSLite

24 ch.

2

I2C

3

DSPI

so

un

d

40x4

LCD


2 CAN

2

LIN

Flex

16 ch

ATD10bit

6

gauge

drivers

eMIOSLite

24 ch.

2

I2C

3

DSPI

so

un

d

40x4

LCD


2 CAN

2

LIN

Flex

16 ch

ATD10bit

6

gauge

drivers

eMIOSLite

24 ch.

2

I2C

3

DSPI

so

un

d

40x4

LCD

3232--bit standard architecture adopted across all product familiesbit standard architecture adopted across all product families

MPC5604B (512K)

CROSSBAR SWITCH

PowerPCTM

e200z0Core

VReg


Crossbar Masters

Nexus 2+

JTAG

Debug

Oscillator


System Integration

FMPLL

CORE• PowerPC e200z0 core running 48-64MHz

• VLE ISA instruction set for superior code density

• Vectored interrupt controller

• Memory Protection Unit with 8 regions, 32byte granularity

MEMORY• 512Kbyte embedded program Flash, 64KByte data flash

• 64Kbyte embedded data Flash (for EE Emulation)

• Up to 64MHz non-sequential access with 2WS

• ECC-enabled array with error detect/correct

• 48Kbyte SRAM (single cycle access, ECC-enabled)

COMMUNICATIONS• 3x enhanced FlexCAN

• 64 Message Buffers each, full CAN 2.0 spec

• 4x LINFlex

PIT 4ch 32bPower Mgt


48K SRAM


Crossbar Slaves

512KFlash

BootAssist

Module (BAM)

I/OBridge

3 FlexCAN

4LINFlex

1I2C

3 DSPI

• 4x LINFlex

• 3x DSPI, 8-16 bits wide & chip selects

• 1x I²C

ANALOG• 5V ADC 10-bit resolution

TIMED I/O• 16-bit eMIOS module

OTHER•CTU (Cross Triggering Unit) to sync ADC with PWM Channels

• Debug: Nexus 2+

• I/O: 5V I/O, high flexibility with selecting GPIO functionality

• Packages: 100LQFP, 144LQFP, 208MAPBGA (Development only)

• Boot Assist Module for production and bench programming

Standby RAM

64K DataFlash

36 chADC10bit

eMIOSLite6ch IC/OC50ch PWM

CTU

MPC5607B (1.5M)

CORE

• PowerPC e200z0 core running at 64MHz @ Ta=105C (48Mhz at 85oC Base)

• VLE ISA instruction set for superior code density

• Vectored interrupt controller

• Memory Protection Unit with 16 regions, 32byte granularity

•MEMORY

• 1.5M byte embedded program Flash

• 64Kbyte embedded data Flash (for EE Emulation)

• Up to 64MHz non-sequential access with 2WS

• ECC-enabled array with error detect/correct

• 96Kbyte SRAM (single cycle access, ECC-enabled)

COMMUNICATIONS

• 6x enhanced FlexCAN


CROSSBAR SWITCH

PowerPCTM

e200z0Core

VReg


Crossbar Masters

Nexus 2+

JTAG

Debug

Oscillator


System Integration

FMPLL

PIT 4ch 32bPower Mgt

DMA

additional DMA, bigger memories, additional 12 Bit ADC, richer peripheral set



• 10 x LINFlex

• 6 x DSPI, 8-16 bits wide & chip selects

• 1 x I²C

ANALOG

• Up to 52 ch 5V ADC (16x12-bit, 36x10-bit) resolution

TIMED I/O

• 16-bit eMIOS module, 64ch.

OTHER

• 32 Channel DMA Controller

• Debug: Nexus 2+

• I/O: 5V I/O, high flexibility with selecting GPIO functionality

• Packages: 100LQFP, 144LQFP, 176LQFP, 208MAPBGA (TBD)

• Boot Assist Module for production and bench programming

96K SRAM


Crossbar Slaves

1.5MFlash

BootAssist

Module (BAM)

I/OBridge

6 FlexCAN

10LINFlex

Up to 52 ch ADC

16x12bit, 36x10 Bit

eMIOS64ch, 16 bit

1I2C

6 DSPI

Standby RAM

64K DataFlash

TM

2. System Clock Structure

Clock Structure: Allows sysclk Selection & Dividing Clocks to Most Peripherals

System Clock

Selector(ME)

CorePlatform

Peripheral Set 1

Peripheral Set 2div 1 to 16

div 1 to 16

FXOSC 4-16MHz

div 1 to 32

FIRC16MHz* div 1 to 32

FMPLL

SYSCLKFXOSC_DIV

FIRC_DIV

FIRC

FXOSCRESETSAFE


Peripheral Set 3div 1 to 16

SXOSC 32KHz

div 1 to 32

SIRC 128KHz

div 1 to 32

API / RTC

SWT (Watchdog)

CMUFXOSC SAFE

INT

FIRC_DIV

SXOSC_DIV

SIRC_DIV

CLOCK OUTdiv 1/2/4/8

CLKOUT Selector

FXOSC

FIRC

FMPLL

SIRC

SXOSC32KHz128KHz

*Enabled as sysclk after reset

System Clock Configuration

MODE

SYSTEM RESET TEST SAFE DRUN HALT STOP STBY

IRC DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

IRC_DIV √ √ √ √

XOSC √ √ √ √

XOSC_DIV √ √ √ √


PLL √ √ √

NO CLK √ √ DEFAULT

√ CONFIGURABLE

NOT CONFIGURABLE

TM

3. Low Power Management

RUN 0

RUN 1

HALT

USER MODES

LOW POWERMODES

SAFE

SYSTEM MODES

SW request

RecoverableHW failure

MPC560xB Modes Transition


RUN 3

STANDBY

STOP

TEST

DRUNRESET

Non recoverableHW failure

HW triggered transitionSW triggered transition

MPC560xB Low Power User Modes

►HALT• Core stopped but system clock can remain the same as in RUN mode

• Selective peripheral clock gating

• Flash can be put in low power mode

• Useful to reduce device consumption during a slow serial communication e.g. LIN frame

transmission or reception

►STOP• Provides additional low power features beyond HALT, including:


• Provides additional low power features beyond HALT, including:

� System clock can be disabled

� PLL is always disabled

� System clock is only FIRC upon STOP mode exit

►STANDBY• Mode providing the lowest possible consumption

• Most functions (digital and analog) of the device are not powered

• Remains only the back-up logic (e.g. RTC/API, preserves wake-up inputs, part of SRAM.)

• On STANDBY exit, the processor uses the RESET vector or a SRAM Vector if enabled

� WISR register in the Wake Up Unit can be used to verify the wake up source

12

ME_xxx_MC - Mode Configuration Registers

►Each mode has a Mode Configuration register.

►Examples: ME_DRUN_MC, ME_RUN0_MC, ME_RUN1_MC, etc.

CFLAONDFLAONMVR

ONreservedPDOreserved CFLAONDFLAON

MVR

ONreservedPDOreserved

OSC IRCPLL OSC IRCPLL

1 4 7 8 9 150 32 65 12 13 141110

17 20 23 24 25 3116 1918 2221 28 29 302726


OSC

ONSYSCLK

IRC

ON

PLL

ON

OSC

ONSYSCLK

IRC

ON

PLL

ONreserved

• PDO: Disable pad outputs (put in hi Z)

• MVRON: control VREG on/off

• CFLAON/DFLAON:

• control code / data flash module• Normal• Low Power

• Power Down

• PLLON: control PLL on/off

• OSCON: control XOSC on/off

• IRCON: control IRC16M on/off

• SYSCLK: select system clock

Resource Configuration

PDOMVR

DATA

FLASH

CODE

FLASHPLL OSC IRC

RESET RESET OFF ON NORMAL NORMAL OFF OFF ON

TESTUSER √

ON√ √ √ √ √

RESET OFF NORMAL NORMAL OFF OFF ON

SAFEUSER √

ON NORMAL NORMAL OFF OFF ON

RESET ON

DRUNUSER

OFF ON√ √ √

ON

RESET NORMAL NORMAL OFF OFF

√ √ √ √ √ CONFIGURABLE


RUNxUSER

OFF ON√ √ √ √

ON

RESET NORMAL NORMAL OFF OFF

HALTUSER

OFF√ √ √ √ √ √

RESET ON LOW POWER LOW POWER OFF OFF ON

STOP

USER √ √ √ √OFF

√ √

RESET OFF ONPOWER

DOWN

POWER

DOWNOFF ON

STBYUSER

OFF OFFPOWER

DOWN

POWER

DOWNOFF OFF

√

RESET ON

NOT CONFIGURABLE

√ CONFIGURABLE

Peripheral Control Registers

►For each peripheral, there is a ME_PCTLx register which:

• Controls gating clock to each peripheral on a MODE by MODE basis

• ME_PCTLx register:

� selects one of the 8 run peripheral set configurations

� selects one of the 8 Low Power peripheral set configurations

� enables/disables freezing the clock during debug


Peripheral 1

Peripheral 2

Peripheral 3

Peripheral 143

MC_ME Peripheral Configuration RegistersRUN Modes

►Defines a selection of 8 possible RUN mode configurations for a peripheral


VREG Supply and Regulator Diagram

330nF

330nF

330nF

SW 1

VDD_BV

DOMAIN #1 (MAIN)

Core, peripherals,Flash, XOSC, PLL,ME, etc.

CFlash

DFlash

PLL

VDD_LV

ADCAVDD_HV

AVDD_REF

VDD_HV

VDD_HV

CTRL

Low Power

High Power

CTRL

CTRL

Ultra Low Power


REGULATOR

Main supply : 5v or 3.3vDigital supply : 1.2v

POR

Power On Reset

DOMAIN #0 (STBY)

8KRAM, RGM, IRCWake-up Unit, etc.

SW 2

PCU

LVD 1.2

Low Volt. Detector

LVD 2.7

LVD 4.5

LVD 1.2

DOMAIN #2 (STBY)

24KRAM

PA[0]PA[1]

Px[y]

PC[0]PC[1]

Pn[m]

VDD_HV

VDD_HV

Ballast supply : 5v or 3.3v

Power Domains Control

DomainMode

0 1 2

STANDBY ON OFF OFF

STOP0 ON ON ON

HALT0 ON ON ON

RUN3 ON ON ON

RUN2 ON ON ON

Table: Default Status of Power Domain vs. Modes


RUN2 ON ON ON

RUN1 ON ON ON

RUN0 ON ON ON

DRUN ON ON ON

SAFE ON ON ON

TEST ON ON ON

RST ON ON ON

Not configurable

Configurable

Wakeup Unit Block Diagram

►The WKPU remains powered in low power mode

►Each pin can:

• Issue only a wakeup, or an interrupt, or

both

• Be sensitive on rising, falling or both

edges

• Has an analog glitch filter, which can be

separately enabled


separately enabled

• Internal pull-up

► In addition the chip provides external interrupts through different external pins

19

Low Power - Static Consumption

STANDBY @25°C

CORE 0

RAM (8K/32K) 6 / 17

CFLASH 3

DFLASH 3

ADC 0

XOSC 0

PLL 0

WAIT/HALT @25°C

CORE 0

RAM 32K 1000

CFLASH 13

DFLASH 13

ADC 0

XOSC 0

PLL 10


IRC16M 0

IRC128K 5

VREG 5

WDG 0

API/RTC 2

Wake-up lines 2

LVD 3

Leakage (dig.) 4

TOTAL 33 / 44uA

IRC16M 135

IRC128K 5

VREG 500

WDG 0

API/RTC 2

Wake-up lines 2

LVD 50

Leakage (dig.) 90

TOTAL < 2mA

Low Power - Dynamic Consumption

RUN @8MHz/IRC (from RAM)

CORE 5280

RAM 32K 1625

CFLASH 13

DFLASH 13

ADC 0

XOSC 0

PLL 10

RUN @8MHz/XTAL (from RAM)

CORE 5280

RAM 32K 1625

CFLASH 13

DFLASH 13

ADC 0

XOSC 1500

PLL 10


IRC16M 135

IRC128K 5

VREG 500

WDG 0

API/RTC 2

Wake-up lines 2

LVD 50

Leakage (dig.) 90

TOTAL < 8mA

IRC16M 135

IRC128K 5

VREG 500

WDG 0

API/RTC 2

Wake-up lines 2

LVD 50

Leakage (dig.) 90

TOTAL < 10mA

TM

4. Intelligent Autonomous Operations

►Power Reducing Strategies• MCU level perspective - Put more intelligence into peripherals

• ECU level perspective - Put more intelligence outside MCU

►Key system techniques to help achieve this

• Typical Autonomous MCU peripherals include:

� API – Autonomous Periodic Interrupt

– Allows device to recover from very low power state at selectable time intervals

� RTC – Real Time Clock

Autonomous Operation

CPU is the most power hungry module on MCU


� RTC – Real Time Clock

– Offers time keeping functionality in very low power state

� DMA – Direct Memory Access

– Allows data transfer between peripherals minimizing CPU activity

� ADC – Analog Digital Converter

– Continual conversion while running in low power

– Triggers wake-up when signal reaches certain level

� Communication ports – LIN/CAN/FlexRay/Ethernet, minimizing CPU interrupts

• Typical external intelligence includes:

� Regulator supervisor

� SBC (System Basis Chip)

Low power scenario MPC560x – option 1a

Run @2MHz bus (int 16MHz RCosc/8)

Current consumption MPC5601/2

30µA

16ms

48µsMode switchVreg recovery

10µsDevice init (20 cycl.)

1µsSetport (2 cycl.)

7µsRTC &Intinit (14 cycl.)

3µsEnterstop (6 cycl.)

<8mA

standby with running APIStop with RTC active<300µA


10µsRead digIOs (20 cycl.)

3µsEnterstdby (6 cycl.)

Stop with RTC active

64µs

69µs 57µs

Current consumption SBC 16ms


Phase 1 – 16ms : Micro in standby mode, internal API timer automatically wakes after 16ms

Phase 2 – 69µs : Micro in run mode, running from internal 16MHz RC osc and 2MHz bus.In this phase IO is set after device init to enable external pullup switchRTC is set to minimum period of 64µs to wakeup the device after entering stop

Phase 3 – 64µs : Micro in stop mode, RTC set to wake up from stop after 64µs.Phase 3 – 57µs : Micro in run mode, running from internal 16MHz RC osc and 2MHz bus.

In this phase digital switches are read

Stop mode (VDD on)

Current consumption SBC

Stop window on mode

28µA

8mA

16ms

Average currentMPC5602:

94µA

Average currentMPC5602 & SBC:

184µA

Low power scenario MPC560x – option 1b

Run @2MHz bus (int 16MHz RCosc/8)

Current consumption MPC5601/2

30µA

16ms


10µsDevice init (20 cycl.)

1µsSetport (2 cycl.)

7µsRTC &Intinit (14 cycl.)

3µsEnterstop (6 cycl.)

<8mA

standby with running APIStop with RTC active<300µA


10µsRead digIOs (20 cycl.)

3µsEnterstdby (6 cycl.)

1µsA/DSwitchon

10µsAD setup(20 cycl.)

9.5µsAD Sampl.&Conv.(20 cycl.)

Stop with RTC active

64µs

69µs 77.5µs

Current consumption SBC 16ms


Phase 1 – 16ms : Micro in standby mode, internal API timer automatically wakes after 16ms

Phase 2 – 71µs : Micro in run mode, running from internal 16MHz RC osc and 2MHz bus.In this phase IO is set after device init to enable external pullup switchRTC is set to minimum period of 64µs to wakeup the device after entering stop

Phase 3 – 64µs : Micro in stop mode, RTC set to wake up from stop after 64µs.Phase 3 – 77.5µs : Micro in run mode, running from internal 16MHz RC osc and 2MHz bus.

In this phase ATD converter started, digital switches are read and Analog inputs converted and read

Stop mode (VDD on)

Current consumption SBC

Stop window on mode

28µA

8mA

16ms

Average currentMPC5602:

104µA

Average currentMPC5602 & SBC:

205µA

TM

Documents

AUT-F0950 MPC560xB, MPC560xP, MPC560xS Low … MPC560xP, MPC560xS Low Power Features ... Module (BAM) Oscillator System Integration ... MPC560xB Modes Transition TM