August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University

August 06August 06

PKUnity: A SoC PKUnity: A SoC Design and Verification PlatformDesign and Verification Platform

Lu JunlinMicroProcessor R&D Center (MPRC)

Peking University

August 06August 06

ICDFN 2006ICDFN 2006

Outline

• PKUnity SoC Platform Features

• Multi-Layers Verification Framework

• CDC Verification Tool

• Future Works

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Outline




• Future Works

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What for

• Providing a PLATFORM for implementing and verifying NEW IDEALS in Nanotechnologies

Behavioral Level Simulation Behavioral Level Simulation (SystemC)(SystemC)

RTL Simulation/EmulationRTL Simulation/Emulation

(Verilog/VHDL)(Verilog/VHDL)

FPGA PrototypingFPGA Prototyping

Silicon ProvingSilicon Proving

New IdeasNew Ideas

Multi-MediaMulti-Media

ProcessingProcessing

CPUCPU

On-chipOn-chip

communicationcommunication

NetworkNetwork

CompilerCompiler

SoftwaresSoftwares

PKUnity PlatformPKUnity Platform

SynthesisSynthesis

Low PowerLow Power

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What is

• PKUnity Platform includes:– a scalable and configurable SoC architecture– a series of UniCore CPU– plenty of communication IPs – a verification framework– some verification tools– compilation tool chain and OS based on UniCore

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PKUnity Architecture

UniCoreUniCoreCPUCPU

Memory and Memory and High Speed I/OHigh Speed I/O

Low Speed I/OLow Speed I/Oandand

System ModulesSystem Modules

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Design Features

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Design Features

• CPU– 600MHz UniCore– 8-Stage Pipeline– 64-bit Floating Point Co-Processor– 16KB I/D Cache– 2-Port Bus Interface

• Main Memory– DDR (Double Data Rate) SDRAM– 166MHz Clock and 64-bit Width– 2 Memory Access Channels

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Design Features

• High Speed I/O Devices– 10M/100M/1G Ethernet MAC– 66MHz PCI Bridge– IDE SATA Controller– USB OTG Controller

• Low Speed I/O Devices– UART– I2C– SPI– AC’97– PS/2

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Design Flow

SystemC-based

HW/SW Co-verification

SystemC-based

HW/SW Co-verification

RTL Simulationand Emulation

RTL Simulationand Emulation

FPGA Prototyping

FPGA Prototyping

Design and

Implementation

Design and

Implementation

RTL Sign OffRTL Sign Off

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Challenges

• Complex Communication Protocol

• Lots of Asynchronous Clock Domains

DesignDesign

VerificationVerification&&

• Gap between CPU and Main Memory

• Different Bus Bandwidth Requirements

• Power Supply

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Design Solutions

• Two-Layer bus– CPU-MEM bus– IO-MEM bus

CPU-MEM BusCPU-MEM Bus

IO-MEM BusIO-MEM Bus

Slow ClockSlow ClockEnough Enough

PerformancePerformance

ReduceReduce the power the power

supplysupply

Fast ClockFast ClockBest Best

PerformancePerformance

Minimize Minimize CPU-MEM CPU-MEM

bandwidth gapbandwidth gap

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Verification Solutions

• Multi-Layer Verification Framework– For Complex Communication Protocol

• CDC Verification Tool– For Lots of Asynchronous Clock Domains

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Outline


• Multi-Layers Verification FrameworkMulti-Layers Verification Framework


• Future Works

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Verification Challenges

• Complex Communication Protocol– AHB vs. DDR SDRAM– AHB vs. PCI– AHB vs. MAC– AHB vs. USB OTG– AHB vs. IDE– APB vs. AC’97– … It’s hard to cover all the It’s hard to cover all the

transaction types!transaction types!

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Verification Methodology

• Multi-Layer– Signal Layer– Bus Layer– Transaction Layer– Scenario Layer

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Self Checking

• Self Checking by two channels

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Verification Framework

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Example

Veri fi cat i on Coverage(3)

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Li ne CoverageBranch CoverageCondi t i on Coverage


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Ver i fi cat i on Coverage(2)

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• Ethernet MAC Verification Coverage

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Outline



• CDC Verification ToolCDC Verification Tool

• Future Works

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What’s CDC

• CDC: Clock Domain Crossing

CLKA

FF1 FF2

CLKB

R1 R3R2QD QD QD

FF3

CYCLE 2CYCLE 1 CYCLE 3

setup time hold time

CLKA

R1

CLKB

R2

R3

metastable

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Challenges

• Lots of Asynchronous Clock Domains– The relationship of clocks is static in the normal simul

ation– It’s difficult to find setup time and hold time violation

(metastable state)

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Method (Step 1)

1. Find all the CDC paths– Handshake Logic– Gray code counter– ...

HCLK domainICLK domain

FF1

QDram_out[7:0]

QD

QD QD

sample_en

QD

FF2 FF3FF4

Q

D

EN

combinationlogic

CYCLE 1

HCLK

ICLK

ram_r1 ram_r2

ram_out 0x5A 0xA5

ram_r1CDC_state

CYCLE 2 CYCLE 3 CYCLE 4

CDC State Normal

ram_r2CDC_state CDC State Normal

Normal

Normal

sample_enCDC_state CDC State NormalNormal

CYCLE 5

critical to propagation

QD

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Method (Step 2)

2. Insert a module which can provide random delays on each CDC paths

A 1 2 3

Clka

B

Clkb

Clkb

4 C

CDC_delay U_RdDMA_D (.in(RdDMAH), .out(RdDMAH_d));

CDC_delay U_WrDMA_D (.in(WrDMAH), .out(WrDMAH_d));

Clk_jitter U_ICLK(.in(ICLK), .out(ICLK_j));CDC_monitor U_RdDMA_M (.in(RdDMAH_d));CDC_monitor U_WrDMA_M (.in(WrDMAH_d));

always @ (posedge HCLK)begin RdDMAH <= (RWCON & !RdDMAH); WrDMAH <= (!RWCON & !WrDMAH);end

assign XCS <= !WrDMAH_d & !RdDMAH_d & CS0;

always @ (posedge ICLK_j) NCS <= (WrReqI | RdReqI) & XCS;

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Method (Step 3)

3. Add reasonable delays on the CDC paths in simulation repeatedly

It’s hard to reach It’s hard to reach

100% coverage, 100% coverage,

but it does find some but it does find some

severe bugs missed in severe bugs missed in

the normal simulation!the normal simulation!

RdDMAH WrDMAH

XCS

RdReqH WrReqH

WrReqI_Meta

WrReqI

RdReqI_Meta

RdReqI

NCS

!WrDMAH & !RdDMAH & CS

(WrReqI | RdReqI) & XCS@ICLK

@ICLK @ICLK

@ICLK @ICLK

Starting Vertex

Observable Vertex

Combinational Logic

Sequential Logic

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Example

• A commercial ATA-5 IDE controller IP

- The table shows coverage

comparability after 30 transactions

finished

- The right diagram show the full

coverage growth

Table 1: Comparing Code Coverage with CDC Coverage.

Module Name Function DescriptionNum.

of LinesLine

CoverageNum. of CDC

coverage pointsCDC

Coverage

m3s010fa Asynchronous FIFO 426 97.14% 14336 0.40%

m3s008fa Asynchronous FIFO Control 917 95.14% 5170 0.39%

m3s007faIDE PIO/DMA Timing

Control353 100% 1458 0.27%

m3s012fa IDE UDMA Timing Control 470 100% 972 0.41%

m3s005fa AMBA AHB DMA Control 471 95.70% 620 2.26%

0

10

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30

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60

70

0 1, 000 2, 000 3, 000 4, 000 5, 000 6, 000

Transact i on Num.

CDC

Cove

rage

(%)

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Outline




• Future WorksFuture Works

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Future Works

• Communication Architecture• Bandwidth Allocation Algorithm• CDC Coverage Improvement• …

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Thank You!

Documents

August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University