ATMEL APPLICATIONS Number 6 • Winter 2006 - EFO · Welcome to Atmel Applications Journal Volume 6. ... page 2 ATMEL APPLICATIONSNumber 6 • Winter 2006 ... Computer-On-a-Stick™

A T M E L A P P L I C A T I O N S Number 6 • Winter 2006

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Everywhere You Are™

In This Issue:

• Using ARM Core-based Flash MCUs as a Platform for Custom Systems-on-Chip

• The Explosive World of Serial Flash

• Networked Networks and Embedded Microcontroller Architectures

• Polybot Board: A Robot Controller Board Using the Atmel ATMega32

• Integration and Low Current Consumption: A Reality Today for License-free Wireless Applications

• SiGe BiCMOS or RF CMOS for Your Next Wireless Application?

• Lighting: Ballast Controller Combined with RISC Processor Yields an Efficient Lamp

• Automotive Bus Systems

• Atmel’s Complete Chipset for DAB Reception in Automotive Environments

• Areascan Cameras: How to Choose Between Global and Rolling Shutter

• Simple VGA/Video Adapter Using the Atmel AVR

• A 10-bit 2.2 Gsps ADC Operating Over First and Second Nyquist Zones

Graham Turner, Vice Presidentand General Manager,Microcontrollers Business Unit,Atmel

www.atmel.com page 1

Introduction

Welcome to Atmel Applications Journal Volume 6.

I would like to thank all of you for your dedication to the AVR microcontroller family. 2005 has been anoth-er great year for us and the AVR product family has enjoyed high double-digit growth, both in revenue andunits shipped. Design wins continue to go from strength to strength and we are all very excited about ourprospects for 2006.

In 2006 we will celebrate the 10th anniversary of the AVR. It all started in 1996 in Norway and with thecontinuous efforts of everyone who has joined the team, we have grown the AVR to be the most exciting8-bit microcontroller family in the market place.

In 2005 we increased the family of products by 24 to over 50. We entered the automotive market with theAVR and already have received great customer acceptance for these products. We have also introducedproducts for motor control applications and are able to offer solutions for the PC fan market below 50cents. The TinyAVR family has been expanded with several new parts including 14-pin devices, and final-ly, we have introduced many parts with increased pin counts and larger memories.

Looking forward to 2006, we have many exciting new products to announce. The first of which is as a resultof our considerable R&D efforts to set new standards in the power consumption of our microcontrollers.We will launch a new range of ultra low power products which will significantly extend the lifetime of thebattery in the system. This new development combined with the efficiency of our AVR core will allow us tocontinue as the leader in the 8-bit microcontroller market.

Along with our great products we have continued our advances in software tools and hardware develop-ment systems. There are hundreds of thousands of AVR Studio users out there who will continue to bene-fit from our high quality, low-cost tools. The latest AVR Studio version has enabled third party suppliers toplug their software directly into it for complete integration, which will allow for increases in functionality indebug software and hardware designs. Our continued focus on the AVR Studio, combined with our low-cost starter kits and emulators will ensure that we have the best offering in the market.

In 2006 we will further develop our plan to reduce our lead-times for these popular products so that ourcustomers can get their hands on the AVR quicker than before.

I would like to thank you all for your continued support of the AVR products. We will continue to bring youthe products that you need to develop your own exciting and world-beating products.

www.atmel.compage 2

A T M E L A P P L I C A T I O N S Number 6 • Winter 2006

T A B L E O F C O N T E N T S

Introduction Graham Turner, Atmel

Automotive Bus Systemsby Markus Schmid, Atmel

The Explosive World ofSerial Flash

by Richard De Caro, Atmel

Using ARM Core-based FlashMCUs as a Platform for Custom

Systems-on-Chipby Peter Bishop, Atmel

Atmel News New Product Releases

page 37

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page 10Integration and Low CurrentConsumption: A Reality Today forLicense-free Wireless Applicationsby Eric Mercier, Atmel

Networked Networks andEmbedded Microcontroller

Architecturesby Jacko Wilbrink, Dany Nativel and

Tim Morin, Atmel

Lighting: Ballast ControllerCombined with RISC Processor

Yields an Efficient Lampby Jean-Florent Helie, Electronique Magazine

SiGe BiCMOS or RF CMOS forYour Next Wireless Application?by David Hess, Atmel

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8

13

16

20

22

25

27

29

33

37

40

46

Areascan Cameras: How to Choose Between Global andRolling Shutter by Jacques Leconte, Atmel

A 10-bit 2.2 Gsps ADC OperatingOver First and Second Nyquist Zonesby Francois Bore, Sandrine Bruel and Marc Wingender

Everywhere You Are®

page 32

page 41

Polybot Board: A RobotController Board Using the Atmel

ATMega32by Dr. John Seng, Cal Poly State University

Simple VGA/Video AdapterUsing the Atmel AVRby Ibragimov Maksim, Developer, Russia

page 20

Atmel’s Complete Chipset forDAB Reception in AutomotiveEnvironmentsby Dr. Martin Alles, Atmel


BCDMOS Fail-safe System IC, ATA6814,Designed for Safety-critical

Automotive Applications

Atmel has released a new monolithically integratedfail-safe system IC, the ATA6814, manufacturedusing Atmel's state-of-the-art 0.8-µm BCDMOStechnology. With its built-in driver functions andcomplete monitoring system, the ATA6814 is aunique solution beneficial for all safety-relevantautomotive electronics, such as DC motor controlsthat can be found in electric parking brake systems,power steering, chassis and powertrains. TheATA6814 combines various functions into one sin-gle IC, an improvement over competing solutionsrequiring the addition of several standard compo-nents such as stand-alone voltage regulators andwatchdogs. This leads to significant board spacereduction and smaller, more cost-efficient designs.

The ATA6814 is ideally suited to safety-critical auto-motive applications, since the watchdog is com-pletely separate from the system microcontrollerand operates with its own dedicated oscillator,which in turn is monitored by a second oscillator.

The fail-safe system IC ATA6814 is highly integrat-ed, including voltage regulators, driver stages, anSPI interface, as well as watchdog and monitoringfunctional blocks. Two separate voltage regulatorsand band gaps enable high flexibility, while stillmaintaining a high safety level, thanks to the mutu-al monitoring. Power consumption reduction down

Atmel News: More information on the products and services in these articles can be found at www.atmel.com

to 80 uA in standby mode is achieved since one ofthe voltage regulators can be switched off. The fullyintegrated, 250 mA low-side relay drivers do notneed any additional external circuitry and thus helpto further save cost and space on the PC board.

The independent watchdog circuitry – the heart ofthe fail-safe concept – monitors the microcon-troller's operation. In addition, the monitoring func-tion covers the battery voltage, all internally gener-ated voltages, and the chip temperature in twostages, and it can disable the different IC blocks.

Samples of the new fail-safe system IC ATA6814 inRoHS-compatible QFN48 (7 mm x 7 mm) packagesare available now. Pricing starts at US $2.70 (10 k)

Product information on Atmel's new BCDMOS Fail-safe System IC ATA6814 may be retrieved at:http://www.atmel.com/dyn/products/product_card.asp?part_id=3770

BCDMOS = Mixed-signal technology with Bipolar, CMOS andDMOS componentsDC = Direct CurrentPC board = Printed Circuit boardSPI = Serial Peripheral InterfaceRoHS = Restriction of the Use of Certain Hazardous Substances

Industry’s First MultipleSmart Card ReaderInterface IC for POS

and Health Card ReaderThe AT83C26 is the industry’s first multiple analogsmart card interface which can physically handle up to5 smart cards. It powers the smart cards with theappropriate supply voltage and enables data transferbetween the host controller and the smart cards.System designers can use a single chip to developreaders requiring multiple cards, thus reducing systemsize and cost. The AT83C26 is the ideal solution forPoint of Sales (POS) Terminals that typically involve oneuser card and up to 4 SAM cards, and Health CardReaders that require 2 user cards and 1 SAM card.

The device can interface with any host controller fea-turing an ISO7816 UART such as Atmel’s ARM7, ARM9and ARM SecurCore™ (AT91SO100) devices.Featuring two DC/DC converters and low drop out reg-ulators to power independently each smart card, theAT83C26 is compliant with the EMV and ISO7816standards.

“It is clear that the need to handle multiple smart cardsduring various forms of secure transaction will becomethe norm in the future and the AT83C26 has alreadybeen adopted by a major POS manufacturer for its newapplications,” said Manish Vadher, Marketing Directorfor Microcontroller products with Atmel.

Samples are available now in VQFP48 and QFN48packages. Full production will start in January 2006with pricing starting at $1.95 each for 10K units.

Atmel's AT83C26 product information may be retrievedat: http://www.atmel.com/dyn/products/product_card.asp?PN=AT83C26


Highly Integrated RoHS-compliant SiGe Front-end IC for Private Mobile Radios (PMR)

A new Silicon Germanium (SiGe) based front-end IC,ATR0981, from Atmel, makes the new device easy touse, highly efficient, and extremely flexible The use ofSiGe technology, the simple yet flexible application cir-cuit, and the device’s wide operating frequency range(300 MHz to 500 MHz) make possible a broad range ofapplications, from hand-held family radios (privatemobile radios, PMR) to meter readers. It is easy todesign applications with low external componentcounts using this front-end device because of its highlevel of integration, including a very efficient power

amplifier (PA) and a low-noise amplifier (LNA) for thereceive path.

In contrast to most competitors’ family-radio front-endsolutions, which are designed as discrete solutions, thisdevice is an integrated circuit manufactured usingAtmel’s innovative Silicon Germanium (SiGe) technolo-gy, providing many advantages over discrete or non-SiGe solutions. SiGe ensures high reliability and robust-ness due to low temperature dependency; plus, thecost savings of using the ATR0981 IC go beyond sim-

ply the component cost – lower component count alsoequals decreased design effort, failure risk and assem-bly cost.

What is more, SiGe offers increased efficiency – thePAE value is as high as 55%, typically, helping toensure the low current consumption of the PA. Theoverall current consumption can be reduced even fur-ther by shutting down the PA, providing extended bat-tery life. The output power can reach 29 dBm and thePA has a power gain of 34 dB, controllable within arange of 3 dB. ATR0981’s LNA offers excellent noiseperformance, with a noise figure of 1.5 dB and a powergain of 19 dB. Samples of the ATR0981 are availablenow in PSSO20 packages, which are both Pb-free andgreen. Atmel is the one of very few suppliers offeringthis type of product as an RoHS-compliant device.Pricing for the ATR0981 starts at 1.20 US$ in quanti-ties of 10k.

Atmel’s front-end IC ATR0981 product information maybe retrieved at: http://www.atmel.com/dyn/products/product_card.asp?part_id=3765

LNA = Low Noise AmplifierPA = Power AmplifierPAE = Power Added EfficiencyPMR = Private Mobile RadioRoHS = Restriction of the Use of Certain Hazardous SubstancesSiGe = Silicon Germanium

Atmel's FingerChip Featured in FingerGear's Computer-On-a-Stick Biometric Edition

Atmel, and FingerGear, the consumer products divi-sion of biometrics leader Bionopoly LLC, announcedtoday the release of its groundbreaking BioComputer-On-a-Stick™ USB Flash Drive now withfingerprint security. The Computer-On-a-Stick is theworld's first bootable USB flash drive. The OS and allDesktop Software applications come preinstalledand occupy as little as 200Mb of flash memory. Thedevice also features Atmel's FingerChip® sensor forconvenient and accurate one-swipe secure dataaccess, and a large font LCD display for the ultimateuser-friendly experience.

The FingerGear Computer-On-a-Stick also includesan Office Productivity Suite, along with many of themost commonly used home and office applications.The Office Suite, developed by OpenOffice.org, iscompatible with Microsoft Office™ applications,

including Word™, Excel®, PowerPoint®, andOutlook®. The Computer-On-a-Stick also bundles theincreasingly popular Mozilla FireFox® web browser,now at a 25% market share*, as well as a PDFCreator, a zip compression utility, and an InstantMessenger which communicates with Yahoo® IM,MSN® Messenger, AIM, and Napster®, among others.

The Bio Computer-On-a-Stick includes a USB 2.0extension cable, a neck lanyard, and a mini boot CD.The device is bootable from any PC using an x86processor, which can be found on nearly everyWindows and Linux desktop shipped over the past 5years. Recent PCs allow the user to configure theirsystem to boot directly from a USB Flash Drive with-out the need for a CD. The Computer-On-a-StickStandard and Biometric Editions are currently instock and shipping now. The Computer-On-a-Stick

pricing starts at only $99, and the Biometric Editionstarts at $149.

“The USB standard has experienced one of thefastest adoption rates in the history of consumerelectronics,” said Bionopoly C.E.O. Jon Louis, “Thenext wave of USB devices, led by FingerGear, nowallows you to carry not only your files, but also yourentire Desktop Software Environment as well, essen-tially replacing your hard drive. The Computer-On-a-Stick, and now the Biometric edition, offer the ulti-mate combination of desktop portability andadvanced security.”

For further information on Atmel's FingerChip®, goto: http://www.atmel.com/products/Biometrics/.

*According to W3Schools.com.


Contactless Credit Card Markets Targeted with SecureAVR µC

Atmel’s secureAVR 8-/16-bit RISC microcontrollerprovides 16-bit CPU performance while offeringstate of the art security features. It is now availableas a contactless only product, optimizing perform-ance with smaller die size for price sensitive con-tactless applications. These features includeDFA/DPA/SPA resistant, DES/TDES processor, trueRNG (Random Number Generator), firewalls, andenvironmental protections. The AT90SC6404RFT,

comprising of 64K ROM, 4K EEPROM and 1.2K RAMis a derivative of the popular AT90SC12872RCFTdual-interface chip targeted at e-Passport and IDapplications, but having only a single RF ISO-14443contactless interface. It is ideally suited to theemerging USA Contactless Card Payment marketbased on the standard Credit/Debit magnetic stripeprofile offerings from “American Express(ExpressPay)”, MasterCard® (PayPass™) and Visa®.

The ROM/EEPROM mem-ory sizes provide sufficientcapacity to allow addition-al applications, such asLoyalty or Mass Transit oralternatively as a Physicalor Logical Access contact-less card.

Ian Duthie, Atmel’s SmartCard IC MarketingManager, commented“The success of our firstPayPass product, whichestablished Atmel as aleading IC vendor in theUSA Contactless Card

Payment market, convinced us of the potentialgrowth and need for further product development toserve the USA payment industry. The customer inter-est in the AT90SC6404RFT bears this out; we aresampling now and planning volume productioncapability for 1Q 2006. Preliminary estimates fromour customers indicate that the USA ContactlessCard Payment market will grow from several millioncards this year to 25M+ next year and 40M+ by end2007.”

For further information on Atmel’s secureAVRfamily: http://www.atmel.com/products/Secure AVR

Atmel Achieves Higher Resolutions with2.5M Pixel CMOS Industrial Camera

Atmel has announced the introduction of a new mem-ber of the ATMOS™ area scan CMOS camera familydedicated to industrial machine-vision applications.The additional members ATMOS 2M30 and ATMOS2M60 are fast CMOS area scan cameras able to workin 8, 10 or 12 bits that offers an excellent dynamicrange. Specific CommCam software, also developed byAtmel, renders camera configuration easy.

ATMOS 2M30 and 2M60 are composed of a 2.5 mil-lion pixels CMOS sensor featuring high sensitivity andhigh quality even at maximal speed. The region ofinterest (R.O.I.) allows the end-user to implement infi-nite resolutions and to increase frame rate such as: 48fps full resolution at 2.5M pixels, 60 fps at 2M pixelsand 160 fps in VGA format (640X480 pixels) for the2M60 model (half-speed for the 2M30). Furthermore,the ATMOS 2M30 and ATMOS 2M60 cameras com-prises an electronic shutter and Camera Link® inter-face suitable for those wanting to upgrade from analogto digital modes while offering cost effective solutions.The two ATMOS cameras are delivered in a 44 mm

square section design with a C-mount adapter, amongthe smallest in the market. The performance, versatili-ty and adaptability of the compact mechanical bodygive OEM and integrators an optimum solution to spacesaving in systems. It also allows an implementation intomultiple configurations. The camera can be uploadedremotely.

“With these new members, ATMOS™ camera family

offers an exciting alternative to CCD base cameras,”said Christophe Robinet, Camera Marketing Managerof Atmel’s Professional Imaging. “These cameras allowfor customized solutions on request.”

The ATMOS 2M30 and 2M60 cameras are at samplestage now and will enter their production phase in April2006. Pricing starts at $2500 and $3000 respectivelyfor a quantity of 100 pieces.

Atmel’s product ATMOS 2M30 may be retrieved at:http://atmel.com/dyn/products/product_card.asp?part_id=3802

Atmel’s product ATMOS 2M60 may be retrieved at:http://atmel.com/dyn/products/product_card.asp?part_id=3803

For further information on Atmel’s Camera products, goto: http://atmel.com/products/Cameras/


New Generation of Secure Microcontrollers Released for TrustedElectronic Transaction Terminals

The AT91SO100, a new high-end 32-bit securemicrocontroller for electronic transaction terminalsimproves security and level of integration for POS,PINPads and health card reader applications.

Based on the ARM® SecurCore™ SC100 CPU core,the AT91SO100 achieves an outstanding level ofintegration. This chip featuring 256 Kbytes EEPROMfor program and data, 32 Kbytes ROM and 100Kbytes RAM, provides also USB, SPI, USARTs, I/Oports, magnetic stripe card interfaces plus a securedexternal bus interface. In addition, Atmel offers asmart card interface integration through a singlepackage solution in BGA 256 embedding two chips,

the AT91SO100 and the AT83C26, which physicallyinterface with up to 5 smart cards.

Herve Roche, Atmel’s Smart Card IC MarketingManager stated, “To comply with EMV standard,VISA® PED and others, terminals and readers indus-try require higher security and more performance.Atmel leverages its design expertise in highly securesmart card ICs by providing to its customers themost efficient secure product for EMV migration.”

The AT91SO100 hosts strong security mechanics,including intrusion sensors, dedicated hardware pro-tections, real-time clock and battery backup. It also

has an impressive set of cryptography features,hardware DES/TDES, hardware AES, hardware SHA-n, hardware cryptography accelerator for asymmet-ric algorithms (RSA, Elliptic curves, Key generation)and a true random number generator. Implementedin 0.18-micron embedded technology, this securechip runs a RSA 2048-bit decryption in less than150 ms. It is targeted to achieve Common CriteriaEAL4+ certification. Complete sets of documenta-tion and development tools are available.

For further information on Atmel’s ARMSecurCore™ family, go to: http://www.atmel.com/products/SecureARM

Avnet, Atmel Supercharge Battery Technology Inc.'s Design ProcessWhen Battery Technology Inc. (aka Battery Tech) beganworking on its next-generation of batteries, it enlistedengineering aid from the silicon chip expertise of AvnetElectronics Marketing, a division of Avnet, Inc.(NYSE:AVT) and Atmel® Corporation (Nasdaq: ATML).Together, Avnet and Atmel field application engineers(FAEs), in conjuction with Battery Tech’s internal engi-neering department, created a new line of batteries forlaptop computers that rely on Atmel’s AVR® line ofmicrocontrollers. The AVR features an award winningRISC-based processor core and is the world’s highestperformance, low power 8-bit Flash memory micro-controller.

“With help from Avnet and Atmel, we brought engi-neering in-house and now we control our own designdestiny,” says Andy Tong, Battery Tech, vice presidentof research and development.

The collaborative group effort also resulted in a designthat uses fewer components, has a smaller form fac-tor, and features improved performance. “We created atotal team effort between Atmel, Avnet and BatteryTech,” says Andy Barbosa, Avnet account manager.Rodney McCray, Atmel’s field application engineer,added, “All of this was done to make Battery Tech morecompetitive. We looked at everything to help them

become more competitive – from performance andpower consumption to cost and flexibility.”

Tapping Avnet’s supply chain expertise, Battery Techwas also able to speed the product’s time-to-market.By using Avnet’s Point of Use Replenishment System(POURS), Battery Tech is assured of the right amount ofinventory at exactly the time it’s needed on the pro-duction floor. Today, Battery Tech has plans to migrateadditional products to the same microcontroller plat-form, and it continues to rely on its relationship withAvnet and Atmel in bringing new products to life.

STAFF BOX

Publisher: Glenn ImObersteg

[email protected]

Technical Editor: Markus Levy

[email protected]

Sales Manager:Mike Miller

[email protected]

Production Manager: Dave Ramos

[email protected]

This issue of the Atmel Applications Journal is published byConvergence Promotions. No portion of this publication may bereproduced in part or in whole without express permission, in writ-ing, from the publisher. The contents of this publication areCopyright © Atmel Corporation 2006. All rights reserved. Atmel®,logo and combinations thereof are registered trademarks, andEverywhere You Are™ is the trademark of Atmel Corporation or itssubsidiaries. Other terms and product names may be trademarks ofothers. All product names, specifications, prices and other informa-tion are subject to change without notice. The publisher takes noresponsibility for false or misleading information or errors or omis-sions. Any comments may be addressed to the publisher, GlennImObersteg at [email protected], or +1 (925) 516-6227.

Atmel's New 200 MIPS ARM9 MCU Draws Only 2.5 µA Standby, and 350 µA/MHz at Maximum Performance

Atmel has announced the industry’s first ultra low-power, deterministic microcontroller, the AT91SAM9261 Smart ARM Microcontroller (SAM), based onthe ARM926EJ-S processor.

Targeted at low power, high throughput wirelesshandheld applications, such as wireless PoS devices,

the AT91SAM9261 consumes only 2.5 µAin standby mode. Operating

at 500 Hz it draws 400µA. In industrial temper-ature range, its currentconsumption at 200 MIPSwith all peripherals turnedon is just 65 mA. TheAT91SAM9261's through-

put and its extended instruction set with DSP exten-sions allow complex DSP functions, such as biomet-rics, voice recognition, software modems, or encryp-tion/decryption algorithms like RSA, to be executedvery quickly in burst mode, so the system can be shutdown much of the time.

In a typical PoS application with a four-hour batterylife, such as a rental car-return processing module,these new MCUs can extend battery life by as muchas a factor of 4 to 16 hours.

Packaging and Availability: The AT91SAM9261 isavailable now in a 217-ball LFBGA RoHS-compliantpackage and is priced at sub $10 in high volume.

Atmel’s AT91SAM9261 product information is avail-able at http://www.atmel.com/products/AT91/ or byemail from [email protected].

Atmel Introduces First Power Management IC for Handset Add-on Modules

Add-on modules are a key factor in the marketingstrategy of handset manufacturers. Mobile phones,music players, digital still cameras, PDAs and multi-media devices can add GSM/GPRS, 3G, WLAN,Bluetooth®, GPS, image capture, music playback andother features by simply adding plug-in modules toexisting devices. These modules require a specific reg-ulated power supply interface from the main supply.

Manufactured using Atmel’s low-cost mainstreamCMOS process, the AT73C211 is designed to supplythe digital, analog, interface, and, if required, the RadioFrequency (RF) and backup sections of add-on mod-ules used in hand-held products such as PDAs andmobile phones. The AT73C211 integrates a high-per-formance DC to DC converter with integrated switchesto supply digital cores at 1.9V, delivering up to 300mA.Additionally, three high-current Low Drop Out (LDO) lin-ear voltage regulators supply analog, interface andRFportions of typical multimedia or wireless communica-tion applications, with voltage from 2.7 to 2.8V andcurrent up to 130 mA. An ultra low-power LDO and aback-up battery or supercap charger are also providedto supply the Real-Time Clock (RTC) section that isusually present inside the application processor core.This achieves the lowest current consumption possiblein standby mode. A reset generator and a voltagesupervision function complete the integration of theAT73C211.

“Our AT73C211 is a first in its market,” said MicheleCasetta, Marketing Manager for Atmel’s PowerManagement and Audio Analog Companion PMAAC™Product Line. “The integration of various power supply


channels and an ultra-low-power backup supply chan-nel with a power controller circuit for startup and shut-down, it makes it an ideal companion for every appli-cation where power consumption, cost and space arekey.”

Atmel offers the AT73C211 in a 5 x 5 mm, 25-ballultra-thin BGA package in order to satisfy portabledevice manufacturers’ minimum space requirements.It is available now mounted on a reference designboard or as engineering samples. Production quantities

are also available, with a reference price below $1.00in large quantities.

Atmel’s Power Management product information maybe retrieved at: http://www.atmel.com/products/PowerManage/

For more information about AT73C211 go to:http://www.atmel.com/dyn/products/datasheets.asp?family_id=639

By: Peter Bishop, Communications Manager,Atmel Rousset

The Big Picture: System-on-Chip ChallengesThere is a consensus in the semiconductor industrythat the challenges facing designers of systems-on-chip (SoC) are electronic system level (ESL) design,design for manufacturing (DFM)/design for test (DFT),power management, and the cost, time and risk asso-ciated with SoC development. As a consequence ofthese challenges, there has been a decrease in recentyears in the number of systems-on-chip beingdesigned, offset by the increase in revenue derivedfrom a successful system-on-chip.

Electronic System Level DesignA system-on-chip is almost always built around one ormore microcontroller(s) (MCUs), digital signal process-ing (DSP) core(s) or other software programmable ele-

ment. Accordingly, the software that drives the systemmust be developed concurrently with the hardware,and is at least as costly and time-consuming.

Numerous attempts are being made to develop a uni-fied language to specify the entire SoC (both hardwareand software) at the outset of the design cycle. Theseelectronic system level (ESL) design projects are most-ly based on System Verilog or System C, but to dateneither has been widely adopted in practice. In realitymost SoC hardware and software is developed concur-rently but separately. This causes a number of prob-lems, originating from the differences in culture, train-ing and methodology between hardware and softwaredevelopers. Combined hardware/software testing onlyoccurs late in the design cycle, and the hardware/soft-ware interface is a major source of errors. In additionarchitectural limitations or design errors are oftendetected late in the cycle.


Using ARM Core-based Flash MCUs as aPlatform for Custom Systems-on-Chip

ADVANCES IN PROCESS TECHNOLOGY

ARE MAKING IT POSSIBLE TO FABRICATE

SYSTEMS-ON-CHIP (SOCS) CONTAINING

HUNDREDS OF MILLIONS OF TRANSIS-

TORS OPERATING AT GIGAHERTZ CLOCK

FREQUENCIES IN A FEW TENS OF SQUARE

MILLIMETERS. HOWEVER, THESE SAME

ADVANCES ARE MAKING IT INCREASINGLY

DIFFICULT TO DEVELOP SUCH COMPLEX

SOCS ECONOMICALLY IN AN ACCEPTABLE

TIMESCALE, AND MAKING POWER

CONSUMPTION A CRITICAL ISSUE. YIELD

AND TESTABILITY ISSUES ARE BECOMING

A MAJOR CONCERN. SOCS INCORPORATE

PROGRAMMABLE ELEMENTS

(MICROCONTROLLERS AND DIGITAL

SIGNAL PROCESSORS) MAKING THEIR

SOFTWARE CONTENT AS EXPENSIVE

AND TIME-CONSUMING TO DEVELOP

AS THEIR HARDWARE.

USING A FLASH MCU BASED ON THE

INDUSTRY-STANDARD ARM PROCESSOR

AS A PLATFORM REPRESENTS A

PRACTICAL APPROACH TO SOC

DEVELOPMENT THAT ADDRESSES ALL

THESE ISSUES. INCORPORATING AN FPGA

(FIELD PROGRAMMABLE GATE ARRAY)

PROTOTYPING STEP INTO THE DESIGN

FLOW ENABLES PARALLEL HARDWARE/

SOFTWARE TESTING AND INCREASES THE

CHANCES OF RIGHT-FIRST-TIME SILICON.

ARMProcessor

JTAGScan

VoltageRegulator

System Controller

Advanced Int CtrlPower Mgt Ctrl

Reset Ctrl

Prog Int TimerWatchdog TimerReal Time Timer

Debug UnitPIO Ctrl

PLLOsc

Brownout DtrPower On Reset

RCOsc

PeripheralBridge

SRAM

Flash

FlashProgrammer

Mem

ory

Con

trol

ler

PeripheralData Ctrl

USART0-1

SPI

Two Wire Interface

ADC0-7

USB Device

PWM Ctrl

Synchro Serial Ctrl

Timer/Counter 0-2

PIO

PIO

PIO

ASB/AHB

APB

EBI

Figure 1: ARM-based Flash MCU Platform Architecture

reduce once a process becomes stable), design timesare lengthening in proportion to the transistor count,and increasing design complexity makes errors moredifficult to detect during the design flow.Hardware/software interaction is an increasing sourceof error, and difficult to identify until late in the designflow.

The delay and cost over-run induced by a re-spin cankill a product. Often the market window has closed,particularly for a consumer product, and client dissatis-faction can lead to cancelled orders or worse.

An ARM-based Flash Microcontroller as an Architecture PlatformUsing an ARM-based Flash microcontroller as an archi-tecture platform for the development of a custom(application-specific) SoC is a practical approach thataddresses all the challenges outlined in the previoussections. It takes advantage of available designmethodologies and fabrication technologies, while giv-ing a higher performance than the previous approachof testchips-plus-FPGA for dedicated logic. It enablesparallel hardware and software development, with theadditional advantage of software implementation onembedded Flash (as opposed to ROM) that facilitates

bug fixes and upgrades to meet evolving interfacestandards. The design cycle is short (months instead ofyears for an SoC designed from scratch) and the exten-sive re-use of IP blocks makes it cost-effective. It is anapproach based on years of experience and multiplesuccessful SoC products.

ARM-based Flash MCU Platform ArchitectureThe general-purpose architecture of an ARM-basedMCU platform (Figure 1) is characterized by a high levelof system integration. It embeds an ARM processorcore together with Flash memory for program and ref-erence data storage and an SRAM workspace. Anexternal bus interface (EBI) provides high-speed accessto external memories or memory-mapped devices suchas FPGAs to emulate custom logic.

The system controller includes a number of elementsthat until recently were off-chip, notably oscillator/PLL,voltage regulator, reset controller, brownout detectorand power-on-reset. An advanced interrupt controller(AIC) reduces interrupt latency, enhancing the real-timeperformance of the system. The system controller alsoincludes the power management controller that is thecentral clock source to the entire device.


It is recognized that ESL design is essential in reducingthe time-to-market of the end-user product.

Design for ManufacturingDesign for manufacturing (DFM) implies taking intoaccount issues that influence yield and device charac-teristics during the logical and physical phases of thedesign cycle. It involves “feeding forward” processissues into design steps that have traditionally beenprocess-independent. The first area to be impacted hasbeen timing closure and the identification of critical sig-nal paths. Physical synthesis has been helpful inaddressing this, but is not a panacea.

Analog characterization is a major area of difficulty, asis that of embedded Flash memory. The process com-promises required in embedding Flash into mainstreamCMOS technology give rise to problems ofendurance/data retention. There is also the practicalissue of the time taken for Flash programming, oftencarried out as an integral part of the test cycle.

Yield optimization is generally carried out by processrefinement after successive iterations of a product onceit is in volume production. This can be expensive unlessan acceptable yield level is achieved reasonably rapidly.

Design for TestDesign for test (DFT) is well understood for digital logic,where scan insertion/automatic test pattern generation(ATPG) is the norm. Built-in self-test (BIST) for embed-ded memories is less common now than a decade ago.Accordingly, the time taken in testing of embeddedFlash memory can be a major issue unless adequateprovisions such as parallel testing are made.

Power ManagementWasted power drains supplies by generating heat, bothof which are undesirable. The problem is becomingmore significant with smaller transistor geometries, inparticular static leakage current due to reduced gatethickness. Higher clock speeds lead to a proportionalincrease in dynamic power consumption.

A number of approaches to power management are invogue, including partitioning the device into separatevoltage islands and clock domains. These enable theclock to be slowed or stopped in under- or unusedblocks (to reduce dynamic power consumption), andunused blocks to be powered down (to reduce staticpower consumption). In extreme cases the entire SoCcan be put in power-down mode except for its real-timeclock, but the time taken to wake up from low-powermode can be an issue.

It is essential to integrate a device-wide power man-agement methodology into the design of an SoC fromthe outset; it cannot be grafted on as an afterthought.

Development Cost, Time and RiskThese are all becoming more significant with smallergeometries: mask costs are escalating (although they

ARMProcessor

JTAGScan

VoltageRegulator

System Controller

Advanced Int CtrlPower Mgt Ctrl

Reset Ctrl

Prog Int TimerWatchdog TimerReal Time Timer

Debug UnitPIO Ctrl

PLLOsc

Brownout DtrPower On Reset

RCOsc

PeripheralBridge

SRAM

Flash

FlashProgrammer

Mem

ory

Con

trolle

r

PeripheralData Ctrl

USART0-1

SPI

Two Wire Interface

ADC0-7

USB Device

PWM Ctrl

Synchro Serial Ctrl

Timer/Counter 0-2

Ethernet MAC CAN

PIO

PIO

PIO

ASB/AHB

APB

EBI

Application-SpecificLogic

Figure 2: Application-specific SoC Derived from ARM-based Flash MCU Platform


External communication is via industry-standard inter-faces such as USB, SPI, etc. Data throughput isenhanced by peripheral DMA controller (PDC) channelsthat link each external interface directly with the mem-ory, enabling data transfers to take place with noprocessor intervention. A multi-channel ADC enablessensors and other analog devices to be directly con-nected. A parallel I/O controller multiplexes theinput/outputs from the communications interfaces witha number of general-purpose I/O lines, significantlyreducing the device pin count.

Modular AMBA-compliant IP BlocksThe intellectual property (IP) blocks that make up theARM-based SoC are all separately designed, validatedand documented. They are designed for re-use, eitherin-house or externally by qualified sub-contractors.They are characterized on-silicon, in particular thecharacteristics of the analog and Flash memory blocksare determined. Software device drivers, real-timeoperating systems and communications protocolstacks are developed and tested in parallel. The indus-try-standard ARM core facilitates software develop-ment via the re-use of legacy code and the availabilityof a wide range of software development tools, portedoperating systems and support.

Synthesized, Fabricated and CharacterizedPlatformThe ARM-based Flash MCU platform is created by inte-grating the qualified IP blocks around the ARM core.The platform is synthesized, timing closure is achieved,critical paths are dealt with and power consumption isoptimized by fabricating the device and marketing it asa standard product, with successive silicon iterationsfor yield enhancement. The device is validated in mul-tiple applications by diverse clients.

Transformation to Application-specific System-on-ChipThe generic ARM-based Flash MCU platform is trans-formed into an application-specific device (Figure 2) by

adding or removing communications interfaces, and bybuilding in an application-specific logic block. The EBIor one of the high-speed serial interfaces is used toconnect external memory-mapped devices. Datathroughput is enhanced by the DMA capability thatreduces processor performance loss to a few percentduring bulk data transfers. The application-specific SoCis emulated on an FPGA-based development platformbefore fabrication, as described in a later section.

SoC Design Flow Based on Architecture andEmulation Platforms The System-on-Chip design flow shown in Figure 4 isbased on parallel hardware and software development.Its starting point is the architecture platform pre-builtfrom generic hardware and software IP blocks thathave already been characterized and debugged, asdescribed in previous sections.

The key steps are to partition the hardware and soft-ware of the application-specific system, using theexisting hardware/software IP blocks as a guide. Thenfollows the development of any application-specifichardware and software IP blocks that are required.These are integrated, together with an operating sys-tem if needed, into the architecture platform and asso-ciated software. After synthesis and simulation, thehardware and software of the application-specific sys-tem are emulated on an FPGA-based emulation plat-form.

Emulation Platform ArchitectureThe central feature of the emulation platform (Figures 5and Figure 6) is a high-density FPGA onto which aremapped the application-specific logic and any non-standard communications interfaces. An on-boardclock generator provides all the required timing

Figure 3: System-on-Chip with embedded MCU andMemory Blocks

OperatingSystem

SpecifySystem-on-Chip

PartitionHardware/Software

Hardware/SoftwareVerification on

Application Prototypeor Development Board

Integrate Application-specific IP Blocks into Architecture

Platform

IntegrateSoftware

IP Modules

Hardware and Low-levelSoftware Emulation on FPGA-based

Emulation Platform

Hardware/SoftwareCo-simulation

PrototypeIC Fabrication

PhysicalDesign

ApplicationSoftware

Development

VolumeIC Fabrication

SoftwareTest

FunctionalSimulation

SoftwareSimulation

GenericHardwareIP Blocks

GenericSoftware

IP Modules

Parallel Development of Hardware IP Blocks

Parallel Development ofSoftware IP Modules

Ship ICs and Software to Clients

ArchitecturePlatform Select

ArchitecturePlatform

Application-specific

HardwareIP Blocks

Application-specific

SoftwareModules

Select Software IP

Modules

Figure 4: SoC Design Flow


sources. There are connections to mezzanine board(s)that host the architecture platform(s), and both on-board and external memories. There are also connec-tions to custom interface boards, and an extensive setof user switches, displays, LEDs and buttons. There areinterfaces (including PHYs) for USB, Ethernet, RS232and other standards, as well as external user I/O pins.

Emulation Key StepsThe first step is to map the Verilog or VHDL code of theapplication-specific IP block and any non-standardcommunications interfaces onto the FPGA. The archi-tecture platform(s) are available on plug-in mezzanineboards (Figure 7). These, and any custom interfaceboards are connected to the emulation platform, whichis in turn linked to the development PC.

The development software, comprising at least the low-level device drivers, operating system and basic func-

tional modules, is loaded on the PC, from where it isrun and debugged using an industry-standard develop-ment system. Although the emulation board cannotgenerally achieve the full operational speed of the tar-get device, it is orders of magnitude faster than a sim-ulation, and enables functional behavior to be investi-gated, rather than just simulation test patterns.

Should any errors be detected, they are correctedeither by modifications to the Verilog/VHDL code of theIP blocks, or by modifications to the device drivers orhigher-level software. The sequence of test/correctioncontinues until all errors have been identified and elim-inated.

Emulation BenefitsEmulation provides many benefits. The most importantis to be able to use the software to drive the hardwareat close to operational speed. This tests real-time

behavior such as interrupt handling that is almostimpossible to simulate. For the first time in the designcycle, the hardware/software interface can be thor-oughly tested.

Errors are corrected and re-tested rapidly and at mini-mal cost. There are no masks to re-make or fabricationre-spins to correct prototypes. The savings in time andcost are significant.

Finally, the debugged emulation system corresponds tothe fabricated devices. It can be used as the startingpoint for upgraded versions of the system-on-chip(both hardware and software).

Platform-based SoC Design: How Does it Rate?How does the use of an ARM-based Flash microcon-troller platform measure up to the challenges of SoCdevelopment listed at the start of this article?

Electronic System Level DesignPlatform-based SoC design does not use a unifiedelectronic system-level design language, but it doesaddress the key issue of hardware/software designpartitioning. The use of pre-qualified hardware/soft-ware IP blocks guides and simplifies design partition-ing, and the architecture platform provides a system-level starting point. The emulation of the entire hard-ware/software system relatively early in the designcycle resolves many ESL design issues before fabrica-tion. The use of Flash memory ensures that softwaremodifications can be incorporated late in the designcycle, or even as field upgrades.

Design for Manufacture/TestThe architecture platform is implemented on silicon asa standard product, which means that timing closureand critical path issues are already addressed. Analogand embedded Flash characterization is alreadyachieved. Yield enhancement by process optimization isalready accomplished, or yield data from the platformcan be taken into account in the fabrication of theapplication-specific device. The major test issues, gen-erally concerning the analog and embedded Flash, arealready resolved in the test regime for the architectureplatform. All these factors increase the probability of aright-first time application-specific SoC with an accept-able yield starting from the first production batch.

Power ManagementThe principles of power management, including anintegrated power management controller, are incorpo-rated in the architecture platform. The IP blocks are alldesigned for compatibility with the power managementcontroller, and these design principles are easilyextended to the application-specific logic and any ded-icated interfaces. These include the provision of clockand voltage domains, and the establishment of stand-by or power-down modes where appropriate. The resultis an application-specific device with optimal powerconsumption in all modes of use.

Mezzanine 1Connectors

Mezzanine 2Connectors

High-Speed/LVDS EdgeConnectors

PCIExtension

Slot

DIN41612Extension

Connector (VME)

Power CyclePush-button

PC-ATXPower

Input

Warm ResetPush-button

JTAG

JTAG

ExternalClock Input

UserPush-buttons

UserDIP Switches

User Rotary Selectors

Extension Connectors

System Memory

RJ45RJ45

USB HostUSB DeviceUSB On-the-Go

CAN 1CAN 2

Serial FullSerial Minimal

TWI

QWI

Speaker OutputMic/Line Input

Sta

ndard

Inte

rface

s

Pow

er

Managem

ent

FP

GA

Config

ur-

atio

nC

lock

ing

Use

r In

puts

VoltageRegulators

Reset Gen

System ACE(Embedded Flash &

Config Ctrl)

User Clock

ProgrammableTriple Digital

PLL

TCXO

Debouncer

Debouncer

12V5V3.3V2.5V1.8V1.5V

ResetNReset

Xilinx Virtex IIXC2V8000 FPGA

500K GateAsic Equivalent

67584 Flip-flops

16 GlobalClock Paths

2.5 Mbit SSRAM

12 Digital ClockManagers (PLL)

12 18x18 Multipliers

1104 User I/O Ports

Ethernet PHY

USB 1.0/2.0PHY

USB 1.0 PHY

XMatrix

CAN PHY

CAN PHY

RS232 LevelShifters

Amplifier

Line Adapter

4-digitLED Display

LED Bar

FreeUser I/O

512K x 32ZBT

SSRAM

32-bit DDR-SDRAM Slot

32-bit SDRAM Slot

Xtal

(Dual Mounting)

50 MHz

1 to 200 MHz

Use

r O

utp

uts

/C

onnect

ions

DAC

ADC

Figure 5: Emulation Platform Architecture


Design Cost, Time and RiskThese are all significantly reduced by starting from analready-fabricated architecture platform with re-use ofqualified hardware/software IP blocks. The emulationphase enables the custom hardware and software driv-ers to be thoroughly debugged at minimal cost. Theembedded Flash memory enables software upgradesat minimal cost, even in the field.

ConclusionAn ARM-based Flash microcontroller can serve as anarchitecture platform for the development of an appli-cation-specific system-on-chip. The design flow basedon its use addresses all of the issues of system-on-chipdesign, contributing to lower development cost andrisk, and increasing the chances of right-first-time sili-con with an acceptable yield.Figure 6: Atmel’s Mistral Emulation Platform Figure 7: Mezzanine Board for ARM-based

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ply selects the serial Flash, sends it one command tostart reading the memory, and then continues to clockthe serial Flash until all of the necessary code has beenoutput. The serial Flash is designed to be read sequen-tially and incorporates an internal address counter sothat every clock cycle will output the next bit of data.

In order to minimize boot time, shadowing code intoRAM requires relatively fast transfers from the Flash,especially as code densities increase. A common mis-conception in the industry is that serial equates to slowperformance, but that simply isn’t true anymore.Today’s PCs, for example, incorporate a host of somevery high-speed serial interfaces such as PCIExpress™, serial ATA, USB 2.0, and IEEE1394/FireWireTM.

Atmel Corporation, with its AT26 and AT45 seriesDataFlash® family of serial Flash, currently offers theindustry’s highest speeds at 66 MHz. These devicesare capable of sustaining read throughputs at a veryfast 66 Mbps, or 8.25 MB per second, which is equiv-alent to a 120 ns 8-bit parallel Flash. With such highthroughputs, an entire 64 Mbit device can be read inless than one second. A lower density device, such asan 8 Mbit can output the entire contents of its memo-ry in a mere 127 ms.

Increasing PerformanceThe performance requirements of today’s applicationscontinue to increase, despite the seemingly simplisticnature of some of these applications. The performanceincreases generally arise from the incorporation ofadditional and improved features in the applications orimproved data transfer rates and processing through-put. As the performance requirements increase, theaccess times (45 ns+) of traditional XiP parallel Flashsimply aren’t fast enough to directly execute the pro-gram code. In such instances, either external RAM orembedded RAM in the ASIC or processor must be usedto execute the code since the RAM access times aremuch faster than Flash, especially when consideringDDR type SDRAM.

With embedded SRAM technology, sub-10 ns accesstimes can be achieved, and the data paths from theSRAM array to the processor core in an embeddeddesign are, of course, very short. With external DDRSDRAM, read throughputs of 400 MB per second areeasily achievable, which are faster than what any typeof XiP parallel Flash in production today can offer, eventhe fastest burst-mode type Flash.

Saving Cost by ShadowingIn a code shadowing application, the code can bestored compressed in the Flash and decompressedduring the shadowing process. With today’s algo-rithms, compression rates as high as 2.5-to-1 can beachieved, thereby effectively halving the density of

By: Richard De Caro, Atmel Corporation

Since it’s inception in 1997,the serial Flash market hasgrown at an incredible rate and is rapidly becoming theFlash memory of choice in many applications oncedominated by parallel NOR Flash. Developed initiallyfor the nonvolatile data storage segment, serial Flashhas since found it’s way into the much more lucrativeand high volume code storage market.

As applications evolve, the code storage landscapecontinues to change, driving more and more appli-cations away from traditional parallel Flash andtowards code shadowing with serial Flash. Threevery important factors are fueling this migration:

the need to increase system performancebeyond what execute-in-place (XiP) parallelFlash can accommodate, the need to reducetotal system cost, and of course the need toreduce system pin counts.

Applications that shadow code from serialFlash are not extravagant, high-end, or one-off

designs. They are, on the contrary, high-volume,everyday consumer applications that can be foundeverywhere. Listed below are just some of the appli-cations currently code shadowing with serial Flash:• Desktop and notebook PCs• Hard disk drives• CD-ROM/CD-RW drives• DVD-ROM/DVD±RW drives• Video graphics cards• Gigabit Ethernet (GbE) LAN controllers• DSL modems• Wireless LAN (WLAN) routers/access points• Inkjet and laser printers (including all-in-one multi

function units)• DVD players and recorders• Video game system remote controls• Radar detectors• Household alarm systems

Shadowing Code is Fast and EasyThe concept of shadowing code into RAM is not a newone. PCs, for example, have been shadowing codepractically since their beginning. Aside from increasesin device density, the only thing that has changed overtime is the type of nonvolatile memory that the code isshadowed from, whether it be EPROM, parallel Flash,Firmware Hub/Low Pin Count Flash, or serial Flash.

Shadowing code from serial Flash is extremely simple,and it can be effortless since native boot support isbeing added to more and more third-party chipsets.With native boot support, the downloading of code fromthe serial Flash to RAM is automatically handled at sys-tem power-up. In applications being developed withcustom ASICs, implementing the shadow process isvery easy. After the system powers up, the ASIC sim-


The Explosive World of Serial FlashDesigner’sCornerDesigner’sCorner


Flash needed to store the code compared to whatwould be needed for direct code execution. In an XiPscenario, it is generally not possible to store the codecompressed because it would have to be decom-pressed “on the fly” while being executed, which wouldseverely degrade system performance.

In many applications, a portion of the system SDRAMmay not be used as work/scratchpad memory and canbe used to store uncompressed shadowed programcode. Therefore, the total system cost can be reducedby compressing the code, halving the Flash density, andkeeping the SDRAM density the same as what would beused in an XiP scenario. Dynamic shadowing, in whichspecific subroutines are pre-fetched and shadowedonly when needed, can also be incorporated to reducethe amount of SDRAM needed to store the shadowedcode.

If the uncompressed code cannot fit into unusedSDRAM space, then in many instances, it is still morecost effective to double the SDRAM density rather thandouble the Flash density because of SDRAM’s lowercost per bit factor. This is especially true when consid-ering high density parallel NOR Flash such as a 128-Mbit and the cost increase that would be incurred ifforced to jump to a 256 Mbit device.

Serial Flash Reduces System Pin Counts and CostLooked at any way, pins aren’t free, whether it’s leadson a package, traces on a PCB, I/O buffers and logic inan ASIC, or bond pads on a die. The desire of everysystem designer, and for that matter every ASIC andcontroller designer, is to keep the number of used pinsto a minimum. Using serial Flash for code shadowingcan significantly help in this area. For example, in asystem with 32 Mbits of code, 36 pins can be trimmedoff the ASIC/controller by using serial Flash and elimi-nating the 16-bit parallel Flash bus.

A savings of 36 pins translates into cost reductions in

many areas. Many ASIC/controller designs are padlimited in that the number of bond pads dictates howlarge the die is rather than the amount of gates usedfor the core and logic. Eliminating 36 bond pads allowsfor a much more compact ASIC/controller design thatresults in a reduced die size which lowers the die costand increases the die per wafer count. In addition,reducing the number of active pins allows the use oflower pin count packages and reductions in assemblyand package costs. For example, a $0.30 to $0.50assembly and package cost savings per unit can easi-ly be realized by going from a high pin-count BGA to alower pin-count QFP. With smaller and lower pin-countpackages comes reduced PCB areas and simplifiedrouting, both of which help lower system costs.

Of course, the package size of the Flash device itselfalso drastically changes when going from large 40-,48-, or 56-lead TSOPs used for parallel Flash to 8-leadSOICs used for serial Flash. A 48-lead TSOP, which isused for 32M (x16) parallel Flash, uses 240 mm2 ofPCB area. A 32 Mbit serial Flash in an 8-lead pack-age, on the other hand, uses a very small 48 mm2 ofboard area. This savings in board space again helps

lower the system cost and allows for a more compactPCB design.

Is the Future Serial Flash?Increased system performance by code shadowing, thepositives of storing code compressed, reduced ASICand controller pin counts, less board space…the listgoes on. Serial Flash brings a number of advantagesover parallel Flash, so it’s no wonder designers aremaking the migration to serial Flash. In today’s com-petitive environment, designers must investigate andimplement new technologies and architectures toreduce their time to market and give them a cost com-petitive product. Is serial Flash that new technology?Most definitely, and one thing is for sure, serial Flash is

here to stay and is already changing the landscape ofcode storage.

Richard De Caro is the Director of Strategic Marketingfor Nonvolatile Memory Products at Atmel Corporationin San Jose, California. For more information onAtmel’s serial DataFlash products, go towww.atmel.com.

Pad limited whenusing Parallel Flash

Optimized by usingSerial Flash

ASIC/Controller Die

sensor to a PC via the Internet), and greatly reducesnetwork complexity, while increasing device interoper-ability.

As the Ethernet protocol reaches deeper into theembedded world, it will become a mandatory compo-nent of embedded systems networks. Controllers, suchas Atmel’s SAM7X Smart Advanced Microcontroller,include a 10/100-Mbps IEEE 802.3-compliant Ether-net media-access controller (MAC) on chip, as well asCAN, USB, SPI, TWI, UART and USART interfaces. TheEthernet MAC can be configured in full- or half-duplexmodes and has a dedicated DMA controller thatensures maximum 100 Mbps throughout. The EthernetMAC also offers programmable interpacket gap, sup-port for virtual-LAN tagged frames and automatic-pause frame generation and termination. A dual modeinterface allows the device to connect seamlesslythrough either a Media Independent Interface (MII) or aReduced Media Independent Interface (RMII) interface,allowing a large selection of PHYs in Fast Ethernetapplications. The MII offers a wider choice of PHYs,while the RMII frees I/Os on the microcontroller for theapplication. These MCUs can be interfaced directly withPOS-PHY Level 2/SPI-3-compliant devices, includingstandard network processors. On-chip system buffersoffer lossless flow-control, eliminating the need forexternal memory and a flow-control mechanismreduces port congestion and traffic loss. Jumbo framesof up to 10240 bytes are supported.

A dedicated DMA controller connects the EthernetMAC to the MCU memories via the SAM7X AdvancedSystem Bus (ASB) bus interface. The DMA controllercontains 28 byte receive and transmit FIFOs for buffer-ing frame data. It loads the transmit FIFO and empties

By: Jacko Wilbrink, Dany Nativel, andTim Morin, Atmel Corporation

Trends in Embedded ConnectivityThe evolution of embedded systems to embedded net-works radically changes the architectural requirementsof embedded microcontrollers. The MCU must inter-face to multiple networking protocols. It must be ableto transfer and verify large amounts of data. It mustprovide security. It must have sufficient memory den-sity and processing power to accommodate all the var-ious protocol stacks and, in many cases, it must dothese tasks while consuming a minimal amount ofpower. And, it must do all these things while providingthe determinism required for real-time applications.

In environments where the number of networkeddevices is increasing rapidly, cable lengths and band-width requirements increase exponentially. Lowerbandwidth networks, such as CAN, which has a maxi-mum bandwidth of 1Mbps, are facing their limits andare beginning to be replaced by higher bandwidth 100Mbps Ethernet networks. CAN will remain a factor inembedded networks for sometime, and ZigBee isexpected to make substantial inroads into low data ratecontrol applications. For communication with a PC,USB has become the standard.

Ethernet is the most widely used and best understoodnetworking protocol around. Extending it into theembedded space offers a great opportunity to provideseamless communications within the local network andwith the Internet. Since both Ethernet and the Internetuse the TCP/IP communication protocol, implementingEthernet in the local network eliminates the need forprotocol conversions (e.g. when connecting a remote


Networked Networks and EmbeddedMicrocontroller Architectures

Figure 1: Embedded Networks

EMBEDDED SYSTEMS USED TO BE DEEPLY

EMBEDDED INSIDE END PRODUCTS. THEY

WERE ONLY RARELY CONNECTED TO THE

OUTSIDE WORLD. THE MICROCONTROLLER

WORKED IN A FAIRLY CLOSED SYSTEM

POLLING PERIPHERALS, COLLECTING

DATA, PERFORMING SIMPLE PROCESSING

AND TURNING SWITCHES AND LEDS ON

AND OFF. THERE WAS LIMITED DATA

MANIPULATION OR DATA TRANSFER. THEY

WERE NOT CONNECTED TO A LAN OR THE

INTERNET. SECURITY WAS NOT AN ISSUE.

THAT’S CHANGED. TODAY, EMBEDDED

SYSTEMS ARE FREQUENTLY NETWORKED

USING CAN, 802.15.4 OR EVEN ETHERNET

PROTOCOLS. THESE LOCAL NETWORKS

ARE IN TURN CONNECTED TO OTHER

NETWORKS AND TO THE REST OF THE

WORLD VIA THE INTERNET. AS EMBEDDED

CONTROL SYSTEMS BECOME MORE NET-

WORKED, EMBEDDED MICROCONTROLLER

ARCHITECTURES WILL HAVE TO ADAPT TO

PROVIDE THE BANDWIDTH, CONNECTIVITY

AND SECURITY MANDATED BY ANY

EXTENSIVELY CONNECTED SYSTEM.

THIS ARTICLE TAKES A CLOSER LOOK

AT TODAY’S NETWORKED EMBEDDED

SYSTEM AND THE CRITICAL ROLE

THE MICROCONTROLLER ARCHITECTURE

PLAYS IN CONNECTIVITY, POWER

MANAGEMENT AND SECURITY.

Local Controland Monitoring

Ethernet

PLC PLC

Control ServerFirewall

InternetRemoteAccess

Servo-Drive

Servo-DriveServo-Drive

Servo-Drive

ActuatorActuator

Actuator Actuator

Bring TCP/IPDown to the Node

Secure RemoteAccess over Internet

CommunicationBandwidth


the receive FIFO using ASB bus master operations.Receive data is not sent to memory until the addresschecking logic has determined that the frame should becopied. Receive or transmit frames are stored in one ormore buffers. Receive buffers have a fixed length of128 bytes. Transmit buffers range in length between 0and 2047 bytes, and up to 128 buffers are permittedper frame. The DMA block manages the transmit andreceive frame buffer queues. These queues can holdmultiple frames.

Frame data is transferred to and from the Ethernet MACthrough the DMA interface. All transfers are 32-bitwords and may be single accesses or bursts of 2, 3 or4 words. Burst accesses do not cross 16-byte bound-aries. Bursts of 4 words are the default data transfer;single accesses or bursts of less than four words maybe used to transfer data at the beginning or the end ofa buffer.

At 100 Mbps, it takes 960 ns to transmit or receive 12bytes of data. In addition, six master clock cycles shouldbe allowed for data to be loaded from the bus and topropagate through the FIFOs. For a 60 MHz masterclock this takes 100 ns, making the bus latencyrequirement 860 ns.

The only wrinkle is that, using a public communicationnetwork, such as the Internet radically increases theneed for security. Advanced encryption algorithms andsecure keys are mandatory.

Networking Mandates Data SecurityTransferring megabits of control data over the Internetor any other open network poses serious security prob-

lems because it opens up access to those embeddedsystems. You wouldn’t want an outsider messing withyour building security or HVAC systems. And you reallywouldn’t want anyone to get into the utility system andshut down the power grid, or release all the water froma dam on short notice, or open a valve on a gaspipeline.

Therefore, access to embedded networks must becontrolled and data must be encrypted. Encryption iscomputationally intensive. The Advanced EncryptionStandard (AES), Data Encryption Standard (DES), andTriple Data Encryption Standard (TDES) are FederalInformation Processing Standard (FIPS)-approvedcryptographic algorithms that can be used to protectelectronic data. AES supports five confidentiality modesof operation for symmetrical key block cipher algo-rithms (ECB, CBC, OFB, CFB and CTR), as specified inthe NIST Special Publication 800-38A Recommen-

dation. TDES supports four different confidentialitymodes of operation (ECB, CBC, OFB and CFB), as spec-ified in the FIPS Publication 81.

AES Encryption The AES algorithm is a symmetric block cipher capableof using cryptographic keys of 128 bits to encrypt anddecrypt data in blocks of 128 bits. Encryption convertsdata to an unintelligible form called cipher text.Decrypting the cipher text converts the data back intoits original form, called plain text. The CIPHER bit in theAES Mode Register allows selection between theencryption and the decryption processes. This 128-bitkey is defined in the Key Registers. The input to theencryption processes of the CBC, CFB, and OFB modes

includes, in addition to the plaintext, a 128-bit datablock called the initialization vector. The initializationvector is used in an initial step in the encryption of amessage and in the corresponding decryption of themessage. The Initialization Vector Registers are alsoused by the CTR mode to set the counter value.

The AES supports Electronic Code Book (ECB), CipherBlock Chaining (CBC), Output Feedback (OFB), CipherFeedback (CFB), with 8-, 16-, 32-, 64- or 128-bit datasegments, and Counter (CTR). The data pre-process-ing, post-processing and data chaining for the con-cerned modes are performed automatically. Thesemodes and the encryption/decryption start modes areselected by setting fields in the AES Mode register.

DES/Triple DESThe DES standard uses a 64-bit encryption/decryptionkey to operate on 64-bit blocks of data. Triple DES usesthree DES keys, referred to as a key bundle. Thesethree 64-bit keys are defined, respectively, in the Key1, 2 and 3 Word Registers In Triple DES mode a bit inthe TDES Mode Register is used to choose between atwo- and a three-key algorithm. In three key triple DESthe data is first encrypted with Key 1, then decryptedusing Key 2 and then encrypted with Key 3, then de-/encrypted in reverse order. In two-key mode, the dataare first encrypted with Key 1, then decrypted usingKey 2 and then encrypted with Key 1.

The input to the encryption processes of the CBC, CFB,and OFB modes includes, in addition to the plain text,a 64-bit data block called the initialization vector (IV),which must be set in a register. The initialization vectoris used in an initial step in the encryption of a messageand in the corresponding decryption of the message.

TDES supports the similar modes to AES, except it hasno 128-bit CFB mode.

Software or Hardware Security?Based on the number or encryption steps and/or thesize of the keys, encryption can be a particularly com-pute-intensive activity, frequently overwhelming theresources of even 32-bit processors. For example, anARM7 Family processor can execute software AESencryption at 4.7 Mbps. This is not nearly fast enoughto keep up with even a 12 Mbps full-speed USB con-nection, much less that 25 Mbps data rates of SPI andTWI. Even at 4.7 Mbps, the ARM7TDMI® processorends up becoming a dedicated encryption processor,limiting its ability to do anything else.

Clearly, the optimal solution is to embed the encryptionengine directly on the processor itself. This solution notonly speeds up encryption. It also frees up the CPU todo its embedded control job. For example the embed-ded encryption engine on Atmel’s SAM7X executesAES encryption at 20 Mbps, DES at 11.2 Mbps and

Embedded ICE

ARM7TDMICore

MemoryController

32 bit Flash128K - 256KB

32 bit SRAM32K - 64KB

ASB

APB

POR/BOD

1.8VLDO

SPI SPI TWI DebugUART USART USART

USBDevice

SSC CAN EthernetMAC10/100

AES

3DES

AIC

Timerx3

PWMx4

PIO

10-bitADCx8

SAM-BAFFPIXTALOSC

RCOSC

PLL WDT

PMCRTT

PIT

PeripheralDMA

Controller

AT91SAM7X

AMBA Bridge

1 Refer to the NIST Special Publication 800-38A Recommendation for more complete information.

Figure 2: SAM7X Block Diagram

that directly transfers data between the peripheralsand the chips internal and external memories. MostSAM7X peripherals have two dedicated PDC channels,one each for receiving and transmitting data. The userinterface of a PDC channel is integrated in the memo-ry space of each peripheral, and contains a 32-bitmemory pointer register, a 16-bit transfer count regis-ter, a 32-bit register for next memory pointer, and a16-bit register for next transfer count. The peripheralstrigger PDC transfers using transmit and receive sig-nals. When the first programmed data block is trans-ferred, an end-of-transfer interrupt is generated by thecorresponding peripheral. The second block datatransfer is started automatically and the processing of

the first block can beperformed in parallelby the ARM proces-sor, thereby remov-ing heavy real-timeinterrupt constraintsto updating the DMAmemory pointers onthe processor, andsustaining high-speed data transferson any peripheral.

It is possible, at anymoment, to read thelocation in memoryof the next transferand the number ofremaining transfers.

The PDC has dedicated status registers which indicateif the transfer is enabled or disabled for each channel.

When the peripheral receives an external character, itsends a Receive Ready signal to the PDC which thenrequests access to the system bus. When access isgranted, the PDC starts a read of the peripheralReceive Holding Register (RHR) and then triggers awrite in the memory. After each transfer, the relevantPDC memory pointer is incremented and the numberof transfers left is decremented. When the memoryblock size is reached, the next block transfer is auto-matically started or a signal is sent to theperipheral and the transfer stops. The sameprocedure is followed, in reverse, for trans-mit transfers.

If simultaneous requests of the same type(receiver or transmitter) occur on identicalperipherals, the priority is determined bythe numbering of the peripherals. If transferrequests are not simultaneous, they aretreated in the order they occurred.Requests from the receivers are handledfirst and then followed by transmitterrequests.

To ensure that the DMA transfers operatecontinuously, at speed, the PDC is config-


triple DES at 12.8 Mbps, pretty much independently ofthe CPU, while leaving 99% of the processor’sresources free for other things.

Moving the Data Around.Embedded MCU applications linked to a network mustbe able to deal with both communications and controlchores and give the programmer as much control aspossible over those operations. They also must be ableto provide seamless and endless transmission betweenmemory and the peripheral devices with no interrup-tions. You don’t want a transmission counter to expire.Direct the processor to do something else while itresends and then comes back to the stack.

DMA is not native to the ARM7TDMI® processor. TheCPU itself transfers data one byte at a time. Thus, datarates can be very slow and they consume processingresources that are needed for the embedded controlfunction. This is fine, as long as the quantity of databeing transferred is relatively small. However, as datarates exceed one million bits per second (Mbps), evenfast processors start to bog down. For example, at 50MHz, a one Mbps data transfer uses 28% of anARM7TDMI processor resources. A 2 Mbps data trans-fer uses more than half the ARM7 processorresources, and at 4 Mbps, the processor is not avail-able for any other activity.

When you consider that the data rate for full speedUSB 2.0 is 12 Mbps, the CAN data rate is 1 Mbps,Ethernet at 100 Mbps and SAM7 SPI and USARTperipherals can run at 25 Mbps, it becomes quite clearthat the issue of data transfer must be dealt with in anyextensively connected embedded control system. Inapplications where there is a lot of data to movearound, can the microcontroller act as both a gatewayAND a controller?

Atmel has augmented the ARM7 Family processorarchitecture with a peripheral DMA controller (PDC)

Peripheral Peripheral DMA Controller

THR

RHR

Control

PDC Channel 0

PDC Channel 1

Status & Control

Control MemoryController

Figure 3: PDC

ured so that when one counter expires, the PDC down-loads the next counter into the current register, gener-ates an interrupt and updates the next counter. Onecounter-register set is used for the initial transfer andthe other set for the next transfer, allowing the pro-grammer to ping pong the DMA count and simulate anendless DMA transfer of data to the peripherals with-out interruption.

Unlike traditional DMA structures, PDC transfers arenot measured in terms of 8-, 16-, 32-bits or bytes,words or halfwords. The transfer counter transferscycles over a 32-bit bus, with the PDC definingwhether the transfer is byte, word or halfword. If theperipheral is programmed to transfer eight bit data, thePDC can transfer 64 kbytes of data per block transfer.If programmed for 16-bit transfers, it moves 128kbytes of data per block transfer. If programmed for32-bit data, it transfers, four times as much or 256kbytes per block transfer. This gives the programmerconsiderable leeway over the DMA transfer character-istics.

To simplify programming, the PDC programming struc-tures are embedded into each supported peripheraldevice. The register and counter locations are in theperipheral control map so the programmer sees a listof registers and pointers: addresses and counts for thecurrent and next counter and a controller register toenable or disable it.

The PDC avoids processor intervention and removesthe processor interrupt-handling overhead, therebysignificantly reducing the number of clock cyclesrequired for a data transfer and freeing up the MCU todo its embedded control job. The DMA schemes in theSAM7X architecture enable it to simultaneously serveas both a gateway AND a controller, even at high datarates. When transferring just 4 Mbps, a conventionalARM7TDMI processor effectively ties up all its pro-cessing resources. In contrast, Atmel SAM7X proces-sor uses only 2% of its processing capacity to transfer4 Mbps. The device easily supports 25 Mbps SPI orTWI transfers, and still has 96% of it resources avail-able to execute embedded control functions.

Figure 4: TX Rate Table


Encryption and the Peripheral Data ControllerAny embedded control system that needs an Ethernetconnection is going to have to be able toencrypt/decrypt data at or near Ethernet speeds. Thismeans that even the relatively fast 20 Mbps AESencryption/decryption throughput achieved by theSAM7X hardware encryption engine may not be suffi-cient in some applications.

The same bandwidth increases achieved by the PDC indata transfers can also be applied to encryp-tion/decryption. Encryption requires that data be fedcontinuously to the peripheral devices at the data ratethey need so they can perform control operations whilesimultaneously servicing the compute- and memory-intensive encryption blocks.

Data may be encrypted and decrypted directly throughthe peripheral data controller (PDC) channels, withoutout the aid of the ARM7 processor. This capabilityincreases encryption throughput by a factor of 300%to 400%. And frees up the ARM7 processor for otherfunctions. For example, AES encryption that runs at 4Mbps in software and 20 Mbps using a hardwareencryption engine, executes at 80 Mbps when aug-mented by the SAM7X PDC. DES and triple DES requiretoo much computation and memory to be done in soft-ware on the ARM7TDMI processor. However, the PDCincreases hardware DES encryption from 11.2 to Mbpsto 20 Mbps and triple DES from 12.8 Mbps to 32.8Mbps.

Support for Real-time ApplicationsWith all the glamour of 10/100 Ethernet MACs andCAN and USB and advanced encryption, it is all tooeasy to lose site of the fact that, even when connectedby vast arrays of networks, embedded systems are stillreal time systems. Processing must be deterministicand instructions and data must arrive in the right placeat a precisely predictable clock cycle. Unfortunately,the vast majority of 32-bit controllers that have thehorsepower to handle a networked are ill-equipped forreal-time applications.

High-speed 25 ns flash memory on SAM7X microcon-trollers allows single-cycle fetches of code directlyfrom memory, eliminating the need for code shadow-ing and guaranteeing deterministic processing. TheSAM7X can achieve 38 MIPS of raw performance with-out using cache running out of the Flash and 50 MIPSwhen running out of the on-chip SRAM.

Real-time systems are inherently interrupt driven. TheSAM7X has a set of individually maskable, vectoredinterrupt sources and an 8-level priority interrupt con-troller, permanently stored in SRAM that resolves inter-rupt priorities.

Read/Modify/Write (RMW) sequences that individuallyset or clear a bit in I/O space are all too common in realtime systems, but not well supported by 32-bit MCUswhich typically require 15 instructions to execute.Every peripheral on the SAM7X has its own “set” con-trol register and a “clear” control register. This allows asix cycle load/move/store sequence to handle all inter-rupt masking and bit set and reset operations, reduc-ing the processing overhead and code required for thisoperation by 60 percent.

Another weakness of 32-bit processors is their lack ofsupervisory functions to anticipate and prevent unex-pected system crashes due to power failures (brown-out) memory and registers with old values, andunforeseen “loops” The SAM7X includes a full set ofsupervisory functions and on-chip RC clocks thewatchdog timer guarantees the system can be resetusing the RC to put the system into a “safe” state in theevent the “mechanical” crystal fails.

ConclusionToday’s embedded control systems are rapidly morph-ing into embedded networks that are themselves fre-quently networked via the Internet. This trend changesthe criteria for selecting microcontroller for manyembedded applications. Microcontrollers must offerextensive connectivity, based on industry standards,such as USB, CAN and Ethernet, is paramount. MCUarchitectures must be capable of moving largeamounts of data, without compromising processor per-formance. The exposure of these systems to publicnetworks mandates that MCUs include advancedencryption algorithms and secure key storage.

Designers should not, however, allow high perform-ance networking requirements to trivalize the fact thatembedded systems are still real-time systems andneed features that support real-time performance,whether or not they are networked. When evaluatingMCUs designers should verify the level on-chip supportfor real-time applications. At a minimum MCUs shouldprovide deterministic processing, single-supply volt-age, an RC clock and supervisory functions, such aspower on reset, brown out detection, and watchdogtimers.

Figure 5: Software V. Hardware and PDC Encryption Table

SAM7X@50MHzWithout

PDCWithPDC

DES 12.8Mb/s 32.8Mb/sTDES 11.2Mb/s 20Mb/sAES 20Mb/s 80Mb/sAES softemulated 4.3Mb/s n/a

By: Dr. John SengComputer Science DepartmentCal Poly State University – San Luis Obispo

Cal Poly State University, San Luis Obispo recentlyintroduced an undergraduate-level robotics course inits computer engineering program. I was responsiblefor designing and teaching this course. In the class, Iwanted the students to assemble their robots from theground up, starting with the controller board. I lookedat a number of controller boards available on the mar-ket, but none met all of the requirements I was lookingfor in a board design: availability as an unassembledkit, sufficient number of inputs and outputs, powerfulsoftware tools, and overall low-cost. As a result, I setout to design a board with these requirements andended up with a design I called the PolyBot board.

For the design of the PolyBot board, I wanted to sup-port a number of features. The board was going to beassembled by students with limited soldering experi-ence, so all the chips for the board had to be availablein a DIP package and seated in sockets on the boarditself. Chip packages are moving to smaller and small-er sizes, but I needed one that was both available in aDIP package and powerful enough for my application.

The board was going to be used in a classroom envi-ronment, so input power protection was important. Theboard needed to support both over-current and reversepolarity power protection. In addition, it would be use-ful to have the ability to use different voltages to powerthe board. For example, the ability to disable andenable a 7805 voltage regulator was desirable. Ifsomeone wanted to power a robot with a voltage high-er than the logic supports, then they could use the reg-ulator; otherwise, they could disable it.

As for sensor inputs, the controller board needed tohave multiple digital inputs along with analog inputs forthe various sensors that are needed on a robot. Interms of outputs, robots need several motor outputs. Idecided that 8 hobby servo output connectors and 4DC motors would satisfy the requirements.

Hardware designThe microcontroller I chose was the AVR ATMega32.This chip provides more than enough capability for ourapplication. It has a RISC core that allows for good per-formance for our application (many of the instructionsexecute in a single cycle). In addition, the 16 MHzclock rate was more than adequate for the robots in ourclass. This chip was the most powerful microcontrollerI could find in a DIP package, and fortunately, the chipwas also available at a low cost. This microcontrollerhad all of the features I needed for my application.

The over-current and reverse-polarity power protectionis achieved by using a PPTC fuse coupled with a1N5401 diode. A PPTC fuse greatly increases inresistance when the fuse current rating is exceeded.This resistance increases to the point that the fuseeffectively becomes an open connection. In the case ofthe PolyBot board, I selected a PPTC fuse with a ratingof 1.85A. This is sufficient to provide over-current pro-tection in the cases of stalled motors and accidentalshorts. For the reverse current protection, a 1N5401diode is connected in a crow-bar configuration. Whenthe power is connected with reverse polarity, the1N5401 diode conducts, and the current causes thefuse to trip.

For the voltage regulator, I added a 3-pin male headerthat uses a 2-pin jumper to enable or disable the volt-age regulator. If 2 of the pins are shorted, then the volt-

age sent to the logic is +5 volts. This voltagecomes from the output of the 7805 voltageregulator. If the other set of 2 pins are short-ed, then the voltage sent to the logic is takendirectly from the battery voltage.

For the hobby servo outputs, I used 0.1”spaced male headers as connectors. Theymatch the female connectors available onhobby servos. Hobby servos require 3 pins foroperation: signal input, +5 volts, and ground.The 8 servo signals come from the ATMega32microcontroller.

For the DC motor outputs, I used 2 SN754410H-bridge chips. These chips are commonlyused to control motors in small robots. Eachchip provides 2 DC motor H-bridges. Each H-bridge allows bi-directional control of a DCmotor with up to 1-amp of current draw. This


PolyBot Board: A Robot Controller BoardUsing the Atmel ATMega32

Figure 1: Sample Robot

THIS ARTICLE DEALS WITH DESIGNING

A ROBOT CONTROLLER BOARD USING

THE ATMEGA32 FROM ATMEL.

boards successfully. I have found that 4 AA NiMH bat-teries provide an excellent power source. The voltageof fully charged batteries is sometimes a little higherthan the 5.5V maximum voltage for the ATMega32, soI recommend using a Schottky barrier diode to drop thevoltage by approximately .3 volts.

ConclusionThe PolyBot board has worked well at Cal Poly. Usingthe ATMega32 microcontroller on the PolyBot boardhas provided ample computing horsepower for ourrobot applications. More information about the PolyBotboard and full schematics can be found here:www.csc.calpoly.edu/~jseng/PolyBot_Board.html


provided sufficient current for our applications, and theoutputs can be bridged to obtain 2-amps of current ifneeded.

As for other features on the board, I included: an LCDconnection port, a jumper for the LCD backlight,jumpers to allow the use of different voltages for the DCmotors and servos, a relay control port, and a software-controlled LED. The backlight jumper was quite usefulbecause disabling the backlight allowed the robots torun longer on a single charge.

SoftwareThe ATMega32 has a number of open source toolsavailable that make this chip a practical choice for auniversity environment. For software development, weuse the WinAVR software suite that provides a C com-piler (based on GCC), a download utility (AVRdude), andan editing environment (Programmer's Notepad). TheGCC compiler and download utility are also available forLinux and Mac OS X. In our lab environment, we usedboth Windows and Linux and found the experience to besimilar on both platforms.

For the PolyBot board, I wrote a set of library routinesthat allowed easy reading of the analog and digitalinputs, servo control, DC motor control, and LCD displaycontrol.

Board designI designed the PolyBot board using the Eagle CAD pro-gram. This is an excellent PCB design program and isfree for limited size applications. Fortunately, thePolyBot board design fit into the freely available version.The board itself measures 3”x4” and required only 2layers of routing.

In addition to the PolyBot board, I designed a compan-ion download board that mates a parallel port downloadcable with an RJ-45 download cable. Preparing for adownload to the microcontroller becomes just a matterof clicking the RJ-45 cable into the PolyBot board.

ExperienceThe board has been well received by the students at CalPoly and has been successful as a controller in smallrobots as well as in other student projects. All of thestudents in the robot class were able to assemble their

Figure 2: PolyBot board.

Figure 3: Download board

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a ballast inductance that is suitable for the voltage andthe frequency of use. An electromagnetic ballast isspecific to an electricity supply and a type of tube. Itmust be suited to the starting technique, adapted to thesize of the tube (which governs the consumption ofelectrical power), and wired in accordance with the lay-out and the number of tubes concerned.

Optimal consumptionOver time, ballast systems have taken advantage ofpower-switching conversion techniques, and incorpo-rate not only the starting function but also a power fac-tor correction stage, which is necessary so that theswitching at high frequency does not disrupt the elec-tricity supply. In fact, tubes can now be controlled usingvariable-frequency half-bridge inverters, based on arectified voltage, irrespective of the voltage and fre-quency of the supply network, and efficiency increasesof approximately 10% are possible.

More recently, the integration of microcontrollers inballast control circuits marked the beginning of pro-grammable ballasts, offering even greater flexibility,and opening the door to new applications such as light-ing network management, automatic luminosity con-trol, inventory control, and even contrast optimizationfor video projection in the case of high-intensity dis-charge lamps (HID). Such lamps, which are also usedin vehicles and for street lighting, will benefit from aluminosity intensity control which can be automaticallyadjusted to a minimal dormancy level, because theyare particularly refractory to hot starting.

By: Jean-Florent Helie, Electronique Magazine

Unlike incandescent lamps, which convert almost 90%of consumed energy into heat, fluorescent lamps (LFLin the case of linear tubes) are significantly more effi-cient at converting electrical energy into luminousenergy. While the former use a resistant filament thatprovides incandescence, the latter make use of anelectric arc that passes through the lamp between twoelectrodes located at either end.

This arc is conducted by a vapor mixture of mercuryand noble gases (neon, krypton or argon) enclosed in atube with a phosphorous coating. The excited gasreacts by means of photoelectric emissions, mainly inthe ultraviolet wavelength. The phosphorus in turnreacts by emitting a visible light.

In order to start the LFL, it is necessary to create anelectrical arc in a gas that is relatively cold and in tubesof varying lengths. A high initial resistance must beovercome and this is achieved using one of the follow-ing three techniques: ionization of the gas by applyinga high electrical potential; application of a high voltageat the electrodes; and the simplest is based on pre-heating with the aid of filaments.

Each lamp is designed for a particular techniquedepending on the required speed of operation. In eachcase, the excitation causes the heating of the gas andfacilitates current conduction, thereby giving the fluo-rescent tubes a negative resistance characteristic. Thisrequires a current-limiting device, the most basic being


Lighting: Ballast Controller Combined withRISC Processor Yields an Efficient Lamp

MICROCONTROLLERS HAVE BEEN USED IN

THE CONTROL OF FLUORESCENT LAMPS

FOR A NUMBER OF YEARS, PROVIDING

LOGISTICS AND ENERGY MANAGEMENT.

ATMEL OFFERS COMMUNICATION AND

LUMINOSITY CONTROL FUNCTIONS FOR

LIGHTING, BY INCORPORATING AN 8/16-

BIT AVR AT THE HEART OF ITS MOST

RECENT CIRCUITS.

Reprinted with permissionfrom Electronique Magazine,Issue 158, May 2005.

Figure 1: From street lighting to video projection, ballasts can now be programmed.


In addition to the control functions, an obvious area ofinterest to end-users is energy consumption. A ballastthat is more efficient, with a good power factor and adegree of intelligence, will allow a lamp to consumeless energy over a longer service life. It is also advanta-geous that faults can be detected by means of intelli-gent control: some lamps are able to see that their con-sumption increases when a ballast is trying to start atube that is missing or faulty.

Logistical benefitsAtmel now offers two microcontroller categories thatare particularly suitable for ballast applications. The first

category was developed to meet the needs of a fluo-rescent lamp manufacturer, who had exclusive use of itup until now. With an 80C51 at its heart, the circuitwith the reference number AT83EB5114 is used forelectronic ballasts that do not include an attenuationfunction.

With a 256-byte serial EEPROM stacked on the chip,this component is able to store utilization parametersfor different tubes and adapt to the detected type. Thisclearly simplifies inventory control for the manufactur-er, since a single ballast model suits numerous tubereferences.

This circuit has four PWM channels for controlling thepower factor and the ballast circuit. Control accuracy isensured by the high resolution of the pulse width mod-ulation modules (16 bits). In addition to an amplifier forconditioning a shunt voltage, reflecting the current inthe tubes, it includes six 10-bit analog-digital conver-sion channels. A triple clocking system is also provid-ed: one oscillator for a 24 MHz quartz or ceramic res-onator, or two oscillators for an external RC network,one of which is optimized for accuracy and the otherfor low consumption. Based on cost, the RC solution ispreferred, but it sacrifices the performance by limitingthe operating frequency to 12 MHz. Performance lev-els off at 2 MIPS with such a frequency, because the80C51 core is not really monocyclic.

The circuit has three reduced activity modes in order tomanage the consumption of energy. An idle mode sus-pends the functioning of the core but keeps its periph-erals active; a deeper dormancy mode retains only theA/D conversion activity. When it is completely isolatedfrom the circuit, the microcontroller saves the contentsof its RAM and all its functions are deactivated. Sincethis microcontroller is intended for low-cost, high-vol-ume applications, it has 4 Kbytes of hidden ROM, buta flash equivalent is also available for developmentpurposes (AT89EB5114). With a power supply between3 V and 3.6 V, these circuits in 0.35 µm technology arecompatible across the industrial temperature rangeand available in a SO20 or SO24 casing.

Variable luminosity controlIn order to enhance performance, provide luminositycontrol functions, and accommodate the protocolsrequired for a communication bus, Atmel hasincreased the processing power by using its mega AVRcore. This virtually monocyclic 8/16-bit RISC architec-ture effectively offers an execution speed of 16 MIPSwithout an external crystal. The circuits in theAT90PWMx range have also been enhanced in termsof PWM channels so that more sophisticated controlscan be generated, particularly for HID lamps which willbenefit from a step-down stage after the PFC moduleand “full-bridge” type control (see figure). The manu-facturer has also been quick to extend the range ofoperating temperatures.

Better pulse modulationIn response to experiments carried out with microcon-troller ballasts, Atmel has improved the PWM for light-ing applications. Known as the PSC (Power StageController) or 12-bit PWM, this module offers two com-plementary outputs with programmable dead time. Itsmain feature is to offer an improved modulation mode,making it possible to obtain a high average resolution,while maintaining an acceptable counter speed.

The anticipated applications actually involve relativelyhigh switching frequencies, extending from 50 to 100kHz. The 16-bit resolution available on standard mod-ules is therefore never used in practice, and a resolu-tion of 12 bits already implies an extremely fast time

Figure 2: Different levels of application: Depending on the type of lamp and the control accuracy required, theenergy conversion stages can utilize 6 to 10 PWM channels. The schematic diagram at (b) based on theAT90PWM3 is particularly suitable for HID lamps.


base. The resolution enhancement mode allows thePSC module to spread a resolution step over 16 cycles,thereby gaining 4 bits compared with the average res-olution. The modulation step is therefore less than 25Hz for a switching frequency of 150 kHz controlled byan on-board PLL providing a time base of 64 MHz. It isalso the integration of this phase locked loop whichallows the core to function at 16 MHz, based on a sim-ple RC oscillator running at 8 MHz, allowing it to devel-op its computing power of 1 MIPS per MHz.

The PSC module also has a control input, coming fromone of the synchronous analog comparators (8 MHz),in order to allow the detection of any excessive inten-sity. Provision is also made to synchronize the analog-digital acquisition (8 or 11 channels on 10 bits in 8 µs).The acquisition module benefits from the association ofone or two switched-capacitor amplifiers. The 10-bitdigital-analog converter provided on the AT90PWM3circuit will make it possible to set a comparison thresh-old. It will also be used for debugging in some cases,to supervise the digital values by means of an analogsignal. In fact, it is not always possible to set a stoppoint with this type of system.

For the purpose of storing advanced control software,the programmer will have access to 8 Kbytes of flash

memory, 512 bytes of EEPROM and the same amountof RAM. Furthermore, the two circuits AT90PWM2 andAT90PWM3 include a two-mode UART for communi-cation functions. In addition to the standard applica-tion, this interface has a two-phase mode for use on aDALI bus. Therefore, it manages Manchester encodingand decoding, 16-bit or 17-bit data frames, and theauto-synchronization function characteristic of thisprotocol. With the help of these hardware aids, fullDALI functionality will require less than 4 Kbytes ofcode.

Implemented in a 0.35 µm technology that is differentto previous circuits, the three AVR-based microcon-trollers will be supplied with a wider voltage rangeextending from 2.7 V to 5.5 V. The supply to the micro-controller is a relatively critical function for correctstarting of the system. Atmel is proposing a referencedesign, developed with Ixys who will provide the rec-ommended power semiconductors. The ballast isdesigned to operate two 18-W linear fluorescent tubeson the basis of a universal 90-265 VAC 50/60 Hz or90-250 VDC input. It ensures correct operation whenthere is only one tube as well as attenuation control viaa DALI or Swiss-type protocol, or a signal of 0-10 V,which is detected automatically.

Atmel AT90PWMx Microcontroller Family Overview

AT90PWM2 – Specially designed for Lamp bal-last and Motor Control applications, theAT90PWM2 AVR microcontroller features 8KBytes Flash memory, 7-channel advancedPWM, 8-channel 8-bit ADC, two or three 12-bitHigh Speed PSC (Power Stage Controllers) with4-bit Resolution Enhancement and DALI protocolsupport.

AT90PWM3 – Specially designed for Lamp bal-last and Motor Control applications, theAT90PWM3 AVR microcontroller features 8Kbytes Flash memory, 10-channel advancedPWM, 11-channel 8-bit ADC, a 10-bit DAC, twoor three 12-bit High Speed PSC (Power StageControllers) with 4-bit Resolution Enhancementand DALI protocol support.

The received RF signal is processed through the RXchain without any need to go outside the device. Thefiltering stages have been integrated on-chip includingthe Image Rejection Mixer, which allows the eliminationof a SAW filter, and the IF filter, requiring no externalcomponent. This has been made possible using a Low-IF architecture in relation with an integrated filter. Theincoming signal is down converted from the RF to IF =226 kHz, keeping the same modulation scheme. Then,the filtering is applied and the signal is demodulatedeither in Frequency (FSK) or in Amplitude (ASK).Thereafter, the data can be retrieved on theSDO_TMDO pin or directly in the buffer, readable onthe SPI port.

On the transmitter side, the data is processed feed-ing through SDI_TDMI the internal buffer or direct-ly the RF in transparent mode. In both cases, thedata straightly modulates the RF signal, directedto the antenna. Again, no externalmodulation/calibration/control is required andwhatever the chosen modulation is, the pro-cessing is applied internally. The softwaredeveloper work is focused on processing theinformation data and not supporting the RFrequirements.

Moreover, the production of applicationmodules populate with such an RF device becomes

easy and cost-effective: less components and no cali-bration means time and money saving.

High Performance LevelSeveral points should be considered in a RF applica-tion. Among them are :• Sensitivity: ability to receive a very low signal, having

gone through a long air path• Output power: ability to transmit a high power,

compliant with regulations, being able to go througha long air path.

• Selectivity: ability to reject other RF signals, close inthe RF spectrum

• Blocking: ability to reject other RF signals, far in theRF spectrum

All these listed points relate to the ability to communi-cate through a long-distance range signal. In a quietworld, the sensitivity and the output power predict thedistance range which could be reached by one’s appli-cation. In a real world, it is important to be able to keepsafe from other applications, which might disturb one’sreceiver chain, on the LNA stage (wide band), on the IFstage ( medium-band ) and on the demodulation stage(narrow-band). The ATA542x was designed to balanceall these specifications.

By: Eric Mercier, Atmel

In the license-free RF ISM world, a new step ahead hasrecently been announced, representing a major step inthe integration of RF transceivers.

The ATA542x family targeting 315/345/433/868/915MHz bands provides a high-level of performance forISM band applications, with a significant lowering incurrent consumption and a cut in the bill-of-materials.

More Simple Outside/More Complex InsideThe new family of RF transceivers is provided in a small7x7 mm QFN package. The connections are limited to:• RF path to/from the antenna• Interface with the µC thanks to an SPI port• Power supply• Ground

From the antenna to the microcontroller, the internalprocessing of the signal requires no external compo-nents, either active or passive, and no calibration, withthe exception of the PA/LNA path matching. Indeed,this level of integration makes the signal path veryshort.

The RF part of the ATA542x application is composed ofthe Power Amplifier output and the Low Noise Amplifierinput. As it is a half-duplex product, one way at a timecan be processed, therefore the integrated Tx/Rxswitch removes the need for external control over thedirection of the signal. The matching to be applied onthe board is given as a standard recommendation.


Integration and Low Current Consumption:A Reality Today for License-free WirelessApplications

FOR YEARS ATMEL HAS BEEN ENGAGED

IN THE WIRELESS MARKET. SUCCESSFUL

STORIES HAVE EMERGED ON THE

AUTOMOTIVE MARKET WITH RKE AND ON

THE INDUSTRIAL MARKET WITH STANDARD

PRODUCTS AS WELL AS WITH ASICS.

THE RF LINK IN MANY INDUSTRIAL

APPLICATIONS CAN SAVE MONEY ON

INSTALLATION BUT ALSO ON THE

MAINTENANCE ITSELF, (APART FROM

THE COST ADVANTAGE OF THE RF MODULE

OR THE BATTERY LIFE). IT ALSO ADDS

THE ADVANTAGE OF REMOVING THE

WIRES.


The sensitivity of the ATA542x device ranks from 105dBm to –110 dBm in FSK mode and from –110 dBm to–115 dBm in ASK mode, both dependant on the fre-quency band and on the data rate. This makes thisproduct at the state-of-art of receivers specifications.

The maximum output power is +10 dBm or 10 mW.This is the most common value in the ISM world, whichcomplies with most of the world standards, without theaddition of any external transistor or PA module.

Despite the very high integration of the receiver chain,the performance is in terms of selectivity and blockingvery good. Since it is substantially not sufficient to pro-vide high sensitivity if this level cannot be reached dueto jamming signals, the integrated IF filter of theATA542x provides 55 dB rejection at 1 MHz from thechannel, 65 dB at 5 MHz and 70 dB at 20 MHz.

Of course, this new architecture which brings high-levelperformance would not be of interest without a strongattention paid to maintain the current consumption to alow level. With 10 mA in Receive mode and 20 mA inTransmit mode for the maximum output power, the lowcurrent consumption target is reached. This makes RFdesigns with the ATA542x, a major step for battery life,that results in more than 20 percent power reductionversus competing multichannel transceivers.

Field PerformancesThe sensitivity and output power specifications allow toreach line-in-sight more than 1 km range in the low fre-quency bands (315/345/433 MHz) and not much farahead for the upper bands (868/915 MHz). Taking intoaccount that most applications are more or less indoor,several walls or floors can be crossed through withoutimpacting on the quality of the reception. The type ofantenna that will be used in the application is also partof the distance range performance. Using wipe dipoleaerial, which means a λ/4 piece of wire, will bring thebest performance for most of the designs. Using print-ed antenna is also possible with no problem. Thesekinds of antenna are very popular as they are manufac-tured at the same time then the PCB, offering no extracost to the application, with the drawbacks of havingless efficiency/more losses than the wipe antenna. Dueto the high-performance of the ATA542x, the loss of theprinted antenna can be handled and most applications

will still keep the satisfaction of long range transmis-sion.

As shown, the selectivity and blocking performancemust also be considered as important when dealingwith quality link analysis. At some MHz from the carri-er, the ATA542x provides a rejection of typical 60 dB.This is by means corresponding to a ratio of about1000 in distance range between the distant transmit-ter and the jammer, both emitting the same power on

their antenna. If the distant transmitter is at 100meters, then the jammer should be very close to 1 mto impact the communication. Considering a strongjammer at 1 W output power, therefore 100 timesstronger than the ATA542x application, it should be atabout 50 m to disturb a communication of 500 mbetween the distant ATA542x. These figures are goodenough to limit any disturbance from strong signalsand ensure a good continuous quality link.

The ATA542x, in addition to the main performancedetailed here above, also features an accurate andagile frequency synthesizer, with less than 1 kHz accu-racy and some hundreds of µs swap time. This makeseasy Listen-Before-Talk and Frequency Agility proto-cols in Europe as well as FHSS in North America. Agilityand frequency stability are the key points to ensurepower saving protocols in an environment where oth-ers’ applications occur.

Last, but not least, the low current consumption drawnbe the ATA542x in both active and PDN mode is theinsurance that the battery life is preserved from use-less consumption. Especially the PDN figure down to10 nA typical value makes the ATA542x almost with noleak when not operating, thereby long battery life is nota dream any more.

Targeted ApplicationsWith the above-described performance, it makes thisRF family a particularly suitable choice and the idealdevice to target optimized long range/long battery lifein a lossy environment.

For Alarm and Security systems as well as for PowerManagement, the long distance range ability, the lowcurrent consumption and dense implementation are

the required solutions for small intrusion sensors, usinghand-shake protocol and allowing a typical 5-year bat-tery life.

For Automatic Meter Reading, the low current con-sumption in both active and power down modes allevi-ates highly current saving protocols, being at their best.Targeting 10-year battery life is then possible using theRx mode for Waking-Up the remote utility and the Txmode for sending metering information.

For the General Purpose Remote Controller since itsimplementation and programming is easy for non-RFexpert, many applications’ fields then become possibleand these systems take the benefits of the short time-to-production and ultimately time-to-market fordesigning an RF remote controller.

0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0

Bit check OK

Preburst

Start-bit

Byte 1 Byte 2 Byte 3

Receiving ModeBit-check Mode

SDO_TMDO

Demod_Out . . .

. . . Atmel ATA542X Transceiver Family Overview

ATA5423 – The ATA5423 is a highly integrated315 MHz ASK/FSK multi-channel half-duplextransceiver with very low power consumptionsupplied in a small 7 x 7 mm QFN48 package.The receive part is built as a fully integrated low-IF receiver. It integrates a fractional-N synthesiz-er with a direct PLL modulation scheme for FSKtransmission and a switching of the PA for ASKtransmission.


ATA5428 – The ATA5423 is a highly integrated433/868 MHz ASK/FSK multi-channel half-duplex transceiver with very low power con-sumption supplied in a small 7 x 7 mm QFN48package. The receive part is built as a fully inte-grated low-IF receiver. It integrates a fractional-Nsynthesizer with a direct PLL modulation schemefor FSK transmission and a switching of the PAfor ASK transmission.


advan-tage mustbe judged againstthe lower cost advantageprovided by RF CMOS. RF CMOS is capable of pro-ducing a smaller die size because of the smallergeometries used in advanced CMOS processing.When compared, bipolar technologies are typically oneor two generations behind CMOS line widths. Theadvantage in total die size offered by RF CMOS is afunction of the ratio of the digital-to-analog areas of thedesign. Designs with a large digital-to-analog ratiotypically benefit most from the lower geometries of RFCMOS. RF CMOS is offered by more fabs and there-fore more readily available to fabless semiconductorcompanies. If the design calls for an integrated microcontroller, and stacking a die or placing multiple chipsinto a single-chip module is not an option for yourdesign, RF CMOS will usually accommodate the microcontroller in a smaller area. Without the NPN modules,RF CMOS processes have fewer masks and signifi-cantly shorter cycle times. However, as smaller geom-etry processes emerge, the number of mask layersused in SiGe BiCMOS and RF CMOS become moreequal, as shown in Figure 1. Having an equal numberof mask levels in the smaller geometry processes helpsto level out process costs.

RF CMOS processes have better linearity across volt-age than SiGe BiCMOS processes. However, RF CMOSprocesses usually do not have the same quality ofnoise performance as the same sized geometry SiGeBiCMOS processes. Noise affects a circuit by introduc-ing small fluctuations into voltage and current. If thevoltage or current being affected is part of the circuitrycontrolling the frequency, devices, such as low-noiseamplifiers, voltage-controlled amplifiers and mixers,may not work as originally intended. Working with asilicon-on-insulator (SOI) process will help to insulatethe noise but can add considerable costs to your

By: David Hess, SiGe BiCMOS/RFCMOS Foundry Marketing Manager,Atmel Corporation

Introduction to the ProcessesSiGe BiCMOS processes utilize advancedCMOS technology, integrated with NPNbipolar transistors and multiple RF passivesfor analog functionality. The direct result ofremoving the NPN bipolar transistor from the SiGeBiCMOS process is the RF CMOS process, which iscomposed of the remaining CMOS and RF passives.This results in a lower cost RF solution that is capableof meeting the requirements for a large percentage ofRF design needs. There are many important factors indetermining which process will best suit your individualapplication. Evaluation of your device’s specification todetermine AC characteristics, DC characteristics, lin-earity, matching, temperature dependence, memoryrequirements and noise requirements should be madeand documented prior to evaluating different process-es. Ft and Fmax are measures of a transistor’s per-formance that indicate how high of an operating fre-quency you will be able to implement into your design.A standard rule of thumb is that the Ft value of theprocess should be 10 times the operating frequency ofyour device. Fmax is the frequency at which the tran-sistor will still demonstrate a unity power gain. Therelated Ft value is the frequency at which the part willdemonstrate a unity current gain. Both variables areimportant in evaluating potential RF performance. SiGeBiCMOS and RF CMOS processes offer many distinctadvantages, but your design must be evaluated inwhole to determine the process that will offer the bestfit and lowest cost.

SiGe BiCMOSHigh-power, low-current RF applications that havelarge analog and small digital areas (70% analog and30% digital) are usually best suited for a SiGe BiCMOSprocess. The high power allows for good transmissionpower, and the low current enables the part to have along battery life. SiGe BiCMOS processes have highcut-off frequencies and good noise performance,enabling them to meet the stringent demands oftoday’s standards set by organizations, such as IEEE.SiGe BiCMOS processes are capable of higher gainvalues than RF CMOS and historically, have had bettermodels than RF CMOS processes. SiGe BiCMOS usu-ally demonstrates better performance, although RFCMOS may be a more viable solution if your limitationsare space and cost.

RF CMOSDespite the fact that SiGe BiCMOS technologies offerimproved RF performance by virtue of the inherentcapabilities, which the bipolar technology provides, this


SiGe BiCMOS or RF CMOS for Your NextWireless Application?

SHOULD A SILICON-GERMANIUM (SIGE)

BICMOS PROCESS OR A RADIO FREQUEN-

CY (RF) CMOS PROCESS BE IMPLEMENTED

FOR THE DEVELOPMENT OF YOUR NEXT

WIRELESS APPLICATION, AND HOW IS THIS

DETERMINED? MANAGERS, DESIGNERS

AND EVEN ENTIRE BUSINESS UNITS OFTEN

START DESIGNING IN A PARTICULAR

PROCESS AND DO NOT STOP TO EVALUATE

DIFFERENT PROCESSES FOR EACH NEW

PRODUCT. HOWEVER, IF YOU LOOK AT

DIFFERENT PROCESSES AND HOW EACH

CAN BENEFIT YOUR DESIGN, YOU MIGHT

BE ABLE TO SAVE TIME AND MONEY,

REDUCE RISKS AND IMPROVE THE

QUALITY OF YOUR DESIGN. RIGHT NOW

MIGHT BE A GOOD TIME TO TRY SOME-

THING NEW. TAKE A HARD LOOK AT THE

TWO PRIMARY PROCESSES USED IN RF

DESIGN AND WHAT FACTORS SHOULD BE

CONSIDERED WHEN TRYING TO CHOOSE

A PROCESS FOR YOUR NEXT PROJECT.

IMPLEMENTING A WELL-SUITED PROCESS

FOR YOUR RF DESIGN WILL RESULT IN

GOOD RF PERFORMANCE AND LOW-NOISE

FIGURES. MOST FOUNDRIES OFFER BOTH

SIGE BICMOS AND RF CMOS PROCESSES.

SIGE BICMOS AND RF CMOS PROCESSES

EACH HAVE INDIVIDUAL STRENGTHS AND

OFFER SOLUTIONS TO DESIGN NEEDS IN

THE RF IC MARKET. AS ALL SYSTEM

ENGINEERS KNOW, THE LOWEST COST

PER SQUARE MILLIMETER THAT ACCOM-

MODATES ALL OF THE PERFORMANCE

REQUIREMENTS IS THE MAIN DRIVING

FORCE BEHIND ALL TECHNOLOGY

SELECTION DECISIONS.


design. Many RF CMOS processes offer options, suchas triple-well and deep-trench isolation, to assist indecreasing noise.

Geometry SizeGeometry size is another important property of a SiGeBiCMOS or RF CMOS process. Decisions should not bemade based on the newest or smallest availableprocess unless that is what your device requires. Often,the newest processes will have smaller geometries, butthe cost savings resulting from a smaller die size doesnot make up for the more expensive mask set and sili-con, especially if your product will be running lower vol-umes. The geometry sizes are often directly related tothe noise figure, operating voltages, Ft and Fmax val-ues. To accomplish equivalent performance betweenSiGe BiCMOS and RF CMOS, the general rule has his-torically been that the geometry size of the RF CMOSmust be one generation ahead of the SiGe BiCMOSprocess. For example, a 0.25-micron RF CMOS wouldproduce the same available frequency range of a 0.35-micron SiGe BiCMOS. Figure 2 shows that as thegeometry size decreases, speed increases. This graphalso shows that certain frequencies can only bereached by using a SiGe BiCMOS process.

Passive ComponentsProcess options shouldalso be evaluated asanother important con-sideration. A processthat offers you manydifferent types of resis-tors, capacitors andinductors allows for thedevelopment of an opti-mized device. The opti-mization implementedinto most circuits isbased on the matchingand linearity of the pas-sive devices. The Q val-ues for inductors shouldbe evaluated to ensure

high quality. The use of integrated components canhelp to reduce the number of external passive compo-nents and help to save real estate on printed circuitboards (PCB). Memory requirements for RAM, ROM,EEPROM and the corresponding densities of the EEP-ROM can also be a determining factor for processes.With new complex packaging techniques, stacking anadditional memory chip is a viable alternative if theprocess best suited for your design does not offermemory. The most important aspect of passivedevices is the quality of the models provided in thedesign kits.

Independent Parameters Temperature dependence, matching and DC charac-teristics are not necessarily SiGe BiCMOS or RF CMOSprocess dependent. Design rule manuals and foundrydatasheets give Q values for inductors, resistivity of theresistors, capacitance density and linearity values forvarious capacitors. Linearity is a measure of the out-put variance in relation to the input, often used in ref-erence to the gain of a circuit. Linearity is composed ofmany different components. Design of a circuit has adirect impact on the linearity. The size of the circuitalso affects linearity because as the circuit size

increases, the amountof capacitance alsoincreases. Temperaturedependence is usuallydescribed as the tem-perature coefficient(TC). The TC is a rela-tionship between aphysical property andtemperature. This valueis usually given for allpassive componentswithin individualprocesses. Processqualification data willoften provide informa-tion as to the processesoverall reaction to tem-

perature. Device characterization of your design overtemperature will demonstrate the temperatures yourproduct will operate at and what effects low or hightemperature will have. However, many AC parameterscan also be affected by temperature. Examples ofthese are transconductance and threshold voltages.The threshold voltage is the minimum gate source volt-age for a transistor to turn on. Transconductance is theratio of the change in the output current to the changein the input voltage that was caused by the change ofthe output current. Transconductance is also known asmutual conductance. Transconductance will vary fromprocess to process, although SiGe BiCMOS tends tohave better transconductance properties than RFCMOS. The quality of matching is often determined bythe quality of the passive parameters. Matchingenables maximum power dispersion between multiplecircuits.

ConclusionChange can be good. With a thorough understandingof RF design and the available processes, your designscan be placed on a well-suited process. Foundries willoften give you recommendations on the process thatwill best fit your design and allow you to evaluate theirdesign kits. Evaluating the models in the design kitswill allow you to see Ft and Fmax curves, models for alldifferent passives and possibly even models of test cir-cuits, such as voltage-controlled oscillators and low-noise amplifiers. Test circuits of your design that arerun on multi-project wafers can help you to determinethe quality of the models for the process and theprocess’ passives you are using. If your designs aremostly analog and have specific performance needsthat cannot be met by the RF CMOS processes, SiGeBiCMOS might be the right path. If your design islargely digital and performance is not the main criteria,RF CMOS might give you a reduced die size and lowercost. Design and process evaluation will help ensurethat your projects will be high quality and low risk,while meeting budgets and schedules. Unfortunately,deciding on a process does not have a clear-cutanswer. The answer is “it depends,” and the best guar-antee for true success, with the lowest cost per squaremillimeter, is to examine and evaluate differentprocesses from different foundries.

About the AuthorDavid Hess joined Atmel in 2000. Mr. Hess has worked in avariety of engineering positions during his career with Atmel.Mr. Hess is currently in Product Marketing for the SiGeBiCMOS/RF CMOS Foundry organization in Colorado Springs.Prior to joining Atmel, Mr. Hess served as an engineer forPhilips Semiconductors working with different technologiesincluding RF BiCMOS. Mr. Hess has also held engineeringpositions with Electrotech and Varian SEG. Mr. Hess receivedhis B.S. degree in Electrical Engineering from the University ofNew Mexico and his M.S.E.E. degree from the University ofColorado.

Average Mask Counts per Generation

Mar

k Co

unt

Geometry Size (µm)

SiGe BiCMOSRF CMOS

60

50

40

30

20

10

00.5 0.35 0.25 0.13 0.09

Average Highest Achievable Frequency perGeometry Size

Freq

uenc

y (G

Hz)

Geometry Size (µm)

SiGe BiCMOSRF CMOS

0.5 0.35 0.25 0.13 0.09

1815129630

Figure 1: Average Highest Achievable Frequency per Geometry Size

Figure 1: Average Mask Counts per Generation

By: Markus Schmid, Atmel

The number of electronic components in vehicles hasincreased rapidly and continuously during recent years.On the one hand many new sensors and actuators andtherefore new electronic control units have been devel-oped to make passengers feel safer. On the other hand,entertainment and navigation systems have made theirway into cars to make travel more comfortable.

To meet the design challenges due to the differentrequirements (capacitance, real-time operation andcost), several new bus systems have been developed orimproved. This article will provide an overview on someof the most important bus systems currently used incars: CAN, LIN, FlexRay™ and MOST. The articlefocuses on each bus system's application area and theprovided protocol.

In a car, there are several operating fields with differentrequirements regarding the corresponding bus system.Each of the bus systems mentioned above is used toserve a certain communication requirement betweenthe automotive electronic components. The designerselects the appropriate bus system depending on therequired safety level, the data transmission rate and thecosts. For example, the CAN bus - even though it iscurrently the most important automotive bus system -is not well-suited for very fast data transmission asneeded for multimedia applications. Also, the CAN bussystem is too sophisticated, and therefore too expen-sive for applications with low data rates, where only fewparts of the system are involved in the transmission, forexample sun roofs or heating systems. For these appli-cations, new bus systems have been designed.

FlexRay, CAN, and LIN are mainly used for control sys-tems, whereas MOST is used for telemetric applica-tions.

MOST - Media Oriented Systems TransportThe MOST bus was developed in 1998 under the lead-ership of BMW and DaimlerChrysler for all kinds of

automotive multimedia applications such as audio,video, navigation and telecommunication systems. InAugust 2004 the new specification 2.3 was released.

The MOST bus features a very high data rate of up to24.8 Mbit/s in synchronous and 14.4 Mbit/s in asyn-chronous transmission mode. It has an additionalasynchronous control channel with a data rate of up to700 kBit/s. These high data rates make the MOST busthe best fit for real-time audio and video transmissionapplications. To ensure a safe data transmission, anoptical medium (Plastic Optic Fiber, POF), which is notsusceptible to EMC, is used as physical layer.

Furthermore, MOST bus systems support plug&play ofup to 64 nodes, which can be arranged in ring, star orchain topology. This enable to connect all parts of aMOST bus system, the so called MOST devices, in avery flexible way.

MOST CommunicationIn a MOST network, one device needs to be determinedto be the master of the network. This device will be theso-called Timing Master, and all other connecteddevices are slaves.

The organization of a data transfer according to theMOST specification is shown in Figure 2.

For control data transport tasks and network manage-ment, the organization of data transfer in blocks offrames is required. 16 frames are combined in oneblock, each frame consists of 512 bits.

Table 2 (see next page) provides an overview on thecontent of these 512 bits.

Synchronous DataThe synchronous area is mainly used for real-time data

transmission likeaudio/video or sen-sor values. Dataaccess is realized byusing Time DivisionMultiplexing (TDM).Physical channelscan be allocated fora certain time whileplaying an audiosource for example.It is possible to varythe band-width byallocating any num-ber of bytes to one

logical channel. To route the synchronous data to theappropriate sink, a routing engine is used.

The number of synchronous data bytes in one frame islimited to 60 bytes.


Automotive Bus SystemsTHIS ARTICLE WILL PROVIDE AN

OVERVIEW ON SOME OF THE MOST

IMPORTANT BUS SYSTEMS CURRENTLY

USED IN CARS: CAN, LIN, FLEXRAY™

AND MOST, AND FOCUSES ON EACH

BUS SYSTEM'S APPLICATION AREA

AND THE PROVIDED PROTOCOL.

Table 1: Bus System Overview

LIN CAN FlexRay MOST Application Low-level Soft real-time Hard real-time Multimedia,

communication systems systems (X-by-wire) telemetrics systems

Control Single-master Multi-master Multi-master Timing-master

Bus Access Polling CSMA/CA TDMA/FTDMA TDM/CSMA

Bandwidth 19.6 kBit/s 500 kBit/s 10 Mbit/s 24.8 mbit/s

Data Bytes per 0 to 8 0 to 8 0 to 254 0 to 60 Frame

Redundant Not supported Not supported Two channels Not supported Channel

Physical Layer Electrical Electrical Optical, electrical Mainly optical (single wire) (twisted pair)

realized by using Carrier Sense Multiple Access(CSMA), which offers fixed and predictable responsetimes. Although a complete control data message is32 bytes long, only two bytes can be transmitted in oneframe. This means that one block (16 frames) is need-ed to transmit one control data message.

The structure of a control data message is shown inTable 4.

FlexRayFlexRay was developed under the leadership of BMWand DaimlerChrysler in 1999 especially for the new X-by-wire systems, such as steer-by-wire systems or

brake-by-wire, whichrequire a very gooderror managementalong with hightransmission datarates. Atmel is also amember of theFlexRay consortium,which released thelatest specification2.0 in June 2004.

FlexRay is based onthe communicationsystem “byteflight”,which was devel-oped by BMW earli-er. To meet therequirements of thenew bus systems,the byteflightmethod has beenimproved in terms ofchronological deter-ministic and fault tol-erance.

FlexRay supportsdata transmission

with a bandwidth of up to 10 Mbit/s and is thus well-suited for real-time operation. There is no need for aspecial physical layer, therefore, electrical and optical

transmission mediums are supported by FlexRay.Furthermore, FlexRay is suited for several networktopologies such as bus, star, cascaded star and hybridnetwork topologies.

FlexRay CommunicationCAN supports CSMA (Carrier Sense Multiple Access),which means that every device starts a transmission assoon as no other device is sending. Since each devicehas different priorities, collisions on the bus will notoccur. On the other hand, this prevents exact predic-tion of which time the sent data will be received (non-deterministic).

In contrast to that, FlexRay supports TDMA (TimeDivision Multiple Access). Each device has a fixed timewindow (time slot), during which the device has exclu-sive access to the bus. These time slots are repeatedin a fixed pattern.

Using TDMA, it is possible to exactly predict the timewhen the data will be received by the bus (determinis-tic bus access). To properly handle that kind of com-munication, however, all nodes need to have the sameglobal time.

Figure 3 shows an example of a typical data transmis-sion using FlexRay with four components. Two out ofthe four (device A and device C) have a redundant sec-ond channel.

The second channel can be used for redundant trans-mission (C1 in figure 3) or for the transmission of twomessages at the same time (A1 and A2 in Figure 3).The devices B and D are only connected to channel 1,so that the corresponding time slot on channel 2 elaps-es without being used.

If a device has exclusive access to the bus, but has nodata to be sent, the designated time elapses withoutbeing used. In this case, the bandwidth is not usedefficiently. If a device, however, has to send more datathan fits into one time slot, the device needs to waituntil it has exclusive access to the bus again to sendthe rest of its data. To avoid this, FlexRay splits thecommunication cycle into a static and dynamic part.The fixed time slots are designated in the static part,whereas the dynamic part has additional time slots, theso-called mini-slots, during which the exclusive busaccess is limited for a short time. Only if a bus accessoccurs within this time, the mini-slots will be enlargedas necessary. This method helps to increase the effi-ciency of the bandwidth.

The message structure is shown in Figure 4 and ashort description is given in Table 5.

LIN - Local Interconnect NetworkIn contrast to FlexRay, which serves more sophisticat-ed application needs than CAN, LIN has been devel-oped for less complex networks, where CAN would be


Asynchronous DataIf asynchronous data needs to be sent in addition to thesynchronous, the boundary descriptor has to be set asdescribed in table 2 to ensure that the beginning of theasynchronous data can be determined exactly.Asynchronous data transmission is mainly used for larg-er-sized blocks and if larger band-width is required.The number of asynchronous data bytes on an asyn-chronous channel is limited to 48 bytes when using the48 byte data link layer. when using an alternative datalink layer, the maximum packet length is 1014 bytes.

The structure of an asynchronous area in a frame isgiven in Table 3.

Control DataThe control data is mainly used for the communicationbetween the separate nodes of the bus. Data access is

Figure 2: MOST Communication

1 block consists of 16 Frames

1 Frame consists of 512 Bits

synchronous orasynchronous data

0 ... 480 bits

controlframe16 bits

Framecontrol7 bits

Parity

1 bits

BoundaryDescriptor

4 bits

Preamble

4 bits

NAME BITS DESCRIPTION

Preamble 4 Synchronizes the MOST core and its internal functions to the bit stream

Boundary 4 If synchronous as well as asynchronous data is transmitted in one descriptor frame, the boundary descriptor marks the number of 4 byte blocks of

data used for synchronous data in the data block. For example, if 40 bytes of synchronous data and 20 bytes of asynchronous data are transmitted, the boundary descriptor will be set to 10 by the timingmaster

Synchronous or 0...480 See chapter “Synchronous Data” and chapter “Asynchronous Data” Asynchronous data

Control frame 16 See chapter “Control Data”

Frame control 7 Frame control and status bits

Parity 1 Error detection

Table 2: MOST Frame Architecture


Arbitration 8 Avoids collisions on the bus

Target 16 When transmitting asynchronous data, the target address has to be transmit-address ted, too.

Length 24 Length in four byte blocks

Source 16 When transmitting asynchronous data, the source address has to be transmit-address ted, too.

Data area 0...384 The actual data

CRC 32 Cyclic redundancy check

Table 3: Message Format in the Asynchronous Area


too expensive. The LIN specification wasdefined by a consortium with the initialmembers BMW, DaimlerChrysler, Audi®,Volvo, Motorola, VW® and Volcano. Atmeljoined this consortium in 2001. After hav-ing gathered additional experience, the LINconsortium released the new LIN 2.0 spec-ification in September 2003.

Typical LIN bus applications include theconnection of intelligent actuators or sen-sors, such as small motors, temperature orrain sensors, sun roof or heating control.For these applications, high transmissiondata rates or complex fault managementare not necessary.

This is why LIN supports only data trans-mission of up to 19.6 kBit/s. For this datarate, a cost-effective 12 V single wire issufficient as transmission medium.

LIN is based on an SCI (UART) 8-bit inter-face and supports the Single-Master/Multiple Slave concept. UART inter-faces are available in almost every micro-

controller or ASIC,

and can be implemented in almost any software orfirmware. due to this, there is no need for the use ofother expensive external components. A typical LINcluster with one master node and three slave nodes isillustrated in Figure 5.

It is obvious that the master node performs both a mas-ter task as well as a slave task.

Due to the simple concept, no node within the LIN net-work, except the master, will be influenced by adding orremoving another slave. In this case, the only neces-sary changes concern the master node.

A special feature of LIN is the synchronization mecha-nism which adjusts the clock rate of the slave nodes tothe master without an external crystal or resonator.

Thanks to the simplicity of the UART communication,the single-wire transmission and the simplicity of theclock rate adjustment, a LIN bus system is very cost-effective.

LIN CommunicationThe structure of a LIN Bus Message Frame is illustrat-ed in Figure 6.

Every LIN Bus Message Frame starts with the headersent by the master. This header consists of a Breakbyte field, the Synch byte field and the protected iden-tifier. Before the slaves send the requested response,there is a short stop, the so-called response space. theinterframe space at the end of each frame pulls the LINbus to high level until the break byte of the next framewill force the bus line to low level again.


Arbitration 24 Avoids collisions on the bus

Target 16 When interchanging control data between separate nodes, it is important to address specify the target node.

Source 16 When interchanging control data between separate nodes, it is necessary to address identify the source node.

Message 8 There are two different message types. Normal messages include single cast, type group cast and broadcast, system messages include resource allocate,

resource de-allocate and remote getsource.

Data area 0...136 The actual data

CRC 16 Cyclic redundancy check

Transmission 16 Indicates the current status of a transmissionstatus

Reserved 16 Reserved for further protocol use

Table 4: Message Format in the Control Frame

Figure 3: Example of a Typical Data Transmission with Four Bus Devices Using FlexRay

Figure 4: Message Architecture in FlexRay

Header segment Payload segment (0 ... 254 bytes)

Cyclecount

6 bits

Header segment

FlexRay Frame (5 + (0 ... 254) + 3 bytes)

Figure 5: Typical LIN Bus Architecture

Figure 6: LIN Bus Message Frame

Frame slotFrame

Header Response

Synch

Break DATA 1 DATA 2 DATA N Checksum Interframespace

BreakResponse space

Protectedidentifier

Each slave is in alert state as soon as it detects theBreak byte field. The following Synch byte field syn-chronizes the slaves with the master for the followingtransmission. The Synch sequence is always a bytefield with the data value Ox55, so all slave noes withinthe network can easily synchronize to the clock of themaster by detecting the edges of this signal.

Apart from the Break byte field, which is indicated by alow level on the LIN bus for at least 13-bit times fol-lowed by a high level for at least one bit time, all otherbyte fields n a LIN message are constructed as shownin Figure 7.

At the beginning, there is a low level start bit which isknown by almost any UART-based communication,followed by eight data bits with the LSB first. The bytefield is completed with a stop bit.

The protected identifier consists of six identifier bitsand two parity bits, so there are 64 different identifierswithin one LIN network.

The structure of the protected identifier byte field isshown in Figure 8. According to the protected identi-fier and after the response space, a slave begins tosend the requested response, or it expects more data.

this response may contain up toeight data byte fields plus onechecksum byte field.

With the release of the LIN2.0specification, a new checksumcalculation has been introduced.To enable compatibility to the stillused LIN1.3 specification, theprevious type of checksum cal-culation is also supported byLIN2.0. The new checksum iscalled enhanced checksum andis calculated by the inverted eightbit sum along with the carry bitover all data bytes plus the pro-tected identifier. The LIN1.3checksum is called classicchecksum and is calculated asdescribed above, but without theprotected identifier.



A = Reserved bit 1 This bit is reserved for future protocol use and may not be used by the application.

B = Payload preamble 1 This bit is used to indicate whether or not an optional vector is contained within the payload segment. This vec-indicator tor is a network management vector if the frame is transmitted in the static segment or a message ID if the frame

transmitted in the dynamic segment.

C = Null frame indicator 1 If this bit is set, the message included contains no useable date in the payload segment.

D = Sync frame indicator 1 If this bit is set, the frame is used to synchronize all receiving nodes.

E = Startup frame 1 This bit is used to indicate whether or not a frame is a start-up frame.indicator

Frame ID 11 This ID defines a certain slot in which the frame should be transmitted.

Payload length 7 These bits determine the number of data bytes transmitted in the payload frame by setting the payload length bitsto the number of the data bytes divided by two.

Header CRC 11 The Sync frame indicator, the start-up frame indicator, the frame ID and the payload length contribute to the 6 Header CRC.

Cycle count These bits contain the number of the current communication cycles.

Payload segment 2032 In that segment the data will be transmitted. It can contain up to 254 bytes (0...127 two-byte words).

CRC 24 This cyclic redundancy check uses the complete header segment as well as the complete payload segment.

Table 5: Description of Message Architecture in FlexRay

Figure 7: Structure of a Byte Field in a LIN Message Frame

Start bit

Bit 0LSB

Bit 7MSB

Stopbit

Byte field

Figure 8: Structure of the Protected Identifier

Start bit

StopbitIDO ID1 ID2 ID3 ID4 PO P1

By: Dr. Martin Alles, Atmel

Digital Audio Broadcast (DAB)Digital audio broadcast is the preferredtechnology to replace common FMradio broadcast in the future; currently,over 300 million people around theworld can receive nearly 600 DABservices. DAB offers various advan-tages compared with today’s FM sys-tems. the digital transmission of audiodata allows the DAB system to delivernear DC-quality stereo sound even tomobile receivers with a reliability androbustness which is unthinkable withtoday's FM broadcast system. Anotherimportant advantage of the DAB sys-tem is that it was designed to carry data transmissionsand program associated data (PAD). The usual DABtransmission system is especially optimized for auto-motive applications, i.e., a moving receiver with speedsof up to 200 km/h, and using a simple rod antenna.

Today’s FM reception is often distorted or interruptedby multi-path interference, especially when using mov-ing receivers. The main cause of this behavior is reflec-tions from hills and buildings, which arrive out of phasewith the main signal and lead to distortions of the fre-quency modulated carrier; in contrast, DAB uses longsymbol times and special guard intervals. However,this protection against multi-path propagation leads toa reduced transmission rate. To compensate for thisbehavior the DAB standard uses several carriers at thesame time, a method called the multi-carrier orthogo-nal frequency division multiplex (OFDM) transmissionstandard. the remaining effects from reflections due tomulti-path propagation are used in the DAB transmis-sion technique to reinforce the main signal, as shownin Figure 1.

The DAB transmission system is specified with four dif-ferent modes (see www.worlddab.org for more infor-mation on the different modes), with each of thesemodes optimized for different applications and fre-

quencies. the most important modes are mode I forterrestrial single frequency network (SFN), used foroverall DAB transmission, and mode II for medium-scale networks with limited range. All modes are sup-ported by Atmel's DAB chipset.

Atmel’s DAB solutionAtmel offers a complete DAB chipset containing threehighly integrated ICs for DAB reception. The chipsetincludes two ICs which cover the analog functions of aDAB tuner (U2730B, U2731B) and a baseband IC. Theblock diagram of a complete DAB receiver is depictedin Figure 2 (see next page) and the tuner portion of thereceiver is discussed in detail below. Obtaining a totalDAB solution from one supplier optimizes performanceand low bill of materials (BOM), since all ICs matcheach other in an ideal way.

The baseband IC (ATR2740) contains a channeldecoder, a source decoder, and a data decoder. Thebaseband is responsible for fast Fourier transformation(FFT, Viterbi decoding, data processing and sourcedecoding.

The tuner application using the two ICs is optimizedand developed using automotive requirements andquality standards. The Atmel DAB solution includesstandard interfaces for car audio (CAN, RDI), portable

(keypad, LCD), home (SPI, RS232), and PCapplications.

Atmel DAB Tuner ICsThe Atmel DAB tuner containstwo ICs which convert the DABsignals to a fixed IF frequency:the one-chip DAB-receiver ICU2731B and the L-band

down-converter IC, U273OB.


Atmel’s Complete Chipset for DABReception in Automotive Environments

THIS ARTICLE PROVIDES AN OVERVIEW

OF ATMEL'S ADVANCED DAB CHIPSET,

WHICH ALLOWS THE REALIZATION OF A

COMPLETE DAB RECEIVER (EMPHASIS IS

PUT ONLY ON THE TUNER PORTION OF THE

DAB RECEIVER).

Figure 1: Multi-path Propagation for DAB Transmission Systems

can also be used to control an external LNA or attenu-ator.

The functionality of the U2730B is completed with alow-power mode, which disables the AGC loop and theinternal VGA and mixer. The oscillator and the PLL loopremain active even in low-power mode to offer very fastswitching from VHF BIII (175 MHz - 240 MHz) receptionto L-band reception.

A DAB Tuner Using Atmel ICsThe simplified block diagram of the DAB tuner for VHFBIII and L-band reception using both ICs is illustrated inFigure 3; Figure 4 shows a photograph of the actualtuner PCB.

The DAB tuner uses external LNAs for VHF BIII and L-band reception. Both LNAs are included in the AGCloops that are controlled from the U2730B or theU2731B. One of the switches included in the U2731Bis used to toggle between VHF BIII reception and L-

band reception, it selects the external LNA and switch-es the U2730B down-converter IC to low-power mode.

The DACs are used to control the automatic tuneralignment (ATA); this special technique is used in theAtmel tuner ICs to realize an automatic channel selec-tion with out further alignment. The main advantage ofthe ATA is the good channel selectivity which leads toexcellent performance of the tuner. The ATA uses var-actors to adjust the center frequency of a tunable bandfilter to the desired frequency in the reception band.Since the 3-dB bandwidth of this filter is about 6 dB, itis possible to have good selectivity even before enter-ing the SAW filter. More details can be found in the

application note “DAB Tuner with U2730B andu2731B”, on Atmel’s website, www.atmel.com.


The U2731B contains all necessary functionality inorder to convert DAB signals in the frequency range175 MHz - 240 MHz to a fixed IF frequency. The signalpath for the IC includes an input amplifier with variablegain, and a down-converter to a fixed IF of 38.912 MHzwith an integrated SAW driver.

After passing the SAW filter, the signal is again ampli-fied in a VGA and, optionally, down-converted. TheU2731B allows an IF frequency of 38.912 MHz, 38.912MHz - ref. frequency or 38.912 MHz - 2x ref. frequen-cy, depending on the customer’s demands according tothe baseband chip used. An integrated AGC loop con-trols the RF power at the SAW filter by adjusting the gainof the internal VGA and an external VGA or variableattenuator. Another AGC loop adjusts the gain of theVGA at the IF output port of the U2731B in order todeliver optimum IF output power.

The timing of both AGC loops can be adjusted inde-pendently, leading to good channel selection and excel-lent selectivity, i.e., protection against adjacent channelpower and other distortion sources. The incoming RFsignal is fed via one of the two RF inputs into theU2731B.

The IC includes a VCO and a fractional PLL circuit forthe generation of the necessary LO signal, which islocked to the integrated quartz oscillator or an externalreference frequency. The reference frequency signal isavailable at an output pin in order to be connected tothe U2730B, if present.

The functionality of the IC is complete with three switch-es and three DACs, which are used for the automatictuner alignment.

All functionality of the U2731B is controlled with a two-wire bus from the baseband.

To add L-band (1.452 to 1.492 GHz) DAB reception tothe tuner, it is necessary to use the U2730B. This ICincludes a mixer for down conversion of the incomingsignal from L-band to a frequency range which can beprocessed by the U2731B. The IC contains a PLL con-trolled oscillator for the generation of the LO signal anda VGA, which is included in an AGC loop. This AGC loop

Figure 2: Atmel DAB Receiver for VHF Bill and L-band Reception (Simplified)

Figure 3: DAB Tuner Using U2730B and U2731B (Simplified)

VHF Bill175MHz - 240MHz

L-band1452MHz - 1492MHz

L-banddown-

converter

ref. fequency

two-wire bus

baseboard

VHF Bill175 - 240MHz

L-Band1452 - 1492MHz

SAW fixed IF38.912MHz

IFout, e.g.2.048MHz

Figure 4: Photograph of the Atmel DAB Tuner


The signal flow through the tuner for VHF BIII receptionis as follows: The antenna signal is first band-pass fil-tered with a tunable filter which is adjusted using theVCO voltage and one of the DACs. The external gaincontrolled LNA amplifies the signal, which is then againband-pass filtered with the next tunable filter using theother two DACs and the VCO voltage. The signal entersthe U2731B using RF port 1. It is amplified using theinternal VGA. The following mixer converts the incom-ing signal to a fixed IF of 38.912 MHz. This is done byadjusting the VCO and the PLL to a desired LO fre-quency. The DAB signal enters the SAW filter whichremoves all signal parts outside the adjusted DABchannel. Finally, the signal again enters the U2731Bfor an additional VGA stage and an optional mixerstage.

The signal flow for L-band reception includes an exter-nal LNA with adjustable gain and a fixed band-pass fil-ter. This signal is fed to the U2730B, where it is againamplified with a VGA and down-converted to a fre-quency range of 190 MHz - 230 MHz. This signal isband-pass filtered with a tunable filter using two DACsand the VCO voltage of the U2731B. The signal is fedto the RF port 2 of the U2731B and follows the abovedescribed signal flow for VHF BIII.

Design HintsSince the DAB signal is an OFDM signal with a band-width of about 1.5 MHz, it is important that the ampli-fiers and mixers used inside and outside the ICs haveexcellent linearity. The tunable filters and the SAW fil-ter used should have low frequency response in the 1.5MHz bandwidth of the DAB signal in order to limit fre-quency distortion.

The described tuner has a noise figure of about 3.5 dBfor VHF BIII and less than 5 dB for L-band reception,and a dynamic range of about 100 dB for both fre-

quency bands. The sensitivity of the DAB receiverusing the described tuner is better than -95 dBm forVHF BIII and L-band. Without changing any parts, alarge signal performance of +10 dBm for both receivebands can be achieved. the use of an EEPROM is alsorecommended, to store the frequency dependent val-ues for the DACs used in the ATA principle. An EEP-ROM using, e.g., a simple two-wire bus can be easilyintegrated in the DAB tuner.

The modular conception of the DAB tuner with one ICfor VHF BIII reception or two ICs for VHF BIII and L-band

reception allows optimum BOM for both tuner types.

SummaryA lot of different DAB broadcasting services are alreadyavailable around the world, and every DAB receiverneeds an RF tuner and a baseband to decode the DABsignal. The Atmel chipset allows an easy realization ofa DAB receiver with leading performance. The tuner isthe most important key for high quality reception ofDAB signals under difficult conditions, such as occurswith moving receivers.

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Rolling Shutter DescriptionWith a rolling shutter sensor:• Integration time occurs just before the readout ofeach line• The readout resets the pixel content

Therefore the integration time for each line is not doneat the same time.

Depending on the required speed, the chosen integra-tion time might be longer or shorter than the framereadout time.

By: Jacques Leconte, Camera & ApplicationDevelopment Manager, Atmel

Do you think shutter is a brand new question whichappeared with digital photography? Well… just con-sider this old well-known picture made with a roller-blind shutter by Jacques Henry Lartigue (a French pho-tographer in the early twentieth century).

What happened? The camera was moving horizontallyduring the image “grab” to follow the car. Due to theirregular camera movement, the static subjects seemto lean over while the wheel in motion still reflects ageometric distortion (the camera should have beenmoving slower). Comparatively drivers are well grabbedwith no distortion at all.

When grabbing images a shutter is required in partic-ular with objects in the scene moving too fast com-pared to the integration time. The effect of the blurobtained is well known when the speed is too slow dur-ing the shooting of pictures with moving objects.

The camera speed or, for industrial camera users, theintegration time must be chosen so that the image ofthe object may not move more than one pixel (forexample) during the exposure time.

The blur is easy to explain, but what about distortioneffect? This article describes the advantages anddrawbacks of two existing solutions in the progressingscan sensor area: the rolling shutter and the globalshutter.

Image ReadoutIn progressive sensor areas, each line is read one afterthe other.


Areascan Cameras: How to ChooseBetween Global and Rolling Shutter


Global Shutter DescriptionWith a global shutter, all lines have their integration timesimultaneously.

• A global reset is done just before starting the readout• At the end of integration the pixel content is stored in

memory• Then the readout may start

Characteristics of Each SolutionRolling Shutter CharacteristicsThe rolling shutter pixel structure is the easiest solutionto implement. Only three transistors are needed at pixellevel. This allows a good signal-to-noise ratio. Microlenses used to optimize the fill factor (% of the pixelarray sensitive to light) are much easier and more toler-ant when using wide aperture lens.

The main drawback of the rolling shutter is the imagedistortion when an image of a moving object is grabbedand if the integration time is too short in comparisonwith the readout time.

Next an example of image distortion of a moving objectanalyzed with a rolling shutter fixed camera.

As shown below, the helmet at the above part of theimage will be integrated first and then the bottom partat the last time. Therefore between these two exposuretimes the object has moved.

This will cause a distortion on the grabbed image.

We can notice that in order to reach this distortion thispicture is shot at full field with a square sensor. Thespeed of this object is approximately 1 m in 20 ms(resulting from a maximum frame rate of 50 image persecond), or 180 km/h /112 miles/h.

An other example on a “sun” pattern grabbed with theAtmos camera with a speed rotation of 85T/mn and1ms integration time/20ms readout time:After the pattern drawing on the left, the first imagewith no rolling shutter effect shows that the lines arestraight. On the second image, with the rolling shuttereffect and the same integration time we can notice thatthe lines are bent.

Global Shutter CharacteristicsTo perform the global shutter function, a memory“area” must be used beside each pixel. Here below anexample with an additional single transistor.

This memory zone must be non-sensitive, whichmeans there is no light leak.

In fact, on the available components nowadays, thismemory zone is always sensitive to light and sometime“very” sensitive. We may find global shutter with theworst ratio of 1/15, while standard ratio ranks from1/200 to1/500 and last best ratio announced today is1/5000.

For “family pictures” this may be acceptable. Howeverthis is not sufficient in most high demanding industrialapplications. Therefore an electrical shutter seems tobe a very good solution. In the case of a global shutterthe user does not have to take care of light conditions

The effect of a bad shutter efficiency level is shown inthe following pictures. A bright white point is movingfrom left to right during readout. On the right of thewhite point an ghost image may be visible. Contrastand size of the ghost image will depend of the speedand of the shutter efficiency itself.

When working with a 12-bit resolution, the global shut-ter at a ratio better than 1/4000 is necessary as toavoid any wrong information that might be generated.During the image readout the light of path continues tomove illuminating the memory zone of the sensor thuscreating a brighter light intensity.

This ratio should be divided as follows:• By the over-saturation factor you may have on the

image (x 100 even x 1000) when metallic reflectionsoccur

• And also by the ratio between the integration time to the longest memory time as an example witha 10 ratio

Meaning a 1/(4 106) ratio, which is not feasible today.

The memory zone is built using room at pixel level (byadding one to three transistors) which results in

Before buying or building a vision system the imagequality required must be defined. If no ghost image andno distortion is allowed the light will have to be pulsed.

Therefore the shutter type is not a key feature. Theuser needs to be able to synchronize the light pulse.Therefore the camera must offer either a light outputsignal or an input trigger.

Atmel cameras provide these two possibilities. Both theAtmos 1M30/1M60 and Atmos 2M30/2M60 offer highresolution, high speed with a Camera Link® interfaceable to work at 8-10 or 12-bit.


decreasing the pixel aperture ratio and thereforerequiring micro lenses of higher efficiency. This oftenmeans that micro lenses are less tolerant to telecen-tricity errors of the image side of lens. These addition-al transistors may also induce noise. In fact it is a com-promise between shutter efficiency (increase of num-ber of transistors) and pixel aperture (decrease of thenumber of transistors)

A Solution?The unique solution is to pulse the light. But if there isa need for pulsing the light why not choosing the rollingshutter with its better signal-to-noise ratio and its bet-ter pixel aperture without micro lenses?

ConclusionThere are already many applications where a type ofrolling shutter is used. Often this parameter is not tak-ing into consideration by end users:

Example 1:Roller blind cameras (24 x 36 film camera, for exam-ple) are still used without any complaint from users.

Example 2:All the old vacuum tube cameras were using a readoutthat reset the pixel.

Example 3:All line scan cameras are also using different integra-tion times for each line. To prevent any distortion in thiscase, the object speed to the camera speed should beadjusted.

Based on a rolling shutter sensor these cameras allowexcellent dynamic range. The Atmos 2.5M can capture48 fps at full resolution, 60 fps at 2M, and 160 fps inVGA format for the 2M60 thanks to the region of inter-est function. With a 44 mm square section design, plusa C-mount adapter, Atmos cameras are among thesmallest in the market.

The Atmos cameras features are particularly suited fortypical machine vision tasks: Inspection (glass, FlatPanel Display, PCB) robot-guidance, metrology, as wellas various applications such as microscopy or surveil-lance.

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By: François Boré, Sandrine Bruel and MarcWingender

1. IntroductionA high-speed ADC that offers good linearity over arange of high frequency inputs is a key component fortomorrow’s broadband RF transmitters using highIntermediate Frequency (IF) architectures.

New architectures for ADC allow now to reach perform-ances which were barely conceivable a few years ago.Broadband IF Sampling ADC architectures are todaycapable of directly digitizing wideband signals aroundsecond or first IF zones while keeping excellent lineari-ty performance, paving the way to Software Radio.

The architectural shift to broadband data conversionleads to increased ADC sampling rate, creating newchallenges in design, package and test methodology.

A 10-bit 2.2 Gsps ADC has been developed based on a75 GHz SiGe HBT process, including special featuresfor better industrial test coverage.

Key issues for design, test and circuit specification,altogether with characterization results are presentedand analyzed.

2. Purpose of high-speed ADCsAn ADC is used to produce a quantization of a continu-ous time varying continuous signal, therefore part of theinformation included in the input signal will be lost bythis sampling and quantization process (aliasing, quan-tization noise), and some parasitic information will beadded due to the non ideality of the ADC (apertureuncertainty, thermal noise, non linearity).

The relevance of an ADC for a given application is itsability to keep the ratio of useful information over para-sitic (or undesired) information as high as possible for agiven power budget.

A good ADC must be able to code a small signal closeto a large signal (interferer). This feature is mandatoryfor any broadband (multi channel) application were anADC is used to code all the channels and the demodu-lation is performed through digital processing. The con-straint on the ADC is thus on inter-modulation products(IMD) which level must be below the smallest signal tocode.

2.1 Relevant parameter for ADC specification Global parameters such as Effective Number Of Bits(ENOB) are not always relevant to select the best pos-sible ADC for a given application. This is especially truefor very high speed ADC (over 1 Gsps), because of thevery large bandwidth of integration, Signal to Noise

Ratio is dominated by thermal noise, and SNR becomesthe dominant factor in ENOB. Therefore ADC displayingsimilar ENOB figures may have very different linearityfigures (Spurious Free Dynamic Range and/or TotalHarmonic Distortion). For instance an ADC featuring8-bit ENOB can display only 50 dB SFDR while anotherwould display 60 dB SFDR.

Furthermore, frequency independent and deterministicnon ideal characteristics of the ADC can be compen-sated by digital signal processing (e.g. look-up table).

For operation at Nyquist (Fin~Fs/2) and above, theclock phase noise (also called jitter) has direct impacton SNR. Jitter can be split in 2 components: external jit-ter (due to the sources used, or potential board routingissues), and internal jitter (generated in the ADC bythermal noise on clock path, coupling with other sig-nals, or poor power supply rejection). Therefore internaljitter is also a very important parameter of the ADC.

Parameters to consider for a high speed ADC are there-fore: THD, SFDR, IMD (multitone), SNR, Noise PowerRatio (for broadband application), ADC added Jitter (for2nd Nyquist application).

2.2 Parameters for comparison of ADCsAn SNR value is relevant only if considering also theADC sampling frequency altogether with the ADC fullscale, combining the three informations we can pro-duce a relevant indicator of ADC performance, the perHz Normalized Noise Floor expressed in dBm/Hz:

NNF =FS[dBm] – SNR[dBFS] – 10*log(Fclock/2)

Reachable limit of NNF for a reasonable power dissipa-tion seems to be about -150dBm/Hz.

Another relevant indicator of ADC performance is thequantization energy, that is the energy needed to deliv-er an “effective” level of quantization:

EQ=P/(Fsampling*2ENOB)

where P is the ADC power dissipation.EQ should of course be kept as low as possible.

Normalized Useful Bandwidth can be defined as:NUB=Finmax/Fclock (where Finmax is maximum inputfrequency leading to a 3dB degradation of SINAD).

These indicators allow for comparisons between ADCdesigned for various domains of operation.

3. Design challengesAs previously discussed a pertinent 10-bit high speedADC should meet the following criteria:


A 10-bit 2.2 Gsps ADC Operating Over First and Second Nyquist Zones

Code PatchCode Patch

THIS PAPER INTRODUCES A 10 BIT 2.2

GSPS (GIGA SAMPLE PER SECOND)

FULLY BIPOLAR ANALOG TO DIGITAL

CONVERTER, DEVELOPED ON A 75 GHZ

CUT OFF FREQUENCY HBT SIGE PROCESS,

DESIGNED FOR OPERATION OVER FIRST

AND SECOND NYQUIST ZONES.

PERFORMANCES OVER 8 EFFECTIVE

BITS HAVE BEEN DEMONSTRATED

UP TO 2 GSPS NYQUIST. THIS ADC,

DISSIPATING ONLY 4.2W, ACHIEVES

A 10-BIT EQUIVALENT LINEARITY FOR

2 GHZ INPUT.


1. Linearity over first and second Nyquist zone:beyond 57dB SFDR.

2. Good NNF: around or below -145dBm/Hz3. Stable spectral response over sampling rate,

temperature and input frequency to allows for singlelook-up table processing.

4. Clock phase noise added by the ADC must be keptas low as possible.

5. Power dissipated and EQ must be as low as possible.

6. Bit Error Rate should be kept at a level compatible with the application (values commonly admitted :instrumentation 10-12, transmission 10-6).

Items 1 and 2 are related to the internal front end Trackand Hold (T/H) which is mandatory for Nyquist andabove Nyquist operations, and T/H clock managementin the ADC, item 3 is related to settling through thequantifier. Item 4 is related to the clock tree designstrategy. Item 5 is related to the overall design strate-gy of the ADC, and item 6 is depending on the decod-ing and logic part of the ADC.

When taking all these factors into consideration twoarchitectures are possible:1. A single core ADC2. A massively interleaved ADC [1]

We have discarded this second option because of clockjitter management issues. Nevertheless our ADC fea-tures all the tuning needed to allow for easy interleav-ing (offset adjust, gain adjust, aperture delay fineadjust).

3.1 Front End Track and Hold AmplifierIn a fast ADC the front end T/H is a major design issue.The performances of the ADC will be dominated by theperformances of the front end T/H, granted that thequantifier settles properly in its time slot. Depending onthe front end T/H, the ADC will be able to operate overfirst and second Nyquist zones, over first Nyquist zoneonly or in base band only.

Most of the thermal noise is also generated in the T/Hand associated preamplifiers, so special care must betaken in the trade-off of power and noise.

The structure retained for the T/H stage was based ona fully differential S.E.F (Switched Emitter Follower),since this structure is well known for its robustness. Adifferential output amplifier is used to filter out thecommon mode bounces at the T/H output before driv-ing the analog quantifier. A gain 2 differential inputamplifier, is used in front of the T/H in order to be ableto display a constant impedance at the ADC input thusallowing analog filtering.

The main difficulty is to keep a good linearity over thesecond Nyquist zone, since in this frequency domainclosed loop structures are not relevant. We will see inthe result section that performances are quite good.

3.2 QuantifierQuantifier structure choice is a key issue in the designof an ADC, specially when we are looking simultane-ously for speed, accuracy and power efficiency.

Pipeline and sub-ranging architectures are discarded,because for this sampling range they are not relevant,especially regarding B.E.R (Bit Error Rate) issue.

A full flash architecture is also not acceptable becauseof loading effect caused at T/H output due to too manycomparators (210+1), and also because of powerspillage that this architecture would imply.

Finally we retained a successively folded and interpo-lated architecture which offers the best trade-offbetween speed, accuracy and power dissipation.

The MSBs are generated by a coarse cycle pointer, andare corrected in accordance with LSB’s transition in thelogic part. Gain adjustment is made by controlling thebias of the reference resistor chain.

3.3 Logic partThe function of the logic part in a fast ADC is three fold:1. Provide a B.E.R. compatible with the specified

application (e.g: 10-12 for instrumentation).2. Realize the fusion between MSBs and LSBs

delivered by the quantifier, and eventually correctionof MSBs.

3. Convert the internal coding into Binary code.

3.3.1 Bit Error RateThe purpose of regeneration latches is to convert ana-log signals coming from the quantifier into full swingsynchronized logical signals for further processing.

When an analog level coming from the quantifier is veryclose to its transition level the regeneration latch willperform one of the following:1. Take the good decision and produce a full swing

logical level.2. Take the wrong decision, and produce a full swing

logical level, depending on the internal coding the impact can be major (Binary coding, glitch energy 2N

quantum, where N is the index of the considered bit),or minor (Gray coding, glitch energy 1 quantum,because only one bit can be in the danger area at atime).

3. Take no decision (i.e. meta-stability), or produce a logic level of reduced swing which jeopardize subsequent logical operation.

Taking no decision causes B.E.R. In this case the latchdoes not have enough time to generate a true logicallevel from analog signal coming from the quantifier,thus jamming the subsequent decoding.

With an increase in the sampling rate, B.E.R is a majorissue which cannot be neglected. To minimize B.E.R. itis necessary to use latches which have very low diver-

gence time constant, and/or to spread the divergenceover several half clock period.

3.3.2 Merging of MSBs and LSBsThe second function of the logic part is to combineinformation coming from the MSB (coarse) and LSB(fine) sections, in order to produce a full length word.This function performs a correction of the coarse (inac-curate) transitions in accordance with the fine (accu-rate) transitions. We have been using this method suc-cessfully for many years beginning with TS8388 [2](8-bit 1 Gsps ADC), released in 1997.

The NRZ function is also performed in this logic block.This function makes sure that underflow (or overflowrespectively) will not produce codes other than the min-imum code (or maximum code respectively).

3.3.3 Binary encodingThe code conversion from Gray code to natural Binarycode is rather straightforward: a cascaded XOR fromMSB to LSB. To avoid limitations due to propagationripple in this decoding, we have spread the decodingover one and a half clock periods. This decoding circuitincludes a multiplexer, in order to be able to deliver alsoGray code at the output of the ADC.

The output of this decoder is feeding a master slavebank of latches driving differential ECL / LVDS compat-ible output buffers.

3.4 Clock treeFor a fast ADC operating in second Nyquist zone, thejitter observed on the switch of the T/H amplifier candramatically degrade the performances in term of SNR.Special care has been taken in the design of:• the clock circuitry in order to minimize the jitter

induced on chip,• the package which was optimized to avoid coupling

between the clock and other “unclean” signals, al-together with thermal management optimization [3].

The first idea is to use a fully differential circuitry inorder to have optimal rejection of power supply ripple,and to induce as little as possible power supply ripples.The second idea is to use internal clock edges as steepas possible in order to minimize the thermal noiseeffect at each stage of the clock path. For the samereason the clock driving the T/H switch must be kept assharp as possible.

There is a direct relationship between internal clockedge sharpness, fastest transient (or maximum signalfrequency) to digitize and acceptable thermal noiselevel in clock circuitry to meet a specified SNR level.

All the structures used in the clock tree have alreadybeen proven in our former 10-bit 2Gsps ADCTS83102G0 [4]. The measured jitter including board,generator and ADC, based on locked histogram method,using very good generators is about 150fsrms.


A test mode provides special clocking for output latch-es, decimating by 32 the converted data, thus deliver-ing a word rate compatible with industrial test.

4. ADC main featuresThis ADC is now introduced as a standard product ref-erenced AT84AS008 [5], it is mechanical and electricalcompatible with TS83102G0, but offers extended per-formances and extended functionality domain whilesaving 10% of power, thus allowing seamless upgradeof system designed with TS83102G0.

Die size: 14.7mm2

Process: SiGe HBT 75GHz cutoff, 3 layers of metalMax Sampling Rate: 2.2 GspsFull Power Input Bandwidth: 3.5 GHzFull Scale: 500 mVpp diff (tunable +/-10%).Power dissipation: 4.2 WPackage: CBGA152, pitch 1.27 mm.

5. Characterization resultsTest characterization has demonstrated very goodoperation over first (Figures 2, 5) and second (Figure 3)Nyquist zones up to 2.2 Gsps, ENOB at Nyquist is over8.0 bits up to 2 Gsps.

Characterizations demonstrated also a good perform-ance stability over a wide temperature range (Figure 4& 5).

6. State of the art surveyUsing NNF and EQ indicators, as defined in section 2.2,we have compared our performances with other com-mercial, or published ADCs.

For ADC operating at medium frequency the use oflarge full scale input allows for a significant enhance-ment of NNF when expressed in dBFS/Hz. Full scaleincrease is not possible at higher frequency for practi-cal reasons (linearity and power dissipation impact).

Figure 1: View of the ADC layout

Figure 2: SFDR, THD, SNR, SINAD vs Fclock at Nyquist , Ain=-1 dBFS

Figure 3: SFDR, THD, SNR, SINAD vs Fin at Fclock=2 Gsps, Ain=-1 dBFS

Figure 4: SFDR, THD, SNR, SINAD vs Tj at 1.7 Gsps, Fin=848 MHz, Ain=-1 dBFS


Figure 5: 32k points FTT spectrum at 2 Gsps, 995 MHz, Ain=-1 dBFS

Reference Resolution & EQ NNF FS NUBSampling rate [pJ] [dBm/ [dBm]

Hz][1] 8 bit 20 Gsps 7.8 -138 -2 0.1

This work 10 bit 2.2 Gsps 8.2 -144 -2 >1

[4] 10 bit 2 Gsps 13.6 -143 -2 1

[6] 8 bit 1.5 Gsps 27.2 -140 -2 0.8

[7] 12 bit 210 Msps 5.1 -137 +7.5 0.9

[8] 12 bit 185 Msps 2.4 -137 +10 1

[9] 14 bit 105 Msps 3.8 -141 +11 0.8

Table 1: Published or commercial ADC survey

This survey from commercial and published resultsindicates that at least one of the three parameters EQ,NNF and NUB degrades with max sampling frequency.

7. ConclusionWe have designed a fast ADC for Nyquist and aboveNyquist operation, exhibiting a unique NormalizedNoise Floor (NNF) while keeping a Quantization Energy(EQ) among the lowest in its frequency range.Furthermore, we have pushed the sampling ratebeyond 2 Gsps while keeping an ENOB of 8.0 bits atNyquist, and offering outstanding performance oversecond Nyquist zone, thus paving the way to high inter-mediate frequency (IF) digital processing.

8. AcknowledgementsThe authors thank their colleagues Benoit Dervaux,Christian Morino, Claudie Allene, and Jean-PhilippeAmblard for their contributions.

References:[1] Ken Poulton, et al “A 20GS/s 8b ADC with 1MBMemory in 0.18mm CMOS” ISSCC Digest of TechnicalPapers, Feb 2003.[2] Datasheet of ATMEL’s TS8388B 8-bit 1Gsps ADC,rev 2144C-BDC-04/03.[3] Benoit Dervaux, “A Ceramic BGA 148 Package forassembly of a 2 Gsps Analog to Digital Converter”,European Microelectronics Packaging andInterconnection Symposium, Cracow, Poland, 16-18June 2002.[4] Datasheet of ATMEL’s TS83102G0B 10-bit 2 GspsADC rev 2101D- BDC-06/04.[5] Summary datasheet of ATMEL’s ATMEL’sAT84AS008 10-bit 2.2Gsps ADC, rev 5404AS-BDC-01/05.[6] Datasheet of Maxim’s MAX108 8-bit 1.5 Gsps ADC.[7] Datasheet of ADI’s AD9430-210 12-bit 210 MspsADC.[8] Datasheet of Linear Technology’s LTC2220-1 12-bit185 Msps ADC.[9] Datasheet of ADI’s AD6654-105 14-bit 105 MspsADC.

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