ATLAS Read Out Driver Aloisio, Capasso, Della Pietra, della Volpe, Izzo

ATLAS Read Out Driver

Aloisio Capasso Della Pietra della Volpe Izzo

ATLAS Read-Out Driver

On detector Electronics execute the trigger algorithm at 40 MHz frequency and send information to the trigger processor every 25 ns

On detector Electronics also elaborate and group the detectorrsquos data Data are grouped according to the same event number and bunch crossing parameters (Bunch Crossing ID and Level1Accept) and are stored in FIFO memories

On Detector On Detector electronicselectronics

In occurrence of the L1A signal data are transferred on optical fiber from the FIFO memories to the OFF Detector electronics here data are elaborated by the Read Out Driver (ROD) and then sent to the next acquisition levels (Read Out Buffer)

Coincidence Matrix amp PAD Logic

S-Link to

ROB(Read Out

Buffer)

TCP Intf

L1TriggerProcessor

LHCL1A

Off Detector Off Detector electronicselectronics

FIFOsFIFOsFIFOs

TriggerTrigger

RPC ndash LVL1 ndash DAQ Cratebull Each RPC DAQ subsystem reads-out data

of two of the 64 trigger sectors of the spectrometer

bull Data arrive at the receiver boards RX-SL on optical fiber and are transmitted to the ROD via the custom backplane RODbus on a High Speed Serial Link (each RX-SL sends 48 bit40MHz)

bull Timing signals arriving at the ROD are distributed to the daughter boards over LVDS connections on the custom backplane RODbus

bull After being elaborated and grouped in a frame data are sent to the Read Out Buffer

The custom backplane RODbus

Plug-in on VME64x backplane

Central connector for ROD

Slot 2 and 4 for RX-SL

Slot 1 and 5 for microTCP Interface

Upper connectors for LVDS data (~22 Gbits)

Lower connectors TTL for controls (busy reset diagnostics)

Temperature sensor and ADC for power supply controls

The RODbus has been successfully tested and is already installed

microTCPI

RPC ROD Functionality

The ROD is ldquointerfacerdquo between the RPC LVL1 Trigger Readout and the DAQThe ROD- receives the TTC synchronization signals and re-distribute them via the RODbus to the RXSL and μTCPI- handles the Busy Signal exchanged with μCTPI- readout data from RXSL via the RODbus- formats the data according DAQ specification and sends them to the ROS via optical fiber (SLINK)

RPC ROD Data Formatbull The ROD does the a local Event building of the data at Crate Daq Levelbull The data are formatted according to the ATLAS raw event formatbull The ROD event building packs the data readout from the RXSL in frame

starting with an header block composed by 9 long word (Source ID BunchID LVL1 ID etc ) and an footer of 3 long word

bull The data read-out from the RXSL are packed according a similar schema in which the fragment coming from different sources are packed in fragment starting with an header and a footer

bull The RXSL Data are 16 bit words packed in 32 bit word This means that some word are needed to re-align the data frames

bull It performs LVL1 ID and Bunch ID alignment checks between the trigger information coming from central trigger processor and the ones coming from the front-end electronics

bull It also does some overall data integrity checks (missing data from one or both RX within a timeout window JUMBO size fragments etc )

The ROD board

The ROD architecture

bull The VME FPGA allows the communication with the VMEbus with the microcontroller and with the receiver of the TTC

bull The ROD FPGA is interfaced with the RODbus and with the RX-SL boards via the SerDes receivers

bull The two FPGAs communicate via a custom serial protocol

bull Data are sent to the Read Out Buffers through the S-Link transmitter

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

Event Building block diagram

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

Trigger TypeStrobeControls

TTC Clock

RX dataWrite EnableRX Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

RX HeaderL1ABCIDDataRX Footer

Control Logic

Configuration Register File

Synchronous Serial Link

RODbus Interface

Serial data inSerial data out

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

MUON ROD FRAMEL1A = xxxx

Event Building clock domains

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

bull TTC managed via I2C protocol by the microcontroller

bull Timing signals (clock L1A synchronization) are received by the ROD FPGA and are distributed on the RODbus to the RXSLs

bull RXSL frames arrive at the ROD FPGA via RODbus through the SerDes and are used to build the ROD frame

bull Event monitoring and system status can be checked via VME

The Event Building algorithm (1)

L1A Fifo empty

Write ROD header

Timeout

Error handling procedure

SerDes Fifos empty

Parse RX frame

continue

ROD HeaderL1A = xxxx

bull The builder engine waits for a L1A signal to process data

bull Then starts writing Header in the output FIFO (SLink VME or both)

bull The engine waits for data arriving from the RX boards stored in SerDes FIFOs

bull RX frames retrieved from SerDes FIFOs are parsed to find header and L1A

bull If data are not available from RX boards within a programmable time window an error handling procedure is started

RX frames correct

append RX frames

no Error handling procedure

write ROD footer

L1A Fifo empty

ROD Footer

continue

bull If the RX frame is correctly formatted and the embedded L1A matches the current one it is appended to the ROD frame

bull An error procedure is started elsewhere

bull The ROD Frame is closed by a specific footer with keywords word count and error flags

Event Building syntax error

BCIDDataDataRX Footer

RX HeaderL1ABCIDDataDataRX Footer

Skipped data

RX HeaderL1ABCIDDataData

Skipped data

bull JUMBO Frame frames greater than the maximum allowed length Maxlength Realignment at next Header Error Flag

bull RX Frame incomplete RX Frame Footer missing Realignment at next Header Error Flag

bull RX Frame corrupted RX Frame Header missing Search for next valid Header

The ROD microcontrolled

bull The ARM7 microcontroller allows us to monitor the power supply on the ROD board on the backplane and to access via I2C to all the TTCrx registers

bull Microcontroller data can be read by RS232 and by VME

ROD Test in Naplesbull Stand-Alone test in Naples

ndash ELECTRICAL TESTSndash FUNCTIONAL TESTSndash FPGArsquos Firmwarendash Microcontrollerndash TTC receiverndash Busy handling (send to MUCTPI)ndash Data transfer ROD1064058ROS via SLINK

bull ROD Crate functional Testndash Data Readout of RXSL via

RODBusbull EVENT BUILDING

ndash Only random data packet in RXSL fifos

ndash Loading of pre-built data packets in RXSL fifos (Walking bit RXSL Empty Packet Simulated data packet)

Test procedure still to be finalized

Status - Hardware

bull 10 RODs already at CERNndash 1 pre-series to be replaced + 9 Final version

bull 32 RODs delivered in Naples in November (spares are coming)

bull Test started upon deliverybull Regular shipment at CERN in the coming

weeksbull Tests amp shipment at CERN will finish within

first half of 2008

Status ndash Software

bull A complete low-level VME API Library and Scripts to operate and configure the ROD are ready and used in test bed since long

bull A First Prototype of the Final FSM for RPC RCD is ready and successfully tested during Muon Combined Cosmic Runs in the week 3-9 Dec

bull ROD DAQ software fully integrated in the ATLAS DAQ system

bull Data Channel For data sampling (monitoring) still to be debugged

ROD in ATLAS runsbull As of friday we managed to run the system

ndash 10 RODs on 6 different crates sending data to the ATLAS ROS The data trasfer from ROS to the Event builder was done through TCPIP

bull Many noise runs taken smoothly ndash We generate LVL1 triggers using an external clocks that is sent to the

whole chain (ROD SLRX TTCetc ) and we acquire the chamber with HV on (noise run)

ndash We took smoothly a noise run of about 200K evts at a trigger rate of 180 Hz

ndash We than tried to raise up the clock frequency up to 180 kHz The TCPIP limited the bandwidth but there were no problem in the event building nor data corruption

bull Several comsmic runs in both stand-alone or combined with other subdetectorsndash About few millions of cosmics stored in 1 week 200 Hz of trigger

ratebull ECR and BCR signals handled in the correct waybull Deeper data analyses are ongoing

Cosmics with RODs

bull Qui inserirograve un paio di plot con I cosmici acquisiti con il ROD e statistiche sugli errori di formato dei dati

ATLAS RPC amp LVL1 Online Monitoring

Canale Della Pietra della Volpe

Online Monitoring

bull Based on GNAM framework and fully integrated in the ATLAS Online MOnitoring group

bull Custom RPC Data Decoding library

bull Custom Mapping scheme between elx channels and physical strips (40 done)

bull Operational since 2004 Combined test beam

Coincidence between eta and phi strips on the same chamber for each plane in the muon specrometer

RPCGnam Online Monitoring

RPC time with respect to LVL1 signal for each chamber

Data fragment consistency in the RPC readout

Difference between BCID of the ROD fragment and all sub-fragments (RX PAD CM SL)

RPC Gnam Online Monitoring

bull Open issuesndash Complete the mapping files for all the sectorsndash Better organization of OKS Segmentsndash Selection of histograms to be sent to the DQMF and

definition of checking algorithmsndash Porting of the offline analysis into the online

frameworkbull Clustersbull Geometrybull Fast tracking

ndash Combined Online Monitoring with MDTs

ATLAS Data Quality and Commissioning with cosmics

Biglietti Canale ConventiDella Pietra della Volpe Toglia

Offline Data Quality with cosmics

Cluster size of RPC Hits for each plane

RUN 20504

Cluster size

Simple Geometry description of the RPC in the muon spectrometer

Z (cm)

Y (cm)

RUN 20504 Napoli group

Offline Dat Quality with cosmics

RPC standalone 3D tracking

RUN 20504

Theta angle

Phi angle

Direction of muons recontructed in Barrel C

Direction of muons recontructed in Barrel A

Biggest shaft seen from different point of view

ATLAS Read-Out Driver

On detector Electronics execute the trigger algorithm at 40 MHz frequency and send information to the trigger processor every 25 ns

On detector Electronics also elaborate and group the detectorrsquos data Data are grouped according to the same event number and bunch crossing parameters (Bunch Crossing ID and Level1Accept) and are stored in FIFO memories

On Detector On Detector electronicselectronics

In occurrence of the L1A signal data are transferred on optical fiber from the FIFO memories to the OFF Detector electronics here data are elaborated by the Read Out Driver (ROD) and then sent to the next acquisition levels (Read Out Buffer)

Coincidence Matrix amp PAD Logic

S-Link to

ROB(Read Out

Buffer)

TCP Intf

L1TriggerProcessor

LHCL1A

Off Detector Off Detector electronicselectronics

FIFOsFIFOsFIFOs

TriggerTrigger

microTCPI

The ROD board

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

microTCPI

The ROD board

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

microTCPI

The ROD board

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

The ROD board

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

The ROD board

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

The ROD board

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

The ROD board

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

VME FPGA

ROD FPGA

S-Link

SerDes32

4 + 4 (LVDS)

Power Supply analog

monitoring

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls in

Control Logic

RODbus Interface

Controls out

To S-Link

tofrom VME FPGA

4k x 32

512 x 36

4k x 32

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

S-Link interface

Event B

uilder Engine

es Intf

L1A BCID

Trig Type

L1A BCID

TTC Clock

x2 DLL

40 MHz

Board Clock

40 MHz SLink Clock

Controls

Control Logic

RODbus Interface

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

The data path

VME FPGA

ROD FPGA

S-Link

SerDes32

Power Supply analog

monitoring

4 + 4 (LVDS)

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

L1A Fifo empty

Write ROD header

Timeout

SerDes Fifos empty

Parse RX frame

continue

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

RX frames correct

append RX frames

write ROD footer

L1A Fifo empty

ROD Footer

continue

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Skipped data

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Status - Hardware

first half of 2008

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Cosmics with RODs

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Online Monitoring

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

RUN 20504

Cluster size

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

Z (cm)

Y (cm)

RUN 20504

Theta angle

Phi angle

RUN 20504

Theta angle

Phi angle

Documents

ATLAS Read Out Driver Aloisio, Capasso, Della Pietra, della Volpe, Izzo