Asynchronous Circuit Verification and Synthesis with Petri Nets

Asynchronous Circuit Verification Asynchronous Circuit Verification and Synthesis with Petri Netsand Synthesis with Petri Nets

J. Cortadella

Universitat Politècnicade Catalunya, Barcelona

Thanks to: Michael Kishinevsky (Intel Corporation) Alex Kondratyev (The University of Aizu) Luciano Lavagno (Politecnico di Torino) Enric Pastor (Universitat Politècnica de Catalunya) Alex Taubin (The University of Aizu) Alex Yakovlev (University of Newcastle upon Tyne)

Motivation

Interfaces are often asynchronous Subsystems with different clocks often

want to talk to each other Self timing provides functional and

temporal modularity … and no clock skew, low power,

low EMI, average performance, ...

Why Petri nets ?

Formal model to specify causality, concurrency and choice between events

Simple enough to easily derive state-level information (logic synthesis)

Powerful enough to implicitly represent a large state space

Outline

Design flow Synthesis

– Specification– State encoding– Logic decomposition

Synthesis of Petri nets Formal verification

Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

DesignDesignflowflow

x

y

z

x+

x-

y+

y-

z+

z-

Signal Transition Graph (STG)

xy

z

x

y

z

x+

x-

y+

y-

z+

z-

x+

x-

y+

y-

z+

z-

xyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-

xyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-

Currentstate

Nextstate

Currentstate

Nextstate

Synchronous

Asynchronous

xyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-


x z x y ( )

y z x

z x y z


x z x y ( )

y z x

z x y z

x

z

y

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping


VME bus

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle

STG for the READ cycle

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

LDS

LDTACK

D

DSr

DTACK

VME BusController

Choice: Read and Write cycles

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK- DTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-

Choice: Read and Write cycles

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-

Circuit synthesis

Goal:– Derive a hazard-free circuit

under a given delay model andmode of operation

Modes of operation

Currentstate

Nextstate

Fundamental mode– Single-input changes– Multiple-input changes

Input / Output mode– Concurrency

circuit / environment

STG for the READ cycle


DTACK-

LDS-LDTACK-

DSr+

LDS

LDTACK

D

DSr

DTACK

VME BusController

Speed independence

Delay model– Unbounded gate / environment delays– Certain wire delays shorter than certain

paths in the circuit Conditions for implementability:

– Consistency– Complete State Coding– Output persistency

Other synthesis approaches

Burst-mode machines– Mealy-like FSMs– Fundamental mode (slow environment)

VLSI programming– Syntax-directed translation from CSP

(“Communicating Sequential Processes”)– No logic synthesis– Circuit size ~ Size of the specification

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping


State Graph (Read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Binary encoding of signals

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-


D-

DSr-DTACK+

D+

LDTACK+

LDS+

Binary encoding of signals

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-


D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110 01110

01100

0011010110

(DSr , DTACK , LDTACK , LDS , D)

QR (LDS+)QR (LDS+)

QR (LDS-)QR (LDS-)

Excitation / Quiescent Regions

ER (LDS+)ER (LDS+)

ER (LDS-)ER (LDS-)

LDS-LDS-

LDS+

LDS-

Next-state function

0 1

LDS-LDS-

LDS+

LDS-

1 0

0 0

1 1

1011010110

Karnaugh map for LDS

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 0 0 0 0/1?

1

111

-

-

-

---

- - - -

-

- ---

- - -

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping


Concurrency reduction

LDS-LDS-

LDS+

LDS-

1011010110

DSr+

DSr+

DSr+

Concurrency reduction


DTACK-

LDS-LDTACK-

DSr+

(See today’s presentation in this workshop for more details)

State encoding conflicts

LDS-

LDTACK-

LDTACK+

LDS+

10110

10110

Signal Insertion

LDS-

LDTACK-

D-

DSr-

LDTACK+

LDS+

CSC-

CSC+

101101

101100

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping


Complex-gate implementation

)(csccsc

csc

csc

LDTACKDSr

LDTACKD

DDTACK

DLDS

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping


Hazards

abc

x 0

abcx1000

1

0

0

1100

b+1

1

00100

a-

0

1

0

0110

c+

0

1

1

Hazardsabcx1000

1100

b+

0100

a-

0110

c+

a

bz

cx

1

0

0

00

10001

1

0

001100

1

1

1

001100

0

1

1

00

0100

0

1

1

10

0110

0

1

1

11

0

1

0

11

0

1

0

10

Decomposition

Global acknowledgement Generating candidates Hazard-free signal insertion

– Event insertion– Signal insertion

Global acknowledgement

abc

z

abd

y

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-

abc

z

abd

y

How about 2-input gates ?

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-

a

bc

z

abd

y


d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-

a

bc

z

abd

y


00

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-

abc

z

a

bd

y


d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-

cz

dy


a

b

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-

Strategy for correct logic decomposition

Each decomposition defines a new internal signal of the circuit

Method: Insert new internal signals such that– After resynthesis,

some large gates are decomposed– The new specification is hazard-free under

unbounded gate delays

y-

z- w-

y+ x+

z+

x-

w+

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

Decomposition example

yz=1yz=0

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

C

C

x

y

x

y

w

z

xyz

y

zw

z

w

z

y

s-

s+

s-

s-

s=1

s=0

1001 1011

1000

1010

0111

0011y+

x-

w+

z+

z-

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

C

C

x

y

x

y

w

z

x

y

z

w

z

w

z

y

sy-

s-

s+

s-

s-

s=1

s=0

1001 1011

1000

1010

0111

0011y+

x-

w+

z+

z-

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

y-y-

z- w-

y+ x+

z+

x-

w+

s-

s+

s-

s+

s-

s+

s-

s+

s-

s+

s-

s+

s-

s+

s-

s+

C

C

x

y

x

y

w

z

xyz

y

zw

z

w

z

y

yz=1yz=0

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

s-

s+

s=1

s=0

1001 1011

0111

0011

x-

w+

z+

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

y-y-

z- w-

y+ x+

z+

x-

w+

s-

s+

s-

s+

s-

s+

s-

s+

s-

s+

s-

s+

s-

s+

s-

s+

z- is delayed by the new transition s- !

yz=1yz=0

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

C

C

x

y

x

y

w

z

x

y

z

w

z

w

z

yyyyyyy

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

Signal insertion for function F

State Graph

F=0 F=1

Insertion by input borders

F-

F+

Event insertion

a b

ER(x)

cx x x x

b

SR(x)

a

Properties to preserve

a

a

b

b

a

a

b

b

a

a

b

b

xx

a

a

b

b

a

a

b

b

ba

a

b

b

xx

xx

a ispersistent

a is disabled by b

= hazards

Interactive design flow

Petri Net

(STG)

Transition

System

Transition

System


Transformations + Synthesis

Theory of regions(Ehrenfeucht 90, Nielsen 92)

a

a a

b b b

c

c a

b

c

Synthesis of Petri Nets

a

a

b

bb

c

c

ca

b c

Excitation closure

a

a

b

bb

c

c

c

b c

a

b

bb

b

Label splitting

a

c c

d

d

d

d

a

b

b

c

d

Formal verification

Implementability properties– Consistency, persistency, state coding …

Behavioral properties (safeness, liveness)– Mutual exclusion, “ack” after “req”, …

Equivalence checking– Circuit Specification– Circuit < Specification

Property verification: consistencyd+

a+

b+

c- a-

b- d-

c+

Specification

a+ a-

Property

Failure if a+ enabled in specification anda- enabled in property (or viceversa)

Correctness: environment circuit

d+

a+

b+

c- a-

b- d-

c+a

b

c

d

Environment

Circuit

Failure: circuit produces anevent unexpected (not enabled)by the environment

Fighting the state explosion

Symbolic methods (BDDs) Partial order reductions Petri net unfoldings Structural theory (invariants)

Fighting with state explosion

p1

p2

p3

p1 p2 p3

p1 p2 p3p1 p2 p3

p1

p2 p2

p3 p3

0 1

01

00

00

1

1

1 1

Representing Markings

p1p2

p3

p4

p5 p0

p2 + p3 + p5 = 1p0 + p1 + p4 + p5 = 1

{ p0, p3 } v0 v1 v2 v3

p2 v0 v1

p3 v0 v1

p5 v0

p0 v2 v3

p1 v2 v3

p4 v2

Place encoding

Summary

Asynchronous design is applicable to– asynchronous interfaces– high-performance computing– low-power design– low-emission design

There is an increased interest of few, but large scale companies: Intel, Philips, Sun, Sharp, ARM, HP, Cogency

Summary (continued)

Asynchronous circuits are more difficult to design than synchronous

Formal models and CAD support are essential

Petri nets have been one of the most successful formalisms for modeling asynchronous circuits

Most steps of the design process covered by this tutorial are supported by the tool Petrify

Documents

Asynchronous Circuit Verification and Synthesis with Petri Nets