Asynchornos Counter

7/28/2019 Asynchornos Counter

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Asynchronous Counter


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Asynchronous Counter

2

This presentation will

Define asynchronous counters.

Define the terms states and modulus.

Provide multiple examples of asynchronouscounters designed with D & J /K flip-flops.

Explain an asynchronous counters ripple effect.

Summarize the asynchronous counter design steps.


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Asynchronous Counters

Only the first flip-flop is clocked by an externalclock. All subsequent flip-flops are clocked bythe output of the preceding flip-flop.

Asynchronous counters are slower thansynchronous counters (discussed later) becauseof the delay in the transmission of the pulsesfrom flip-flop to flip-flop.

Asynchronous counters are also called ripplecounters because of the way the clock pulses, orripples, its way through the flip-flops.

3


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States / Modulus / Flip-Flops

The number of flip-flops determines the count limitor number of states:

States = 2 (#of flip-flops)

The number of states used is called theMODULUS.

For example, a Modulus-12 counter (Mod-12)

would count from 0 (0000) to 11 (1011) and wouldrequire four flip-flops (24 = 16 states; 12 are used)

4


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Asynchronous CounterD-Flip Flop 1 Bit

5CLK

Q0 0 1 0 Repeats


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Asynchronous CounterUpCounter D-Flip Flops 2 Bit

6CLK

Q0

Q1

0Repeats

0

1

0

0

1

1

1

0 1 2 3

Note: Since we want

Q1 to toggle on the

falling edge of Q0, we

must clock the

second flip-flop from

the of the first.0Q


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Asynchronous CounterUpCounter D-Flip Flops 3 Bit

7CLK

Q0

Q1 Repeats0

0

0

1

0

0

0

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

1

1

Q2

0 2 4 61 3 5 7

Note: The CLKs

are connected to

the of the

previous flip-flop.

Q


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The Ripple Effect

As the clock input ripplesfrom the first flip-flop to the last, thepropagation delays from the flip-flops accumulate. This causesthe Q outputs to change at different times, resulting in thecounter briefly producing incorrect counts. For example, as a 3bit ripple counter counts from 7 to 0, it will briefly output the

count 6 and 4.

8

CLK

Q0

Q1

Q2

1

1

1

0

0

0

1 mSec 100 nSec

7

111

4

100

6

110

0

000


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Asynchronous CounterDown Counter D-Flip Flops 3 Bit

9CLK

Q0

Q1 Repeats1

1

1

0

1

1

1

0

1

0

0

1

1

1

0

0

1

0

1

0

0

0

0

0

Q2

7 5 3 16 4 2 0

Note: The CLKs

are connected to

the Q of the

previous flip-flop.


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Asynchronous Counter Summary

Up Counters

Connect the CLK input to the Q output with theopposite polarity

Down Counters

Connect the CLK input to the Q output with thesame polarity

10


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Asynchronous CounterUp Counter J K-Flip Flops 3 Bit

11CLK

Q0

Q1 Repeats0

0

0

1

0

0

0

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

1

1

Q2

0 2 4 61 3 5 7

Note: The active

low CLKs are

connected to the

Q of the previous

flip-flop.


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Asynchronous CounterDown Counter J K-Flip Flops 3 Bit

12

0

1

1

1

0

1

0

0

1

1

1

0

0

1

0

1

0

0

0

0

0

Q2

Note: The active

low CLKs are

connected to the

of the previous

flip-flop.

Q

CLK

Q0

Q1 Repeats1

1

1

7 5 3 16 4 2 0


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Modulus Asynchronous CounterUp Counter D Flip Flops 3 Bit / Mod-6 (0-5)

13

1

0

0

0

1

0

0

0

0

0

0

1

1

0

1

0

1

1

0

0

1

Q2

RESET

Q0

Q1 Repeats0

0

0

0 2 4 01 3 5 1

Note: The upper limit of

the count is 5; therefore,

the reset circuit must

detect a 6 (count +1).


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Asynchronous Counter Design Steps1) Select Counter Type

Up or Down

Modules

2) Select Flip-Flop Type D (74LS74)

J /K (74LS76)

3) Determine Number of Flip-Flops

2 #Flip-Flops Modules

4) Design Count Limit Logic

Input to reset logic circuit is count limit plus one for upcounters (minus one for down counters) 14

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Asynchornos Counter