IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 1, JANUARY 2009 93

Asymmetric Schottky Tunneling Source SOIMOSFET Design for Mixed-Mode Applications

Ritesh Jhaveri, Student Member, IEEE, Venkatagirish Nagavarapu, Student Member, IEEE, andJason C. S. Woo, Fellow, IEEE

Abstract—Schottky barrier MOSFETs have recently attractedattention as a viable alternative to conventional CMOS transistorsfor sub-65-nm technology nodes. An asymmetric Schottky tunnel-ing source SOI MOSFET (STS-FET) is proposed in this paper.The Schottky tunneling source SOI MOSFET has the source/drainregions replaced with silicide as opposed to highly doped siliconin conventional devices. The main feature of this device is theconcept of a gate-controlled Schottky barrier tunneling at thesource. The device was optimized with respect to various param-eters such as Schottky barrier height and gate oxide thickness.The optimized device shows excellent short channel immunity,compared to conventional SOI MOSFETs. The asymmetric natureof the device has been shown to improve the leakage current aswell as the linear characteristics of the device as compared toconventional Schottky FETs. The STS-FET was fabricated, usingconventional processes combined with the present NiSi technologyand large angle implantation, and successfully demonstrated. Thehigh immunity to short channel effects improves the scalability,and the output resistance of the device also makes it an attractivecandidate for mixed-mode applications.

Index Terms—Asymmetric, MOSFET scaling, Schottky,silicide, tunneling.

I. INTRODUCTION

MAJOR CHANGES in conventional CMOS scaling havebeen proposed for sub-65-nm regimes due to many

aggravated problems such as gate leakage and reduced perfor-mance. New materials such as high-k, strained silicon, metalgates, and novel design methodologies are under active investi-gation. Schottky Barrier MOSFETs (SB-FETs) as an alternativeto conventional MOSFETs have also attracted a renewed in-terest for sub-65-nm applications [1]–[7]. SB-FETs have theirsource/drain regions replaced with metal, typically silicides,as opposed to highly doped silicon regions in conventionaldevices. The main advantages of using silicides as source/drainregions are low parasitics, superior scaling properties, ease offabrication, and low thermal budget [2], [8]. An excellent scal-ability of SB-FETs to sub-10-nm gate lengths is feasible due tothe low resistance of the silicide regions and atomically abruptsilicide/silicon junctions [9]. Silicides are realized typically attemperatures below 700 ◦C which makes them compatible forintegration with high-k dielectrics and metal gate stacks used

Manuscript received August 7, 2008. Current version published December 19,2008. This work was supported in part by the National Science Foundationunder Grant ECS-9731293 and in part by DARPA. The review of this paperwas arranged by Editor M. J. Kumar.

The authors are with the Electrical Engineering Department, University ofCalifornia at Los Angeles, Los Angeles, CA 90095 USA (e-mail: riteshj@ee.ucla.edu; woo@ee.ucla.edu).

Digital Object Identifier 10.1109/TED.2008.2008161

in a conventionally sub-65-nm CMOS process flow [10], [11].SB-FETs have also been shown to offer immunity to latch-upby essentially eliminating parasitic bipolar actions [12].

Using Schottky barriers as the source/drain junctions, how-ever, has its downside. The major problem is the reductionin drive current due to the presence of a resistance acrossthe source and the channel Schottky barrier in SB-FETs [8],[13]. The potential drop across the Schottky barrier (turn-onvoltage of the Schottky diode) on the drain side also degradesthe device performance at low drain voltages [8], [13], [14].SB-FETs also suffer from ambipolar conduction which leadsto increased OFF-state leakage and variability [1], [15], [16].Hence, improving carrier injection in SB-FETs is essential tofurther improve their device performance.

To overcome these problems, metal silicides that have smallSchottky barrier heights (SBHs) have been proposed by var-ious research groups. Silicides such as ErSi2 and PtSi havebeen investigated to improve performance [17]. Recently, thefabrication of SB-FETs on ultrathin body SOI substrates havebeen shown to improve device performance due to a moreeffective control over the Schottky barrier for carrier injection[6], [7]. Nanoscaled SB-FETs have also been proposed wherethe driving capability is improved by using short spacer lengthsto increase the effect of fringing fields on the Schottky Barrier[18]. Another approach that has been examined recently is toeffectively modify the barrier height by using doped extensiontechniques at the source/drain junctions such that the currentdrive is not degraded by the junction resistance [3], [19]–[22].Asymmetric Schottky source/drain structures with differentsource/drain materials have also been investigated to mitigatesome of the problems described [15], [23], [24].

In this paper, an alternate asymmetric Schottky tunnel-ing source SOI MOSFET (STS-FET) introduced in [25] and[26] is investigated. The proposed device uses gate-controlledSchottky tunneling as the current injector at the source anda conventional heavily doped semiconductor junction at thedrain. The heavily doped semiconductor drain pocket elimi-nates the ambipolar nature of the SB-FET and improves theperformance of the device at low drain voltages by providingan ohmic junction. In this paper, we investigate the deviceperformance and the device design of the proposed transistorswith respect to several critical parameters. First, the deviceconcept is introduced in Section II along with a discussion ofthe principle of operation. Simulation results and optimizeddesign considerations are presented in Section III. Experimentalresults are presented in Section IV along with discussions.Finally, Section V presents the conclusion by summarizing thekey advantages of the asymmetric STS-FETs.

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Fig. 1. Device structure of the Schottky tunneling source SOI MOSFET.

Fig. 2. Conduction band edge near the source end with changing gate voltagefor an STS nFET with a barrier height ϕbe = 0.45 eV.

II. DEVICE DESIGN

Fig. 1 shows the device structure of the novel asymmetricSchottky tunneling source SOI MOSFET (henceforth referredto as STS-FET). The device has an asymmetric structure withfully silicided source/drain junctions along with a highly dopedpocket at the drain. The gate in the Schottky tunneling sourceis chosen to be fully silicided which can be achieved in thesame step as that of the silicidation of the SOI film. The pocketon the drain side (n+ for nFET and p+ for pFET) forms alow resistance contact between the channel and the drain undersmall drain bias, eliminating the potential drop at the drain sidedue to the presence of a Schottky barrier. Transport across theSchottky barrier is primarily of two types: thermionic emissionover the Schottky barrier and tunneling through the Schottkybarrier. The operating principle of the STS-FET utilizes theconcept of gate-controlled Schottky barrier tunneling betweenthe source silicide and the channel Si [27], [28].

The gate controls the tunneling current through the modula-tion of the Schottky barrier at the source side by changing thetunneling width and the available density of states as shown inFig. 2. The tunneling current is a function of the SBH betweenthe metal and the semiconductor, and the gate dielectric thick-ness and gate voltage. When the gate voltage is low, currentinjection is limited by tunneling resistance. Therefore, in thesubthreshold regime, the carriers of the STS-FET are injectedby tunneling between the Schottky barrier source and the siliconchannel as opposed to thermionic emission. As the gate voltageincreases, the tunneling distance decreases and the number ofstates to tunnel into increases, thereby reducing the tunneling

Fig. 3. ID–VG characteristics at various barrier heights for a given oxidethickness of 20 Å and gate length of 90 nm.

resistance. Therefore, at high gate voltages, the current islimited by a combination of tunneling and channel resistances.

III. SIMULATION AND OPTMIZATION

To understand the tunneling concept and the physicsinvolved, extensive simulations were performed using theSynopsys-TCAD tool DESSIS device simulator. The simulatoruses the well-known physics of the tunneling and thermalemission across a Schottky barrier and matches the total currentfrom the source to the channel current [29]. The tunnelingcurrent is calculated using the integral of tunneling probabilityand the density of states on the silicide/silicon junction. Thetunneling probability is calculated by assuming a triangular bar-rier and using WKB approximation. The simulator uses a non-local tunneling model to calculate tunneling between two pointson the grid around the junction. The simulator models wereverified by comparing the resistivities of various silicide/siliconjunctions with known silicide/silicon barrier heights. The de-vice performance was analyzed for a matrix of critical parame-ters to determine the optimum design considerations.

A. Effect of Barrier Height

One of the most important parameters affecting device per-formance is the barrier height (ϕb) of the metal/silicon junctionat the source side. Fig. 3 shows the ID–VG characteristics of de-vices with various barrier heights. It can be seen that, with highbarrier heights, the subthreshold current is limited by tunnelingonly. The thermal emission current is an exponential function of−ϕb and independent of gate bias. For a large ϕb, the thermalemission current is negligible compared to the tunneling cur-rent. As the barrier height increases, the on-current decreases,due to the high tunneling resistance at the source Schottkyjunction. The subthreshold swing is different from that of adiffusion-limited source injector and independent of the barrierheight. As the barrier height reduces to about 0.25 eV, the tun-neling resistance becomes very small, and the thermal emissioncurrent starts to dominate. The channel current is controlledby the gate voltage modulating the diffusion barrier rather than

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Fig. 4. Simulated subthreshold swing with different gate oxide thicknesses.The fit is linear with the equation as listed inset.

the tunneling barrier at the source, and the subthreshold currentbehaves like that of diffusion-limited MOSFETs.

It can also be seen that, for high barrier heights, when thesubthreshold current is limited by the tunneling resistance,the drain induced barrier lowering (DIBL) is considerablyimproved. This is due to the fact that the drain has littleinfluence on the SBH and width which dictate the currentinjection from the source into the channel. As the barrier heightdecreases, the tunneling resistance decreases, and the currentbecomes diffusion limited. Hence, the DIBL worsens as thedrain can much more effectively influence the diffusion barrier(the device becomes similar to a conventional MOSFET atϕb = 0 eV). The off-current of the STS-FET is determinedprimarily by the SBH and width at the source. To reduce theOFF-state leakage, a high barrier height is desired. However, tomaintain a reasonable drive, the barrier height and tunnelingresistance needs to be reduced when the device is on. Hence, atradeoff is established where the barrier height can be tuned forspecific device applications.

B. Effect of Oxide Thickness

One of the distinct features of tunneling-limited subthresholdcurrent is that the subthreshold swing shows a linear depen-dence to the first order on effective oxide thickness as seenin Fig. 4. This is different from conventional diffusion-limitedsubthreshold swing which is independent of oxide thicknessprovided the ratio of CDEP/COX � 1. The minimum swingobtained at room temperature by extrapolation to zero tOX is60 mV/dec. This suggests that the subthreshold swing of thegate-controlled STS-FET is always higher than that of thediffusion-limited conventional MOSFET at 300 K. However,the tunneling process has weak temperature dependence asopposed to diffusion which is linearly proportional to tempera-ture. Thus, for the typical operating temperature of greater than85 ◦C, the STS-FET with small effective oxide thicknesscan have superior subthreshold characteristics even for highlyscaled channel lengths due to the high immunity to shortchannel effects.

C. Scalability

The scalability of this device was studied, and it was foundthat the STS-FET is highly immune to short channel effects

Fig. 5. Vth rolloff and DIBL at different barrier heights for the STS-nFETas compared to conventional SOI-nFET. Improvement in short channel effectsincrease with increasing barrier height.

Fig. 6. Conduction band edge for different drain voltages. The Schottkyjunction at the source is immune to changes in the drain voltage.

down to a channel length of close to 50 nm compared toa conventional fully depleted SOI nFET. A linear thresholdvoltage rolloff at VD = 0.1 V and DIBL for the STS nFET and acomparable SOI nFET at different channel lengths is shown inFig. 5. A high immunity to short channel effects is explainedas follows. The source injection of carriers is dominated bytunneling through the Schottky barrier. The tunneling current isa strong function of the barrier height and tunneling width at thebarrier. The fixed Schottky barrier at the source is insensitive tothe electric field from the drain, and hence, this device suffersfrom very little DIBL as seen in Fig. 6. As the barrier heightincreases, the immunity to changes in the drain field increases,and the short channel effects are further reduced. This makesthe STS-FET a highly scalable device going into sub-50-nmtechnology nodes.

The high immunity to short channel effects in turn increasesthe ROUT of the device. A plot of ROUT versus ID of the STSand a SOI-nFET at LG = 90 and 50 nm at VD = 0.8 V is shownin Fig. 7. Approximately an order increase in ROUT, comparedto a conventional SOI nFET, is obtained for currents less than500 μA/μm. While the continuous scaling of conventionalCMOS makes it an excellent choice for RF wireless commu-nications, due to increased short channel effects, the outputresistance (ROUT) of sub-100-nm MOSFETs degrades signif-icantly. This severely reduces the intrinsic gain of the device,and thus, it is becoming increasingly difficult to achieve bothhigh gain and high ft simultaneously in conventional devices.SB-FETs have been actively investigated for high-frequency

96 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 1, JANUARY 2009

Fig. 7. Improvement in ROUT of the STS-nFET as compared to a conven-tional SOI-nFET.

operations successfully [30], [31]. The high output resistanceof the STS-FET makes it attractive for RF devices that needa high gain at high frequencies. This makes the STS-FET anexcellent choice for RF and mixed-mode applications [32].

IV. EXPERIMENTAL RESULTS

A. Fabrication

In order to verify the device concepts, STS-nFETs and pFETswere fabricated on SOI substrates of silicon film thicknessesof 90 and 50 nm. As compared to conventional SOI devices, alow bulk doping does not degrade the short channel effects dueto the Schottky barrier at the source. Hence, a bulk doping of1 × 1015/cm3 was chosen. Mono nickel silicide (NiSi) is usedto form the Schottky source/drain regions. Nickel silicide hasa ϕbe ∼ 0.6–0.65 eV(ϕbh ∼ 0.45–0.5 eV) [33] which is highenough to ensure that the injection mechanism for both carriersfrom the source into the channel is limited by tunneling throughthe Schottky barrier. NiSi offers the advantage of less siliconconsumption than conventional silicides such as TiSi2 andCoSi2 to achieve the same sheet resistance, thereby minimizingvoid formation. NiSi is also attributed to have the same sheetresistance irrespective of linewidth as well as thermal stabilityover a wide temperature range of 400 ◦C–650 ◦C which makesit an attractive candidate for the demonstration of the STS-FET[34]–[36].

For the successful operation of the device, the silicide/siliconinterface must lie below the gate. Lateral silicidation is veryimportant for conventional Schottky transistors as well. A SOIsubstrate assists in this process as there is limited siliconavailable in the vertical direction and also helps in avoiding voidformation [37]. By the deposition of the thickness of nickel,which is larger than that required for the full silicidation of theSOI film, we ensure that there will be some lateral growth ofsilicide as nickel is the dominating diffusive species. The extentof lateral silicidation can be controlled by the nickel thicknessdeposited before silicidation [37]. Lateral growth distances of800 and 680 Å with no voids were achieved for silicon film

Fig. 8. Full silicidation of the SOI film using NiSi and lateral encroachmentof the film under the gate.

Fig. 9. IS–VG and ID–VG characteristics of (a) STS-pFET and(b) STS-nFET. The ambipolar behavior is due to the insufficient dopantconcentration of the drain side pocket. The effective channel length is reducedto about 0.12 μm due to lateral encroachment of NiSi under the gate.

thicknesses of 90 and 50 nm, respectively, which ensured thatthe source channel Schottky junction is under the gate as seenin Fig. 8.

Two different gate oxide thicknesses of 48 and 31 Å werechosen to study the effect of gate oxide thicknesses on deviceperformance. For the drain side pocket, a high dose of As forthe nFET and BF2 for the pFET was implanted with a large tiltangle of 55◦. The dopants were activated at 1000 ◦C for 5 s.The gate polysilicon thickness is chosen to be the same as thatof the SOI film to ensure that the gate is fully silicided. The Sifilm and gate polysilicon were then fully Ni silicided at 450 ◦Cfor 10 min while the As/B is conjectured to redistribute andpileup occurs at the silicide/silicon interface [22]. Conventionalprocess steps were followed for passivation and metallization.

B. Device Performance

Fig. 9 shows the ID–VG performance of an n-type andp-type STS-FET with gate length of 0.2 μm. It must be notedthat, due to the lateral encroachment of NiSi under the spacerand gate, the effective channel length is close to 0.1 μm. A goodagreement between the experimental data and the simulation, asshown in the following paragraph, demonstrates that the sub-threshold current is controlled by Schottky barrier tunneling.

To confirm the asymmetric nature of the device due tothe presence of the drain side pocket, reverse mode measure-ments were carried out by interchanging the source and drainterminals. In reverse mode, the highly doped pocket at the drain

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Fig. 10. Reverse mode IS–VG characteristics of the STS-pFET. The differ-ence as compared to the forward mode measurement confirms the asymmetricnature of the device.

Fig. 11. IOFF (VG = 0 V) for the STS-nFET at different VD’s withand without a highly doped (W = 10 nm, ND = 1 × 1020/cm3) n+ drainpocket. The experimental curve confirms the hypothesis that the dopant con-centration of the drain pocket is not high enough.

side makes the carrier injection similar to a conventional FET,and the source side Schottky barrier acts as a drain junctionresistance. This is confirmed by our reverse measurement forthe STS-pFET as shown in Fig. 10. The current is no longertunneling limited only as observed in the forward mode mea-surement in Fig. 9(a). This is also confirmed by our devicesimulations which yield a similar behavior in the reverse mode.

The increase in drain current at low VG in Fig. 9 suggests thatthe pocket at the drain is not as highly doped as required. Thiscurrent is caused by the reverse back injection of carriers whichare injected from the drain to the channel due to a reversal ofthe Schottky junction field at the drain end. As the doping ofthe drain side pocket is increased, the gate voltage at whichthis back injection current begins to flow decreases. When thedoping is high enough for the pocket to stay partially depletedeven at low gate voltages (∼1 × 1020/cm3 for a pocket widthof 10 nm), this ambipolar reverse current is eliminated. This hasbeen confirmed by our simulations which show the reduction inoff-current with the increase of the n-type dopants at the drainside for the STS nFET as shown in Fig. 11.

The functional dependence of the subthreshold swing on ox-ide thickness is shown experimentally for two oxide thicknesses

Fig. 12. Experimental and simulated subthreshold swing with different gateoxide thicknesses. The fit is linear with the equation as listed inset.

in Fig. 12. This confirms that the dependence of the swing oneffective oxide thickness is similar to the trend in simulations.Thus, high-k dielectrics with EOT < 10 Å can be used toobtain a subthreshold swing of close to 100 mV/dec with highimmunity to short channel effects and reduced temperaturedependence.

ID–VD characteristics of the STS nFET and pFET are shownin Fig. 13. ION (@VGT = 1.0 V) = 90 μA/μm is obtainedfor both nFET and pFET. The magnitude of this on-current islargely determined by the tunneling resistance of the sourceside Schottky junction. The barrier height of the NiSi/siliconSchottky junction for holes (ϕbh ∼ 0.45–0.5 eV) is less thanthat of the electrons (ϕbe ∼ 0.6–0.65 eV). However, the effec-tive mass of holes for Schottky tunneling is higher as com-pared to electrons, which results in an on-current of similarmagnitude.

Compared to some previously published Schottky FETs, theSTS-FETs show improved behavior in the linear region ofthe ID–VD curves. This is attributed to the presence of thedoped pocket at the drain side which eliminates the potentialdrop at the drain side Schottky junction, thus making it like aconventional MOSFET drain junction. The slight degradationin the linear region can be improved by increasing the dopantconcentration in the drain side pocket. This can be clearly seenin Fig. 14 where for a pocket width of 10 nm and donor con-centration of 1 × 1020/cm3, the potential drop is completelyeliminated and VDsat is also reduced.

Thus, a high pocket concentration on the drain side has atwofold advantage: 1) a reduction in off-current caused by theback injection of holes from the drain into the channel and also2) an improvement in linear region characteristics by the elimi-nation of potential drop at the drain side Schottky junction. Theasymmetric nature of the STS-FET has been shown to improvethe performance of the device while maintaining the advantagesof having a tunneling source injection mechanism as comparedto a diffusion mechanism. This high immunity to short channeleffects and improved output resistance performance makes itan excellent choice for highly scaled analog and mixed-modeapplications.

V. CONCLUSION

An asymmetric Schottky tunneling source MOSFET utiliz-ing the concept of gate-controlled Schottky barrier tunneling

98 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 1, JANUARY 2009

Fig. 13. ID–VD characteristics of (a) STS-pFET and (b) STS-nFET. The behavior in the linear region can be improved by increasing the dopant concentrationof the drain side pocket.

Fig. 14. Improvement in the linear region of the ID–VD characteristics of asimulated STS-nFET due to the presence of the highly doped drain side pocket(W = 10 nm, ND = 1 × 1020/cm3).

has been examined and successfully demonstrated. A tradeoffis established with respect to the barrier height of the sili-cide/silicon Schottky junction at the source end. One of theunique features of the STS-FET is that, for the tunneling-limited regime, the subthreshold swing is linearly proportionalto the oxide thickness and is a weak function of temperature.Simulations also show that the STS-FET has a better shortchannel immunity in terms of smaller DIBL, reduced thresholdrolloff, and increased output resistance. It is also importantto have a “conventional” drain junction for good linear I–Vcharacteristics and the elimination of leakage current which isdue to the back injection of carriers. The asymmetric natureof the device has been shown to improve the transfer charac-teristics as well as the linear characteristics of the device ascompared to conventional Schottky FETs. The experimentaldata obtained from the devices fabricated confirm that themechanism of current injection is Schottky barrier tunnelingas also the dependence of tunneling on oxide thickness. Gateoverlapping Schottky source/drain junctions achieved usingSOI substrates are necessary to prevent degradation due to thepotential drop in the region under the spacer which is not sili-cided. The rigorous control of pocket doping and width wouldensure the elimination of reverse leakage current and alsoimproved linear characteristics for the STS-FET. This makesthe proposed asymmetric Schottky tunneling source MOSFETa promising candidate for sub-50-nm devices and mixed-modeapplications.

ACKNOWLEDGMENT

The fabrication work was performed at the StanfordNanofabrication Facility of NNIN.

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Ritesh Jhaveri (S’03) received the B.Tech. degreein engineering physics from the Indian Institute ofTechnology, Mumbai, India, where his final-yearproject involved working on molecular electronics.He is currently working toward the Ph.D. degree inelectrical engineering in the Electrical EngineeringDepartment, University of California, Los Angeles.

The primary focus of his research is a novelSchottky CMOS device design for analog and mixed-mode applications beyond the sub-65-nm technologynodes. His research interests also include novel tun-

neling transistors, process development, and asymmetric device structures.

Venkatagirish Nagavarapu (S’01) received theB.Tech. degree in electrical engineering from theIndian Institute of Technology, Mumbai, India, in2001, where the focus of his senior-year projectwas RF modeling. Since then, he has been workingtoward the Ph.D. degree in semiconductor devicephysics with Prof. Jason Woo in electrical engi-neering in the Electrical Engineering Department,University of California, Los Angeles.

He is currently working on novel asymmetric de-vice structures and transistor design for high perfor-

mance to meet scaling challenges beyond the sub-65-nm domain. His otherresearch interests include low temperature device behavior and characteriza-tion, study and minimization of gate leakage in MOS devices, and novel dopantannealing methods.

Jason C. S. Woo (S’83–M’87–SM’97–F’05) re-ceived the B.A.Sc. (Hons.) degree in engineeringscience from the University of Toronto, Toronto, ON,Canada, in 1981 and the M.S. and Ph.D. degreesin electrical engineering from Stanford University,Stanford, CA, in 1982 and 1987, respectively.

He has been with the Electrical Engineering De-partment, University of California, Los Angeles,since 1987, where he is currently a Professor. He hasauthored or coauthored more than 100 papers in tech-nical journals and refereed conference proceedings.

Prof. Woo served on the IEEE International Electron Devices MeetingProgram Committee from 1989 to 1990 and from 1994 to 1996, and was thePublicity Vice Chairman in 1992 and 1993. He is the Workshop Chairman andhas been a Technical Committee member of the VLSI Technology Symposiumsince 1992. Since 1993, he has been on the IEEE SOI Conference Committeeand was the Technical Program Chairman for the conference in 1999. He hasalso been appointed to serve as the Chair of the IEEE Electronic Device Societyad hoc committee on short courses.